TWI702674B - 半導體晶片背面圖案與正面圖案精確對準的方法 - Google Patents

半導體晶片背面圖案與正面圖案精確對準的方法 Download PDF

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TWI702674B
TWI702674B TW107122360A TW107122360A TWI702674B TW I702674 B TWI702674 B TW I702674B TW 107122360 A TW107122360 A TW 107122360A TW 107122360 A TW107122360 A TW 107122360A TW I702674 B TWI702674 B TW I702674B
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wafer
preparing
semiconductor element
carrier
carrier wafer
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TW201911452A (zh
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張磊
宏勇 薛
王健
寧潤濤
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大陸商萬民半導體（澳門）有限公司
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Abstract

本發明包括製備半導體元件晶圓；在半導體元件晶圓的第一邊上製備複數個第一對齊標識；製備第一導電類型的第一圖案；在半導體元件晶圓的第二邊上製備複數個第二對齊標識；透過將載體晶圓連接到半導體元件晶圓，製備一個連接晶圓；在載體晶圓的自由邊上製備複數個第三對齊標識；使用研磨製程；製備複數個元件結構組件；除去載體晶圓；使用研磨製程和退火製程；使用金屬化製程並使用分離製程。

Description

半導體晶片背面圖案與正面圖案精確對準的方法
本發明主要涉及一種半導體晶片背面圖案與正面圖案精確對準的方法。更確切地說，本發明涉及引用三組或更多組對準標記的方法。
反向傳導的絕緣閘雙極電晶體(RC-IGBT)的製備要求在矽晶圓背面形成N和P交替的圖案。背面圖案無法準確地對齊正面圖案，這是因為矽晶圓在背面圖案製程中，正面朝下(無法接觸正面)。傳統的製備方法在矽晶圓上使用了一個缺口，在背面圖案和正面圖案之間引入了較大的對齊誤差(20微米的數量級)。
本發明參照三組或三組以上的對齊標識。提高了對齊精度，並且僅作為單獨的正面製程也可以良好運行。例如，利用i-線步進器的話，未對齊小於120奈米，利用DUV步進器的話，未對齊小於60奈米。
由於提高了對齊，本發明可以用於製備需要精密誤差具有複雜元件結構的半導體元件。本發明還可以用於在需要準確對齊到正面的背面上進行金屬圖案刻蝕製程。
本發明提出了一種半導體元件的製備方法。本方法包括製備半導體元件晶圓；在半導體元件晶圓的第一邊上製備複數個第一對齊標識；製備第一導電類型的第一圖案；在半導體元件晶圓的第二邊上製備複數個第二對齊標識；透過將載體晶圓連接到半導體元件晶圓上製備一個連接晶圓；在載體晶圓的自由邊緣上製備複數個第三對齊標識；利用研磨製程；製備複數個元件結構組件；除去載體晶圓；利用注入製程和退火製程；使用金屬化製程並使用分離製程。
將載體晶圓連接到半導體元件晶圓上的步驟有利於處理減薄的半導體元件晶圓。
為了達到上述目的，本發明提供了一種半導體元件的製備方法，該方法包括以下步驟：製備一個半導體元件晶圓，包括第一邊和與對著第一邊的第二邊；在半導體元件晶圓的第一邊上製備複數個第一對齊標識；在半導體元件晶圓的第一邊上製備第一導電類型的第一圖案，參考複數個第一對齊標識；在半導體元件晶圓的第二邊上製備複數個第二對齊標識，參考複數個第一對齊標識；透過將載體晶圓連接到半導體元件晶圓的第一邊上，形成一個連接晶圓，載體晶圓包括一個連接邊和一個自由邊；在載體晶圓的自由邊上，製備複數個第三對齊標識，參考複數個第二對齊標識； 對連接晶圓的半導體元件晶圓的第二邊使用研磨製程，減小半導體元件晶圓的厚度，使研磨表面裸露出來；在研磨表面上製備複數個元件結構組件，形成連接處理晶圓；從連接處理晶圓上除去載體晶圓，構成一個處理晶圓；利用注入製程和退火製程，在第一導電類型的第一圖案附近形成第二導電類型的複數個區域；並且利用金屬化製程，製備一個產品晶圓。
優選地，在使用金屬化製程之後，對產品晶圓使用分離製程，形成複數個單獨的半導體元件。
優選地，其中複數個單獨的半導體元件是複數個反向傳導的絕緣閘雙極電晶體。
優選地，其中載體晶圓包括一個矽基板和一個氧化矽層；其中氧化矽層位於載體晶圓的連接邊上；並且其中透過將載體晶圓連接到半導體元件晶圓第一邊上製備連接晶圓的步驟包括：透過將載體晶圓的氧化矽層連接到半導體元件晶圓的第一邊上，形成連接晶圓。
優選地，其中從連接處理晶圓上除去載體晶圓的步驟包括以下子步驟：研磨掉載體晶圓的矽基板；並且剝去載體晶圓的氧化矽層。
優選地，其中半導體元件晶圓包括一個位於半導體元件晶圓第一邊上的氧化矽層；其中載體晶圓包括一個矽基板和一個氧化矽層；其中氧化矽層位於載體晶圓的連接邊上；以及其中透過將載體晶圓連接到半導體元件晶圓第一邊上製備連接晶圓的步驟包括：透過將載體晶圓的氧化矽層連接到半導體元件晶圓的氧化矽層，形成連接晶圓。
優選地，其中從連接處理晶圓上除去載體晶圓的步驟包括以下子步驟：研磨掉載體晶圓的矽表面；並且剝去載體晶圓的氧化矽層；並且其中半 導體元件的製備方法還包括，在以下步驟之後從連接處理晶圓上除去載體晶圓，剝去半導體元件晶圓的氧化矽層。
優選地，其中在研磨表面上製備複數個元件結構組件的步驟包括以下子步驟：製備第二導電類型的複數個第一區域；製備第一導電類型的複數個第二區域；製備複數個源極區；並且製備複數個閘極區。
優選地，在研磨表面上製備複數個元件結構之間的步驟之前：在研磨表面上製備複數個第四對齊標識，參考複數個第三對齊標識。
優選地，其中在研磨表面上製備複數個元件結構組件的步驟包括以下子步驟：製備第二導電類型的複數個第一區域，參考複數個第四對齊標識；製備第一導電類型的複數個第二區域，參考複數個第四對齊標識；製備複數個源極區，參考複數個第四對齊標識；並且製備複數個閘極區，參考複數個第四對齊標識。
100~130:組塊
202:第一邊
204:第二邊
208:連接晶圓
210:半導體元件晶圓
212:第一對齊標識
214:第一圖案
222:第二對齊標識
229:載體晶圓
230:矽基板
231:連接邊
233:自由邊
236、314、334、336:矽氧化層
242:第三對齊標識
254:厚度
258:研磨表面
262:第四對齊標識
271:第一區域
273:第二區域
275:源極區
277:閘極區
284:區域
286:金屬層
293:連接處理晶圓
297:處理晶圓
299:產品晶圓
第1圖表示在本發明的實施例中半導體元件的製備製程流程圖。
第2A、2B、2C、2D、2E、2F、2G、2H、2I、2J、2K、2L、2M、2N和2O圖表示在本發明的實施例中第1圖所示的半導體元件的製備製程的剖面圖。
第3A及3B圖分別表示在本發明的實施例中兩個連接晶圓的剖面圖。
第1圖表示在本發明的實施例中，製備半導體元件的製程100的流程圖。製程100從組塊102開始。
在組塊102中，製備第2A圖所示的半導體元件晶圓210。在一個實施例中，半導體元件晶圓210是一個矽晶圓，直徑8英寸，厚度為725微米。在另一個實施例中，半導體元件晶圓210是一個直徑12英寸、厚775微米的矽晶圓。在本發明的實施例中，半導體元件晶圓210是一個單晶提拉矽(Cz)晶圓、磁場應用Cz(MCZ)晶圓、浮區融化矽(FZ)晶圓或外延(EPI)晶圓。半導體元件晶圓210具有第一邊202(例如正面)和第二邊204(例如背面)。第二邊204對著第一邊202。組塊102之後可以進行組塊104。
在組塊104中，第2A圖所示的複數個第一對齊標識212形成在半導體元件晶圓210的第一邊202上。組塊104之後可以進行組塊106。
在組塊106中，第一導電類型(例如N+)的第2B圖所示的第一圖案214可以形成在半導體元件晶圓210的第一邊202上，參考複數個第一對齊標識212。組塊106之後可以進行組塊108。
在組塊108中，翻轉第2C圖所示的半導體元件晶圓210。組塊108之後可以進行組塊110。
在組塊110中，第2C圖所示的複數個第二對齊標識222可以形成在半導體元件晶圓210的第二邊204上，參考複數個第一對齊標識212。
在本發明的實施例中，ASML 3DALIGNTM產品用於將第2C圖所示的複數個第二對齊標識222對齊到複數個第一對齊標識212上。組塊110之後可以進行組塊112。
在組塊112中，翻轉第2D圖所示的半導體元件晶圓210。組塊112之後可以進行組塊114。
在組塊114中，透過將載體晶圓229連接到半導體元件晶圓210的第一邊202上，形成第2E圖所示的連接晶圓208。載體晶圓229有一個連接邊231和一個自由邊233。
在一個實施例中，載體晶圓229擁有第3A圖所示的矽基板230和第3A圖所示的矽氧化層336。矽氧化層336位於載體晶圓229的連接邊231上。透過將載體晶圓229的矽氧化層336連接到半導體元件晶圓210的第一邊202(在一個實施例中，由矽製成)上，形成連接晶圓208。第2E圖所示的矽氧化層236僅包含第3A圖所示的矽氧化層336。
在另一個實施例中，生長第3B圖所示的矽氧化層314，並直接連接到半導體元件晶圓210的第一邊202上。載體晶圓229具有第3B圖所示的矽基板230和第3B圖所示的矽氧化層334。矽氧化層334位於載體具有229的連接邊231上。透過將載體晶圓229的矽氧化層334連接到矽氧化層314上，形成連接晶圓208。第2E圖所示的矽氧化層236包含第3B圖所示的矽氧化層314和矽氧化層334。組塊114之後可以進行組塊116。
在組塊116中，第2F圖所示的複數個第三對齊標識242形成在載體晶圓229的自由邊233上，參考複數個第二對齊標識222。組塊116之後可以進行組塊118。
在組塊118中，翻轉第2G圖所示的連接晶圓208。組塊118之後可以進行組塊120。
在組塊120中，對連接晶圓208的半導體元件晶圓的第2G圖所示的第二邊204進行研磨。縮減半導體元件晶圓第2H圖所示的厚度254。第2H圖所示的研磨表面258裸露出來。組塊120之後可以進行組塊122。
第2I圖表示可選的處理步驟。(可選)複數個第四對齊標識262(如圖中虛線所示)形成在研磨表面258上，參考複數個第三對齊標識222。
在組塊122中，複數個元件結構組件形成在研磨表面上，形成第2J圖所示的連接處理晶圓。複數個元件結構組件包括第二導電類型(例如P)的複數個第一區域271、第一導電類型(例如N+)的複數個第二區域273、複數個源極區275以及複數個閘極區277。
在本發明的實施例中，複數個元件結構組件都參考複數個第四對齊標識262。組塊122之後可以進行組塊124。
在組塊124中，從第2J圖所示的連接處理晶圓293上除去載體晶圓，構成第2L圖所示的處理晶圓297。在一個實施例中，除去矽基板230(例如透過研磨製程)，然後除去第2K圖所示的矽氧化層236(例如透過化學刻蝕製程)。組塊124之後可以進行組塊126。
在組塊126中，利用注入製程和退火製程，形成第二導電類型(例如P)的第2M圖所示的複數個區域284，靠近第一導電類型(例如N+)的第一圖案214。在一個實施例中，不需要圖案處理就能形成複數個區域284。組塊126之後可以進行組塊128。
在組塊128中，利用金屬化製程，形成產品晶圓299第2N圖所示的金屬層286。組塊128之後可以進行組塊130。
在組塊130中，對產品晶圓299進行第2O圖所示的分離製程，從而形成複數個單獨的半導體元件。在本發明的實施例中，複數個單獨的半導體元件是複數個反向傳導的絕緣閘雙極電晶體(RC-IGBT)。
本領域的技術人員應理解所述的實施例可能存在修正。例如載體晶圓的厚度可以變化。在本發明的範圍內，還可能存在各種修正和變化。本發明由所附的申請專利範圍限定。
100~130:組塊

Claims (10)

  1. 一種半導體元件的製備方法，其包括以下步驟：製備一半導體元件晶圓，包括第一邊和與該第一邊相對的第二邊；在該半導體元件晶圓的該第一邊上製備複數個第一對齊標識；在該半導體元件晶圓的該第一邊上製備第一導電類型的第一圖案，參考該複數個第一對齊標識；在該半導體元件晶圓的第二邊上製備複數個第二對齊標識，參考該複數個第一對齊標識；透過將載體晶圓連接到該半導體元件晶圓的第一邊上，形成一連接晶圓，該載體晶圓包括一連接邊和一自由邊；在該載體晶圓的該自由邊上，製備複數個第三對齊標識，參考該複數個第二對齊標識；對該連接晶圓的該半導體元件晶圓的該第二邊使用研磨製程，減小該半導體元件晶圓的厚度，使研磨表面裸露出來；在該研磨表面上製備複數個元件結構組件，形成連接處理晶圓；從該連接處理晶圓上除去該載體晶圓，構成一處理晶圓；利用注入製程和退火製程，形成第二導電類型的複數個區域，在該第一導電類型的該第一圖案附近；以及利用金屬化製程，製備一產品晶圓。
  2. 如請求項1所述的半導體元件的製備方法，其中， 在使用金屬化製程之後，對該產品晶圓使用分離製程，形成複數個單獨的半導體元件。
  3. 如請求項2所述的半導體元件的製備方法，其中，該複數個單獨的半導體元件係為複數個反向傳導的絕緣閘雙極電晶體。
  4. 如請求項1所述的半導體元件的製備方法，，其中該載體晶圓包括一矽基板和一氧化矽層；其中該載體晶圓的氧化矽層位於該載體晶圓的該連接邊上；以及其中透過將該載體晶圓連接到該半導體元件晶圓的該第一邊上以製備該連接晶圓的步驟包括：透過將該載體晶圓的氧化矽層連接到該半導體元件晶圓的該第一邊上，形成該連接晶圓。
  5. 如請求項4所述的半導體元件的製備方法，其中，從該連接處理晶圓上除去該載體晶圓的步驟包括以下子步驟：研磨掉該載體晶圓的該矽基板；並且剝去該載體晶圓的氧化矽層。
  6. 如請求項1所述的半導體元件的製備方法，其中該半導體元件晶圓包括一位於該半導體元件晶圓的該第一邊上的氧化矽層；其中該載體晶圓包括一矽基板和一氧化矽層；其中該載體晶圓的氧化矽層位於該載體晶圓的該連接邊上；以及 其中透過將該載體晶圓連接到該半導體元件晶圓的該第一邊上製備該連接晶圓的步驟包括：透過將該載體晶圓的氧化矽層連接到該半導體元件晶圓的氧化矽層，形成該連接晶圓。
  7. 如請求項6所述的半導體元件的製備方法，其中從該連接處理晶圓上除去該載體晶圓的步驟包括以下子步驟：研磨掉該載體晶圓的矽表面；以及剝去該載體晶圓的氧化矽層；以及其中該半導體元件的製備方法還包括，在以下步驟之後，從該連接處理晶圓上除去該載體晶圓：剝去該半導體元件晶圓的氧化矽層。
  8. 如請求項1所述的半導體元件的製備方法，其中，在該研磨表面上製備該複數個元件結構組件的步驟包括以下子步驟：製備該第二導電類型的複數個第一區域；製備該第一導電類型的複數個第二區域；製備複數個源極區；以及製備複數個閘極區。
  9. 如請求項1所述的半導體元件的製備方法，其中，在該研磨表面上製備該複數個元件結構的步驟之前：在該研磨表面上製備複數個第四對齊標識，參考該複數個第三對齊標識。
  10. 如請求項9所述的半導體元件的製備方法，其中，在該研磨表面上製備該複數個元件結構組件的步驟包括以下子步驟：製備該第二導電類型的複數個第一區域，參考該複數個第四對齊標識；製備該第一導電類型的複數個第二區域，參考該複數個第四對齊標識；製備複數個源極區，參考該複數個第四對齊標識；以及製備複數個閘極區，參考該複數個第四對齊標識。
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