CN109216169B - 半导体晶片背面图案与正面图案精确对准的方法 - Google Patents

半导体晶片背面图案与正面图案精确对准的方法 Download PDF

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CN109216169B
CN109216169B CN201810685615.0A CN201810685615A CN109216169B CN 109216169 B CN109216169 B CN 109216169B CN 201810685615 A CN201810685615 A CN 201810685615A CN 109216169 B CN109216169 B CN 109216169B
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semiconductor device
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alignment marks
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CN109216169A (zh
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张磊
薛宏勇
王健
宁润涛
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Alpha and Omega Semiconductor Cayman Ltd
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Abstract

本发明包括制备半导体器件晶圆；在半导体器件晶圆的第一边上制备第一多个对齐标识；制备第一导电类型的第一图案；在半导体器件晶圆的第二边上制备第二多个对齐标识；通过将载体晶圆连接到半导体器件晶圆，制备一个连接晶圆；在载体晶圆的自由边上制备第三多个对齐标识；使用研磨工艺；制备多个器件结构组件；除去载体晶圆；使用研磨工艺和退火工艺；使用金属化工艺并使用分离工艺。

Description

半导体晶片背面图案与正面图案精确对准的方法
技术领域
本发明主要涉及一种半导体晶片背面图案与正面图案精确对准的方法。更确切地说，本发明涉及引用三组或更多组对准标记的方法。
背景技术
反向传导的绝缘栅双极晶体管(RC-IGBT)的制备要求在硅晶圆背面形成N和P交替的图案。背面图案无法准确地对齐正面图案，这是因为硅晶圆在背面图案工艺中，正面朝下(无法接触正面)。传统的制备方法在硅晶圆上使用了一个缺口，在背面图案和正面图案之间引入了较大的对齐误差(20微米的数量级)。
本发明参照三组或三组以上的对齐标识。提高了对齐精度，并且仅作为单独的正面工艺也可以良好运行。例如，利用i-线步进器的话，未对齐小于120纳米，利用DUV步进器的话，未对齐小于60纳米。
由于提高了对齐，本发明可以用于制备需要精密误差具有复杂器件结构的半导体器件。本发明还可以用于在需要准确对齐到正面的背面上进行金属图案刻蚀工艺。
发明内容
本发明提出了一种半导体器件的制备方法。本方法包括制备半导体器件晶圆；在半导体器件晶圆的第一边上制备第一多个对齐标识；制备第一的导电类型的第一图案；在半导体器件晶圆的第二边上制备第二多个对齐标识；通过将载体晶圆连接到半导体器件晶圆上制备一个连接晶圆；在载体晶圆的自由边缘上制备第三多个对齐标识；利用研磨工艺；制备多个器件结构组件；除去载体晶圆；利用注入工艺和退火工艺；使用金属化工艺并使用分离工艺。将载体晶圆连接到半导体器件晶圆上的步骤有利于处理减薄的半导体器件晶圆。
为了达到上述目的，本发明提供了一种半导体器件的制备方法，该方法包括以下步骤:
制备一个半导体器件晶圆，包括第一边和第一边对着的第二边；
在半导体器件晶圆的第一边上制备第一多个对齐标识；
在半导体器件晶圆的第一边上制备第一导电类型的第一图案，参考第一多个对齐标识；
在半导体器件晶圆的第二边上制备第二多个对齐标识，参考第一多个对齐标识；
通过将载体晶圆连接到半导体器件晶圆的第一边上，形成一个连接晶圆，载体晶圆包括一个连接边和一个自由边；
在载体晶圆的自由边上，制备第三多个对齐标识，参考第二多个对齐标识；
对连接晶圆的半导体器件晶圆的第二边使用研磨工艺，减小半导体器件晶圆的厚度，使研磨表面裸露出来；
在研磨表面上制备多个器件结构组件，形成连接处理晶圆；
从连接处理晶圆上除去载体晶圆，构成一个处理晶圆；
利用注入工艺和退火工艺，形成第二导电类型的多个区域，在第一导电类型的第一图案附近；并且
利用金属化工艺，制备一个产品晶圆。
优选地，在使用金属化工艺之后，对产品晶圆使用分离工艺，形成多个单独的半导体器件。
优选地，其中多个单独的半导体器件是多个反向超导的绝缘栅双极晶体管。
优选地，其中载体晶圆包括一个硅衬底和一个氧化硅层；其中氧化硅层位于载体晶圆的连接边上；并且其中通过将载体晶圆连接到半导体器件晶圆第一边上制备连接晶圆的步骤包括：通过将载体晶圆的氧化硅层连接到半导体器件晶圆的第一边上，形成连接晶圆。
优选地，其中从连接处理晶圆上除去载体晶圆的步骤包括以下子步骤：研磨掉载体晶圆的硅衬底；并且剥去载体晶圆的氧化硅层。
优选地，其中半导体器件晶圆包括一个位于半导体器件晶圆第一边上的氧化硅层；其中载体晶圆包括一个硅衬底和一个氧化硅层；其中氧化硅层位于载体晶圆的连接边上；以及其中通过将载体晶圆连接到半导体器件晶圆第一边上制备连接晶圆的步骤包括：通过将载体晶圆的氧化硅层连接到半导体器件晶圆的氧化硅层，形成连接晶圆。
优选地，其中从连接处理晶圆上除去载体晶圆的步骤包括以下子步骤：研磨掉载体晶圆的硅表面；并且剥去载体晶圆的氧化硅层；并且其中半导体器件的制备方法还包括，在以下步骤之后从连接处理晶圆上除去载体晶圆，剥去半导体器件晶圆的氧化硅层。
优选地，其中在研磨表面上制备多个器件结构组件的步骤包括以下子步骤：制备第二导电类型的第一多个区域；制备第一导电类型的第二多个区域；制备多个源极区；并且制备多个栅极区。
优选地，在研磨表面上制备多个器件结构之间的步骤之前：在研磨表面上制备第四多个对齐标识，参考第三多个对齐标识。
优选地，其中在研磨表面上制备多个器件结构组件的步骤包括以下子步骤：制备第二导电类型的第一多个区域，参考第四多个对齐标识；制备第一导电类型的第二多个区域，参考第四多个对齐标识；制备多个源极区，参考第四多个对齐标识；并且制备多个栅极区，参考第四多个对齐标识。
附图说明
图1表示在本发明的示例中半导体器件的制备工艺流程图。
图2A，2B，2C，2D，2E，2F，2G，2H，2I，2J，2K，2L，2M，2N和2O表示在本发明的示例中图1所示的半导体器件的制备工艺的剖面图。
图3A和3B分别表示在本发明的示例中两个连接晶圆的剖面图。
具体实施方式
图1表示在本发明的示例中，制备半导体器件的工艺100的流程图。工艺100从102组块开始。
在102组块中，制备图2A所示的半导体器件晶圆210。在一个示例中，半导体器件晶圆210是一个硅晶圆，直径8英寸，厚度为725微米。在另一个示例中，半导体器件晶圆210是一个直径12英寸、厚775微米的硅晶圆。在本发明的示例中，半导体器件晶圆210是一个单晶提拉硅(Cz)晶圆、磁场应用Cz(MCZ)晶圆、浮区融化硅(FZ)晶圆或外延(EPI)晶圆。半导体器件晶圆210具有第一边202(例如正面)和第二边204(例如背面)。第二边204对着第一边202。组块102之后可以进行组块104。
在组块104中，图2A所示的第一多个对齐标识212形成在半导体器件晶圆210的第一边202上。组块104之后可以进行组块106。
在组块106中，第一导电类型(例如N+)的图2B所示的第一图案214可以形成在半导体器件晶圆210的第一边202上，参考第一多个对齐标识212。组块106之后可以进行组块108。
在组块108中，翻转图2C所示的半导体器件晶圆210。组块108之后可以进行组块110。
在组块110中，图2C所示的第二多个对齐标识222可以形成在半导体器件晶圆210的第二边204上，参考第一多个对齐标识212。
在本发明的示例中，ASML 3DALIGNTM产品用于将图2C所示的第二多个对齐标识222对齐到第一多个对齐标识212上。组块110之后可以进行组块112。
在组块112中，翻转图2D所示的半导体器件晶圆210。组块112之后可以进行组块114。
在组块114中，通过将载体晶圆229连接到半导体器件晶圆210的第一边202上，形成图2E所示的连接晶圆208。载体晶圆229有一个连接边231和一个自由边233。
在一个示例中，载体晶圆229拥有图3A所示的硅衬底230和图3A所说的氧化层336。硅氧化层336位于载体晶圆229的连接边231上。通过将载体晶圆229的硅氧化层336连接到半导体器件晶圆210的第一边202(在一个示例中，由硅制成)上，形成连接晶圆208。图2E所示的硅氧化层236仅包含图3A所示的硅氧化层336。
在另一个示例中，生长图3B所示的硅氧化层314，并直接连接到半导体器件晶圆210的第一边202上。载体晶圆229具有图3B所示的硅衬底230和图3B所示的硅氧化层334。硅氧化层334位于载体具有229的连接边231上。通过将载体晶圆229的硅氧化层334连接到硅氧化层314上，形成连接晶圆208。图2E所示的硅氧化层236包含图3B所示的硅氧化层314和硅氧化层334。组块114之后可以进行组块116。
在组块116中，图2F所示的第三多个对齐标识242形成在载体晶圆229的自由边233上，参考第二多个对齐标识222。组块116之后可以进行组块118。
在组块118中，翻转图2G所示的连接晶圆208。组块118之后可以进行组块120。
在组块120中，对连接晶圆208的半导体器件晶圆的图2G所示的第二边204进行研磨。缩减半导体器件晶圆图2H所示的厚度254。图2H所示的研磨表面258裸露出来。组块120之后可以进行组块122。
图2I表示可选的处理步骤。(可选)第四多个对齐标识262(图中虚线所示)形成在研磨表面258上，参考第三多个对齐标识222。
在组块122中，多个器件结构组件形成在研磨表面上，形成图2J所示的连接处理晶圆。多个器件结构组件包括第二导电类型(例如P)的第一多个区域271、第一导电类型(例如N+)的第二多个区域273、多个源极区275以及多个栅极区277。
在本发明的示例中，多个器件结构组件都参考第四多个对齐标识262。组块122之后可以进行组块124。
在组块124中，从图2J所示的连接处理晶圆293上除去载体晶圆，构成图2L所示的处理晶圆297。在一个示例中，除去硅衬底230(例如通过研磨工艺)，然后除去图2K所示的硅氧化层236(例如通过化学刻蚀工艺)。组块124之后可以进行组块126。
在组块126中，利用注入工艺和退火工艺，形成第二导电类型(例如P)的图2M所示的多个区域284，靠近第一导电类型(例如N+)的第一图案214。在一个示例中，不需要图案处理就能形成多个区域284。组块126之后可以进行组块128。
在组块128中，利用金属化工艺，形成产品晶圆299图2N所示的金属层286。组块128之后可以进行组块130。
在组块130中，对器件晶圆299进行图2O所示的分离工艺，从而形成多个单独的半导体器件。在本发明的示例中，多个单独的半导体器件是多个反向传到的绝缘栅双极晶体管(RC-IGBT)。
本领域的技术人员应理解所述的实施例可能存在修正。例如载体晶圆的厚度可以变化。在本发明的范围内，还可能存在各种修正和变化。本发明由所附的权利要求书限定。

Claims (7)

1.一种半导体器件的制备方法，其特征在于，该方法包括以下步骤:
制备一个半导体器件晶圆，包括第一边和第一边对着的第二边；
在半导体器件晶圆的第一边上制备第一多个对齐标识；
在半导体器件晶圆的第一边上制备第一导电类型的第一图案，参考第一多个对齐标识；
在半导体器件晶圆的第二边上制备第二多个对齐标识，参考第一多个对齐标识；
通过将载体晶圆连接到半导体器件晶圆的第一边上，形成一个连接晶圆，载体晶圆包括一个连接边和一个自由边；
在载体晶圆的自由边上，制备第三多个对齐标识，参考第二多个对齐标识；
对连接晶圆的半导体器件晶圆的第二边使用研磨工艺，减小半导体器件晶圆的厚度，使研磨表面裸露出来；
在研磨表面上制备多个器件结构组件，形成连接处理晶圆；
从连接处理晶圆上除去载体晶圆，构成一个处理晶圆；
利用注入工艺和退火工艺，形成第二导电类型的多个区域，在第一导电类型的第一图案附近；并且
利用金属化工艺，制备一个产品晶圆；
在研磨表面上制备多个器件结构组件的步骤之前：
在研磨表面上制备第四多个对齐标识，参考第三多个对齐标识；
其中在研磨表面上制备多个器件结构组件的步骤包括以下子步骤：
制备第二导电类型的第一多个区域，参考第四多个对齐标识；
制备第一导电类型的第二多个区域，参考第四多个对齐标识；
制备多个源极区，参考第四多个对齐标识；并且
制备多个栅极区，参考第四多个对齐标识。
2.如权利要求1所述的半导体器件的制备方法，其特征在于，
在使用金属化工艺之后，对产品晶圆使用分离工艺，形成多个单独的半导体器件。
3.如权利要求2所述的半导体器件的制备方法，其特征在于，
其中多个单独的半导体器件是多个反向超导的绝缘栅双极晶体管。
4.如权利要求1所述的半导体器件的制备方法，其特征在于，
其中载体晶圆包括一个硅衬底和一个氧化硅层；
其中氧化硅层位于载体晶圆的连接边上；并且
其中通过将载体晶圆连接到半导体器件晶圆第一边上制备连接晶圆的步骤包括：通过将载体晶圆的氧化硅层连接到半导体器件晶圆的第一边上，形成连接晶圆。
5.如权利要求4所述的半导体器件的制备方法，其特征在于，
其中从连接处理晶圆上除去载体晶圆的步骤包括以下子步骤：研磨掉载体晶圆的硅衬底；并且剥去载体晶圆的氧化硅层。
6.如权利要求1所述的半导体器件的制备方法，其特征在于，
其中半导体器件晶圆包括一个位于半导体器件晶圆第一边上的氧化硅层；
其中载体晶圆包括一个硅衬底和一个氧化硅层；
其中氧化硅层位于载体晶圆的连接边上；以及
其中通过将载体晶圆连接到半导体器件晶圆第一边上制备连接晶圆的步骤包括：通过将载体晶圆的氧化硅层连接到半导体器件晶圆的氧化硅层，形成连接晶圆。
7.如权利要求6所述的半导体器件的制备方法，其特征在于，
其中从连接处理晶圆上除去载体晶圆的步骤包括以下子步骤：
研磨掉载体晶圆的硅表面；并且
剥去载体晶圆的氧化硅层；并且
其中半导体器件的制备方法还包括，在以下步骤之后
从连接处理晶圆上除去载体晶圆，
剥去半导体器件晶圆的氧化硅层。
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