1259528 九、發明說明： 【發明所屬之技術領域】 本發明係有關一種半導體製程，特別是關於一種防止 晶圓在半導體製程中龜裂的方法。 【先前技術】 在半導體製程中，為使每一道步驟的圖案或材料彼此 吻合，在每一晶圓之非主動區域上形成一或多個對準記號 區域，每一對準記號區域内含有一或多個對準記號。一般 而吕，對準記號區域靠近晶圓的邊緣。之後，所有微影製 程之光罩即根據該對準記號來對準，例如使用一標線 ㈣icle)光料光顯影後形成多個晶粒區域，再藉由種^物 理或化學處理製作積體電路在該晶粒區域上。但在製程中 總是避免不了 -些不必要的粒子附著在該晶圓表面上，例 如灰塵，或者是為了得到一平整的表面，此時即需要研磨 該晶圓表面。一般而言，晶圓的正面為元件建置區，而背 面係在半導體後段製程才作研磨，然而，當使用研磨裝置 研磨該晶圓之背©時’由於在對準記號區域和元件區域的 應力不同，常造成晶圓龜裂。圖1A至圖斤為習知之半導體 後段製程，圖1A顯示一晶圓1〇包含元件區域1〇1及對準記 號區域102,其具有一正面1〇3及一背面1〇4,積體電路形 成在該正面103之元件區域〗01内，在該正面1〇3上之對準 記號區域102内含有多個對準記號1〇22。首先，在該元件 區域101上沉積-金屬層12 ’金屬蓋緣18則形成在該元件 1259528 區域101之邊緣，如圖1B所示，之後，沉積一墊層14在該 元件區域101及對準記號區域1 〇2上，如圖丨c所示，其中該 墊層14係為一墊氧化層。接著塗佈一光阻層16在該元件區 域ιοί上，經過微影製程後，該光阻層16形成多個溝渠17 在該元件區域101上，如圖1D所示。圖1]£係顯示沿著該溝 渠17向下蝕刻该墊層14，且因而形成邊襯15。最後，圖1F 顯示一研磨裝置11研磨該晶圓10之背面1〇4，由於在該元 件區域101和對準記號區域102之應力不同，當研磨裝 研磨該晶圓10之背面104時，在該金屬蓋緣18附近即產生 龜裂19。此現象在晶圓10愈薄時或元件區域1〇1與對準記 號區域102的地形起伏差異愈大時愈嚴重。 因此，一種防止晶圓在半導體製程中龜裂的方法乃為 所冀。 … 【發明内容】 本發明的目的，在於提供一種防止晶圓在半導體製程 中龜裂的方法。該晶圓具有—正面及—背面，該正面上形 成有元件區域及對準記號區域，該元件區域上沉積有―金 屬層，並在該元件區域之邊緣形成金屬蓋緣，該方法包括 沉積一墊層在該元件區域及對準記號區域上，塗佈一厚光 阻層在該元件區域及對準記號區域上，對該厚光阻層施予 U汾衣私，且在该對準記號區域上仍保留有一部份該厚光 阻層，蝕刻該墊層，以及研磨該晶圓之背面。在研磨該晶 圓之背面時，由於保留在該對準記號區域上的厚光阻層= 1259528 其與該7L件區域之間的應力差大大地減小，因而防止該晶 圓龜裂。 【實施方式] [第一實施例] 圖2八至圖2G為本發明之一實施例，圖2A顯示一晶圓 20包含元件區域2〇1及對準記號區域202，其具有一正面 203及月面204，在該正面203上之對準記號區域202内含 有夕個對準記號2022。圖2B顯示在該元件區域2〇1上沉積 至屬層22 ’金屬蓋緣28則形成在該元件區域201之邊 緣，之後’沉積一墊層24在該元件區域201及對準記號區 域202上，如闰— 朴、 戈圖2C所示，其中該墊層24係為一墊氧化層。 接著±佈一厚光阻層26在該元件區域2〇ι及對準記號區域 2〇2上啟佳者’該厚光阻層26係為PI光阻，厚度為Η微米， 並且使用一光罩23對準該對準記號2022以及使用紫外線 ^曝光’如圖2D所示，在微影製程後，該厚光阻層26形成 多個溝渠27在該元件區域201上，以及多個溝渠29在對準 記7虎區域202上’如圖2E所示。圖2F係顯示沿著該溝渠27 及29向下蝕刻該墊層24，並因此形成邊襯242。最後，圖 2G顯示一研磨裝置21研磨該晶圓2〇之背面2〇4，較佳者， 係使用化學機械研磨法，由於在該元件區域2〇1和對準記 號區域202上皆具有該厚光阻層26，使得在該二區域2〇1及 202的應力的差別大大地減小，當研磨裝置21研磨該晶圓 20之背面204時，即可防止該晶圓2〇產生龜裂。 1259528 [第二實施例] 圖3A至圖3H為本發明之另一實施例，圖3八顯示一晶 圓30包含元件區域301及對準記號區域3〇2，其具有一正面 303及-背面304 ’在該正面303上之對準記號區域3〇2内含 有多個對準記號搬2。圖3B顯示在該元件區域則上沉積 -金屬層32，金屬蓋緣38形成在該元件區域如之邊緣， 圖3C顯示沉積一墊層34在該元件區域3〇1及對準記號區域 302上，圖3D則顯示平坦化該墊層34之表面，較佳者，係 使用化學機械研磨法（CMP)。接著，塗佈一厚光阻層％在 該元件區域301及對準記號區域302上，較佳者，該厚光阻 層36係為PI光阻，厚度為14微米，並且使用一光罩33對準 該對準記號3022，以及使用紫外線35曝光，如圖3E所示。 之後，顯影該厚光阻層36以形成多個溝渠37在該元件區域 301上，以及一厚光阻塊體40在對準記號區域3〇2上，如圖 3F所示。圖3G係顯示沿著該溝渠37向下姓刻該墊層34。最 後，圖3H顯示一研磨裝置31研磨該晶圓30之背面3〇4，較 佳者，係使用化學機械研磨法，在此期間，由於在該對準 記號區域302上仍保留厚光阻塊體40，使得在該元件區域 301及對準記號區域302的應力的差別大大地減小，因而可 防止該晶圓3 0產生龜裂。 以上對於本發明之較佳實施例所作的敘述係為闡明 之目的，而無意限定本發明精確地為所揭露的形式，基於 以上的教導或從本發明的實施例學習而作修改或變化是 可能的，實施例係為解說本發明的原理以及讓熟習該項技 1259528 術者以各種實施例利用本發明在實際應用上而選擇及敘 述，本發明的技術思想企圖由以下的申請專利範圍及其均 等來決定。 【圖式簡單說明】 對於熟習本技藝之人士而言，從以下所作的詳細敘述 配合伴隨的圖式，本發明將能夠更清楚地被瞭解，其上述 及其他目的及優點將會變得更明顯，其中： 圖1A至F係習知之半導體製程； 圖2A至G係本發明之實施例；以及 圖3A至Η係本發明之另一實施例。 【主要元件符號說明】 10 晶圓 101 元件區域 102 對準記號區域 1022 對準記號 103 正面 104 背面 11 研磨裝置 12 金屬層 14 塾層 15 邊襯 光阻層 16 1259528 17 溝渠 18 金屬蓋緣 19 龜裂 20 晶圓 201 元件區域 202 對準記號區域 2022 對準記號 203 正面 204 背面 21 研磨裝置 22 金屬層 23 光罩 24 墊層 242 邊襯 25 紫外線 26 厚光阻層 27 溝渠 28 金屬蓋緣 29 溝渠 30 晶圓 301 元件區域 302 對準記號區域 303 正面 304 背面 1259528 3022 對準記號 31 研磨裝置 32 金屬層 33 光罩 34 塾層 35 紫外線 36 厚光阻層 37 溝渠 38 金屬蓋緣 40 厚光阻塊體1259528 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates to a semiconductor process, and more particularly to a method of preventing cracking of a wafer in a semiconductor process. [Prior Art] In the semiconductor process, in order to match the pattern or material of each step, one or more alignment mark areas are formed on the inactive area of each wafer, and each of the alignment mark areas contains one Or multiple alignment marks. In general, the alignment area is close to the edge of the wafer. Thereafter, all of the lithography process masks are aligned according to the alignment marks, for example, using a reticle (4) icle) to develop a plurality of grain regions after photo-light development, and then forming a composite body by physical or chemical treatment. The circuit is on the die area. However, it is always avoided in the process - some unnecessary particles are attached to the surface of the wafer, such as dust, or in order to obtain a flat surface, the wafer surface needs to be ground. In general, the front side of the wafer is the component build area, and the back side is ground in the semiconductor back end process. However, when the back of the wafer is polished using a grinding device, 'because of the alignment mark area and the component area Different stresses often cause wafer cracking. 1A to FIG. 1A show a conventional semiconductor back-end process. FIG. 1A shows a wafer 1 〇 including an element region 〇1 and an alignment mark region 102 having a front side 1 〇 3 and a back side 〇 4, an integrated circuit. Formed in the element region 01 of the front surface 103, the alignment mark region 102 on the front surface 1〇3 includes a plurality of alignment marks 1〇22. First, a metal cap 12 is deposited over the component region 101. A metal cap edge 18 is formed at the edge of the region 101 of the device 1259528, as shown in FIG. 1B, after which a pad layer 14 is deposited in the device region 101 and aligned. On the mark area 1 〇 2, as shown in FIG. ,c, the pad layer 14 is a pad oxide layer. Then, a photoresist layer 16 is coated on the device region ιοί. After the lithography process, the photoresist layer 16 forms a plurality of trenches 17 on the device region 101, as shown in FIG. 1D. Figure 1] shows that the underlayer 14 is etched down the trench 17, and thus the lining 15 is formed. Finally, FIG. 1F shows that a polishing apparatus 11 polishes the back surface 1 of the wafer 10. Since the stress in the element region 101 and the alignment mark area 102 is different, when the polishing apparatus grinds the back surface 104 of the wafer 10, A crack 19 is formed in the vicinity of the metal cover edge 18. This phenomenon is more serious when the wafer 10 is thinner or the difference in the topography of the element region 1〇1 and the alignment mark region 102 is larger. Therefore, a method of preventing cracking of a wafer in a semiconductor process is a problem. SUMMARY OF THE INVENTION An object of the present invention is to provide a method of preventing cracking of a wafer in a semiconductor process. The wafer has a front surface and a back surface, and an element region and an alignment mark region are formed on the front surface, and a metal layer is deposited on the device region, and a metal cover edge is formed at an edge of the device region, and the method includes depositing a The pad layer is coated on the component region and the alignment mark region, and a thick photoresist layer is coated on the component region and the alignment mark region, and the thick photoresist layer is applied to the thick photoresist layer, and the alignment mark is A portion of the thick photoresist layer remains in the region, the pad layer is etched, and the back side of the wafer is ground. When the back surface of the crystal is polished, the difference in stress between the thick photoresist layer remaining on the alignment mark region = 1259528 and the 7L member region is greatly reduced, thereby preventing the crystal from being cracked. [First Embodiment] FIG. 2 is a second embodiment of the present invention The lunar surface 204 has an alignment mark 2022 in the alignment mark area 202 on the front surface 203. 2B shows deposition on the element region 2〇1 to the genus layer 22'. The metal cap edge 28 is formed at the edge of the element region 201, after which a pad layer 24 is deposited over the device region 201 and the alignment mark region 202. As shown in Fig. 2 and Fig. 2C, the underlayer 24 is a pad oxide layer. Then, a thick photoresist layer 26 is applied to the element region 2〇 and the alignment mark region 2〇2. The thick photoresist layer 26 is a PI photoresist, has a thickness of Ημm, and uses a light. The cover 23 is aligned with the alignment mark 2022 and is exposed to ultraviolet light as shown in FIG. 2D. After the lithography process, the thick photoresist layer 26 forms a plurality of trenches 27 on the element region 201, and a plurality of trenches 29 On the alignment of the tiger area 202 ' as shown in Figure 2E. 2F shows the underlayer 24 being etched down the trenches 27 and 29, and thus forming a liner 242. Finally, FIG. 2G shows a polishing apparatus 21 for polishing the back surface 2〇4 of the wafer 2, preferably by chemical mechanical polishing, since both the element region 2〇1 and the alignment mark region 202 have The thick photoresist layer 26 is such that the difference in stress between the two regions 2〇1 and 202 is greatly reduced. When the polishing device 21 polishes the back surface 204 of the wafer 20, the wafer 2 is prevented from being cracked. . 1259528 [Second Embodiment] FIGS. 3A to 3H show another embodiment of the present invention, and FIG. 3 shows a wafer 30 including an element region 301 and an alignment mark region 3〇2 having a front surface 303 and a back surface. 304' includes a plurality of alignment marks 2 in the alignment mark area 3〇2 on the front surface 303. 3B shows a metal layer 32 deposited on the element region, with a metal cap edge 38 formed at the edge of the component region, and FIG. 3C shows deposition of a pad layer 34 over the component region 3〇1 and the alignment mark region 302. Figure 3D shows the surface of the underlayer 34 being planarized, preferably by chemical mechanical polishing (CMP). Next, a thick photoresist layer is coated on the element region 301 and the alignment mark region 302. Preferably, the thick photoresist layer 36 is a PI photoresist having a thickness of 14 micrometers and a photomask 33 is used. The alignment mark 3022 is aligned and exposed using ultraviolet light 35 as shown in FIG. 3E. Thereafter, the thick photoresist layer 36 is developed to form a plurality of trenches 37 on the element region 301, and a thick photoresist block 40 is on the alignment mark region 3'2, as shown in Fig. 3F. Figure 3G shows the underlayer 34 being engraved along the trench 37. Finally, FIG. 3H shows a polishing apparatus 31 grinding the back surface 3 of the wafer 30, preferably by chemical mechanical polishing, during which a thick photoresist block remains on the alignment mark area 302. The body 40 is such that the difference in stress between the element region 301 and the alignment mark region 302 is greatly reduced, so that cracking of the wafer 30 can be prevented. The above description of the preferred embodiments of the present invention is intended to be illustrative, and is not intended to limit the scope of the invention to the disclosed embodiments. It is possible to make modifications or variations based on the above teachings or learning from the embodiments of the present invention. The embodiments are described and illustrated in the practical application of the present invention in various embodiments using the present invention. The technical idea of the present invention is intended to be based on the following claims. Equal to decide. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects and advantages will become more apparent from the following detailed description. 1A to F are conventional semiconductor processes; FIGS. 2A through G are embodiments of the present invention; and FIGS. 3A through 3 are another embodiment of the present invention. [Main component symbol description] 10 Wafer 101 Component region 102 Alignment mark region 1022 Alignment mark 103 Front surface 104 Back surface 11 Grinding device 12 Metal layer 14 塾 layer 15 Side lining photoresist layer 16 1259528 17 Ditch 18 Metal cover edge 19 Turtle Split 20 Wafer 201 Component Area 202 Alignment Mark Area 2022 Alignment Mark 203 Front 204 Back 21 Grinding Device 22 Metal Layer 23 Photomask 24 Mat 242 Side Lining 25 Ultraviolet 26 Thick Photoresist Layer 27 Ditch 28 Metal Cover Edge 29 Ditch 30 Wafer 301 Component Area 302 Alignment Marker Area 303 Front Side 304 Back Surface 1259528 3022 Alignment Mark 31 Grinding Device 32 Metal Layer 33 Photomask 34 Tantalum Layer 35 Ultraviolet Light 36 Thick Photoresist Layer 37 Ditch 38 Metal Cover Edge 40 Thick Photoresist Block body