TWI690037B - 電子元件封裝 - Google Patents
電子元件封裝 Download PDFInfo
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- TWI690037B TWI690037B TW107130577A TW107130577A TWI690037B TW I690037 B TWI690037 B TW I690037B TW 107130577 A TW107130577 A TW 107130577A TW 107130577 A TW107130577 A TW 107130577A TW I690037 B TWI690037 B TW I690037B
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- H01L2924/3025—Electromagnetic shielding
Abstract
一種電子元件封裝包括:框架,包括貫穿孔及貫穿配線;電子元件,安置於所述框架的所述貫穿孔中;金屬板,安置於所述電子元件的及所述框架的第一側上;以及重佈線層,安置於所述電子元件的與所述第一側相對的第二側上且電性連接至所述電子元件。
Description
本發明是有關於一種電子元件封裝。
電子元件封裝被定義為用於將電子元件電性連接至例如電子裝置的主板等印刷電路板(printed circuit board,PCB),並保護電子元件不受外部影響的封裝技術。與電子元件相關的技術發展中的一個近期主要趨勢是減小電子元件的尺寸。因而,在封裝領域中,隨著對小型化電子元件等的需求的快速增加,對實作具有緊湊的尺寸且包括多個引腳的電子元件封裝的需求已在增加。
為滿足上述技術需求,所建議的一種封裝技術為利用在晶圓上形成的電子元件的電極墊的重佈線的晶圓級封裝(wafer level package,WLP)。所述晶圓級封裝的實例包括扇入(fan-in)型晶圓級封裝及扇出(fan-out)型晶圓級封裝。具體而言,扇出型晶圓級封裝具有緊湊的尺寸且有利於實作多個引腳。因而,近來,扇出型晶圓級封裝已得到積極開發。
本發明的態樣可提供一種其中在電子元件中產生的熱量可得以有效地輻射的電子元件封裝。
本發明所提出的若干解決方案中的一者可為使用金屬板。根據本發明的態樣,一種電子元件封裝可包括:框架,包括貫穿孔及貫穿配線;電子元件,安置於所述框架的所述貫穿孔中;金屬板,安置於所述電子元件的及所述框架的第一側上;以及重佈線層,安置於所述電子元件的與所述第一側相對的第二側上且電性連接至所述電子元件。
根據本發明的另一種態樣,一種電子元件封裝可包括:框架,包括貫穿孔;電子元件,安置於所述框架的所述貫穿孔中;包封體,覆蓋所述框架及所述電子元件中的每一者的至少部分且填充於所述框架的所述貫穿孔的至少部分;金屬板,安置於所述電子元件及所述框架上;黏合層,安置於所述金屬板與所述電子元件之間且安置於所述金屬板與所述框架之間;以及重佈線層,安置於所述電子元件及所述框架下且電性連接至所述電子元件。
所述電子元件封裝可更包括夾置於所述金屬板與所述電子元件之間的第一黏合層。
所述第一黏合層可由導電性環氧樹脂形成。
所述金屬板與所述電子元件可彼此直接接觸。
所述電子元件封裝可更包括夾置於所述金屬板與所述框架之間的第二黏合層。
所述第二黏合層可由焊料形成。
所述電子元件封裝可更包括夾置於所述金屬板與所述電子元件之間的第一黏合層及夾置於所述金屬板與所述框架之間的第二黏合層。所述第一黏合層與所述第二黏合層可由不同的材料形成。
所述框架可包括形成於所述框架的上表面上的配線層,且所述金屬板與所述配線層可彼此直接接觸。
所述貫穿配線的數目可為多個,且所述金屬板可電性連接至所述多個貫穿配線中的某些貫穿配線,且自所述多個貫穿配線中的其他貫穿配線電性分離。
所述金屬板可自所述電子元件電性分離。
所述電子元件封裝可更包括形成於所述電子元件及所述金屬板上的絕緣層。
所述絕緣層可形成於所述金屬板上及所述金屬板之下,且所述金屬板可嵌置於所述絕緣層中。
所述絕緣層可包括連接至所述框架的所述貫穿配線的導電介層窗。
所述絕緣層的所述導電介層窗可穿透過所述金屬板,且可自所述金屬板電性分離。
所述電子元件封裝可更包括填充於所述貫穿孔中以包封所述電子元件的包封體。
在下文中,將參照附圖來闡述本發明中的示例性實施例。在附圖中,為清晰起見,可誇大或縮小元件的形狀、尺寸、等。電子裝置
圖1是說明電子裝置系統的實例的示意性方塊圖。
參照圖1,電子裝置1000中可容置有母板1010。母板1010可包括實體連接至或電性連接至母板1010的晶片相關元件1020、網路相關元件1030、其他元件1040等。該些元件可連接至以下將闡述的其他元件以形成各種訊號線1090。
晶片相關元件1020可包括:記憶體晶片,例如揮發性記憶體(例如,動態隨機存取記憶體(dynamic random access memory,DRAM))、非揮發性記憶體(例如,唯讀記憶體(read only memory,ROM))、快閃記憶體等;應用處理器晶片,例如中央處理器(例如,中央處理單元(central processing unit,CPU))、圖形處理器(例如,圖形處理單元(graphic processing unit,GPU))、數位訊號處理器、密碼學處理器(cryptographic processor)、微處理器、微控制器等;邏輯晶片,例如類比至數位轉換器(analog-to-digital converter)、應用專用積體電路(application-specific integrated circuit,ASIC)等;以及類似晶片。然而,晶片相關元件1020並非僅限於此,而是亦可包括其他類型的晶片相關元件。另外,晶片相關元件1020可彼此組合。
網路相關元件1030可包括例如以下協定:無線保真(wireless fidelity,Wi-Fi)(電氣及電子工程師學會(Institute of Electrical and Electronics Engineers,IEEE)802.11家族等)、全球互通微波存取(worldwide interoperability for microwave access,WiMAX)(IEEE 802.16家族等)、IEEE 802.20、長期演進(long term evolution,LTE)、僅支援資料的演進(evolution data only,Ev-DO)、高速封包存取+(high speed packet access +,HSPA+)、高速下行封包存取+(high speed downlink packet access +,HSDPA+)、高速上行封包存取+(high speed uplink packet access +,HSUPA+)、增強型資料GSM環境(enhanced data GSM environment,EDGE)、全球行動通訊系統(global system for mobile communications,GSM)、全球定位系統(global positioning system,GPS)、通用封包無線電服務(general packet radio service,GPRS)、分碼多重存取(code division multiple access,CDMA)、分時多重存取(time division multiple access,TDMA)、數位增強型無線電訊(digital enhanced cordless telecommunications,DECT)、藍芽、3G協定、4G協定、5G協定及繼上述協定之後指定的任意其他無線協定及有線協定。然而,網路相關元件1030並非僅限於此,而是亦可包括多個其他無線標準或協定或者有線標準或協定中的任意者。另外,該些元件1030可與上述晶片相關元件1020一起相互組合。
其他元件1040可包括高頻電感器、鐵氧體電感器(ferrite inductor)、功率電感器、鐵氧體珠粒、低溫共燒陶瓷(low temperature co-fired ceramic,LTCC)、電磁干擾(electromagnetic interference,EMI)濾波器、多層陶瓷電容器(multilayer ceramic capacitor,MLCC)等。然而,其他元件1040並非僅限於此,而是亦可包括用於各種其他目的的被動元件等。另外,其他元件1040可與上述晶片相關元件1020或網路相關元件1030一起相互組合。
端視電子裝置1000的種類而定,電子裝置1000可包括可實體連接至或電性連接至母板1010或可不實體連接至或不電性連接至母板1010的其他元件。該些其他元件可包括例如照相機模組1050、天線1060、顯示器1070、電池1080、音訊編解碼器(圖中未示出)、視訊編解碼器(圖中未示出)、功率放大器(圖中未示出)、羅盤(圖中未示出)、加速度計(圖中未示出)、陀螺儀(圖中未示出)、揚聲器(圖中未示出)、大容量儲存裝置(例如,硬碟驅動機)(圖中未示出)、光碟(compact disk,CD)(圖中未示出)、數位多功能光碟(digital versatile disk,DVD)(圖中未示出)等。然而,該些其他元件並非僅限於此,而是端視電子裝置1000的種類而定亦可包括用於各種目的的其他元件。
電子裝置1000可為智慧型電話、個人數位助理(personal digital assistant,PDA)、數位攝影機、數位照相機(digital still camera)、網路系統、電腦、監視器、平板個人電腦(personal computer,PC)、膝上型個人電腦、隨身型易網機(netbook)個人電腦、電視、視訊遊戲機(video game machine)、智慧型手錶等。然而,電子裝置1000並非僅限於此,而是可為用於處理資料的任意其他電子裝置。
圖2是說明在電子裝置中使用的電子元件封裝的實例的示意圖。
所述電子元件封裝可出於各種目的而用於上述各種電子裝置1000中。舉例而言,主板1110可容置於智慧型電話1100的主體1101中,且各種電子元件1120可實體連接至或電性連接至主板1110。另外,可實體連接至或電性連接至主板1110或可不實體連接至或不電性連接至主板1110的其他元件(例如,照相機模組1130)可容置於主體1101中。在此種情形中,電子元件1120中的某些電子元件1120可為上述晶片相關元件,且電子元件封裝100可為例如晶片相關元件中的應用處理器,但並非僅限於此。電子元件封裝
圖3是說明電子元件封裝的實例的示意性剖視圖。圖4及圖5是說明圖3所示電子元件封裝的經修改型式的示意性剖視圖。
參照圖3,根據實例的電子元件封裝100可包括框架110、電子元件120、金屬板140及重佈線層150作為電子元件封裝100的主要元件。
一般的電子元件封裝具有其中電子元件由例如環氧模製化合物(epoxy molding compound,EMC)等包封體模製並環繞的結構。在此種情形中,在電子元件中產生的熱量大部分沿重佈線層向下排出,而僅極少量的熱量被傳導至具有低導熱率的包封體,進而使得熱輻射特性劣化。在本示例性實施例中,在框架110上及電子元件120上可安置有金屬板140以使自電子元件120等產生的熱量容易地擴散,且因此可改良熱輻射特性。
另外,在採用其中電子元件僅由例如環氧模製化合物等包封體模製並環繞的結構的情形中,其中安裝有電子元件的電子裝置的運作特性等可因由自電子元件產生的或自外部源引入的電磁波造成的電磁干擾(electromagnetic interference,EMI)而劣化。相反,在本示例性實施例中,在電子元件120上可安置有金屬板140以阻擋電磁波,且因此,亦可防止因電磁干擾而產生的問題。
在下文中,將更詳細地闡述根據實例的電子元件封裝100的上述主要元件及另外的元件。
被設置成支撐電子元件封裝100的框架110可維持電子元件封裝100的剛性並確保電子元件封裝100的厚度均勻性,且可包括貫穿孔(圖3中其中安置有電子元件120的區)及多個貫穿配線115。框架110可具有上表面110A及與上表面110A相對的下表面110B。在此種情形中,貫穿孔可穿透於上表面110A與下表面110B之間。電子元件120可安置於所述貫穿孔中,以與框架110間隔開預定距離。結果,電子元件120的側表面可被框架110環繞。
框架110的材料並無特別限制,只要所述框架可支撐電子元件封裝即可。舉例而言,可使用絕緣材料作為框架110的材料。在此種情形中,絕緣材料可為:熱固性樹脂,例如環氧樹脂;熱塑性樹脂,例如聚醯亞胺樹脂(polyimide resin);將加強材料(例如,玻璃纖維或無機填料)浸漬於熱固性樹脂及熱塑性樹脂中的樹脂,例如,預浸體(pre-preg)、味之素構成膜(Ajinomoto Build up Film,ABF)、FR-4、雙馬來醯亞胺三嗪(Bismaleimide Triazine,BT)、覆銅疊層板(copper clad laminate,CCL)等。作為另外一種選擇,可使用具有優異剛性及導熱率的金屬作為框架110的材料。在此種情形中,所述金屬可為Fe-Ni系合金。在此種情形中,為確保Fe-Ni系合金與模製材料、層間絕緣材料等之間的黏合,亦可在Fe-Ni系合金的表面上形成鍍銅層(copper plating)。除了上述材料之外,亦可使用玻璃、陶瓷、塑膠等作為所述框架的材料。
框架110的橫截面厚度並無特別限制,而是可端視電子元件120的橫截面厚度而進行設計。舉例而言,端視電子元件120的種類而定,框架110的橫截面厚度可為約100微米至500微米。框架110可包括一個層或可包括多個層。在其中框架110包括多個層的情形中,在所述多個層之間可安置有配線層。在此種情形中,相應層的厚度並無特別限制,且如上所述可對各相應層的整體厚度進行調整。
如在圖3所說明的形式中,框架110可包括形成於框架110的上表面110A上的第一配線層113、形成於框架110的內壁110X上的第二配線層116、形成於框架110的下表面110B上的第三配線層114,以及穿透過框架110的貫穿配線115。在此種情形中,貫穿配線115的數目可為多個。
第一配線層113可用作重佈線圖案,且可使用例如銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、鈦(Ti)或其合金等導電材料作為第一配線層113的材料。第一配線層113可端視對應層的設計而執行各種功能。舉例而言,第一配線層113可用作接地圖案、電源圖案、訊號圖案等。此處,訊號圖案可包括除接地圖案、電源圖案等之外的各種訊號,例如資料訊號等。另外,第一配線層113可用作介層窗墊、連接端子墊等。第一配線層113的厚度並無特別限制,而是可為例如約10微米至50微米。
第二配線層116可基本上使自電子元件120產生的熱量分散以使熱量朝框架110擴散,並阻擋電磁波。第二配線層116亦可端視其設計而執行各種功能,且可用作接地圖案。第二配線層116可安置於框架110的內壁110X上。因此,第二配線層116可環繞電子元件120的側表面。第二配線層116可被形成為完全覆蓋框架110的內壁110X。可使用銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、鈦(Ti)或其合金作為第二配線層116的材料。
第二配線層116可用作重佈線圖案且可使用例如銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、鈦(Ti)或其合金等導電材料作為第二配線層116的材料。第二配線層116亦可端視對應層的設計而執行各種功能。舉例而言,第二配線層116可用作接地圖案、電源圖案、訊號圖案等。與第一配線層113相似,訊號圖案可包括除接地圖案、電源圖案等之外的各種訊號,例如資料訊號等。另外,第二配線層116可用作介層窗墊、連接端子墊等。第二配線層116的厚度亦無特別限制,而是可為例如約10微米至50微米。
貫穿配線115可穿透過框架110並用於將安置於與框架110相關的不同層上的重佈線層電性連接至彼此。可使用例如銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、鈦(Ti)或其合金等導電材料作為貫穿配線115的材料。電子元件120的上側與下側可藉由貫穿配線115經由電子元件120的左側表面及右側表面而電性連接至彼此。因此,可顯著地提高空間利用率。另外,電子元件封裝可經由三維結構中的連接而被應用於堆疊封裝(package-on-package,PoP)、系統級封裝(system-in-package,SiP)等,進而使得電子元件封裝可被應用於各種模組、應用封裝的產品組(package applied product groups)等。
貫穿配線115的數目、間隔、安置形式等並無特別限制,而是可由熟習此項技術者端視設計細節而作出充分修改。貫穿配線115可連接至第一配線層113及第三配線層114的墊圖案。舉例而言,貫穿配線115可端視安裝於電子元件封裝100上的另一封裝的形式而安置於框架110的整個區中。作為另外一種選擇,貫穿配線115可安置於框架110的僅特定區中。
在其中使用例如Fe-Ni系合金等金屬作為框架110的材料的情形中,絕緣材料可安置於金屬與貫穿配線115之間以使金屬與貫穿配線115與彼此電性絕緣。貫穿配線115的橫截面的形狀並無特別限制,而是可為例如錐形形狀、沙漏形狀、柱形狀等習知形狀。貫穿配線115可被導電材料完全填充,如圖3所說明,但並非僅限於此。亦即,導電材料可沿介層窗的壁形成。
在本示例性實施例中,除了上述電性配線的功能之外,貫穿配線115亦可被用作熱輻射路徑。亦即,貫穿配線115可藉由包括金屬元件的配線層152而連接至電子元件120,以藉此成為有效熱輻射路徑,且可熱連接至安置於貫穿配線115上的金屬板140以用於進一步改良電子元件封裝100的熱輻射特性。
電子元件120可為被設置成將數量為數百至數百萬個組件或更多個組件整合於單個晶片、主動元件等中的積體電路(integrated circuit,IC)。若需要,則電子元件120可為其中將積體電路封裝成倒裝晶片形式的電子元件。所述積體電路可為例如:應用處理器晶片,例如中央處理器(例如,中央處理單元)、圖形處理器(例如,圖形處理單元)、數位訊號處理器、密碼學處理器、微處理器、微控制器等,但並非僅限於此。
電子元件120可包括出於電性連接目的而形成的電極墊120P。電極墊120P可被配置成在外部對電子元件120進行電性連接,且電極墊120P的材料並無特別限制,只要電極墊120P的材料是導電材料即可。所述導電材料可為銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、鈦(Ti)或其合金,但並非僅限於此。電極墊120P可具有嵌入形式或突出形式。其上形成有電極墊120P的表面可被稱為主動表面,且與所述主動表面相對的表面可被稱為被動表面。
在其中電子元件120為積體電路的情形中,電子元件120可具有主體(未由參考編號指示)、保護層(未由參考編號指示)及電極墊120P。所述主體可在例如主動晶圓基礎上形成。在此種情形中,可使用矽(Si)、鍺(Ge)、砷化鎵(GaAs)等作為所述主體的基材(basic material)。保護層可用以保護主體免受外部因素的損害且可由例如氧化物層、氮化物層等形成或者可由包括氧化物層與氮化物層的雙層形成。如上所述,電極墊120P可包含例如銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、鈦(Ti)或其合金等導電材料。
電子元件120的橫截面厚度並無特別限制,而是可端視電子元件120的種類而改變。舉例而言,在其中電子元件為積體電路的情形中,電子元件的厚度可為約100微米至480微米,但並非僅限於此。
在本示例性實施例中,如在圖3所說明的形式中一般,可使用包封體130來保護電子元件120等,儘管包封體130並非必需的元件。包封體130的形式並無特別限制,而是可為環繞電子元件120的至少某些部分的形式。然而,不同於圖3所說明的形式,包封體130可覆蓋例如框架110及電子元件120,且可填充貫穿孔內的框架110與電子元件120之間的空間。因此,端視某些材料而定,包封體130可用作黏合劑且可減少電子元件120的彎曲(buckling)。
包封體130的某些材料並無特別限制。舉例而言,可使用絕緣材料作為包封體130的材料。在此種情形中,所述絕緣材料可為:熱固性樹脂,例如環氧樹脂;熱塑性樹脂,例如聚醯亞胺樹脂;將加強材料(例如,有機填料或無機填料)浸漬於熱固性樹脂及熱塑性樹脂中的樹脂等。作為另外一種選擇,所述絕緣材料可為環氧膜製化合物(EMC)等。
如上所述,在本示例性實施例中,藉由金屬板140而設置有有效熱輻射路徑,且因此,電子元件120的上表面未被包封體130覆蓋,而是可被暴露出。因此,熱量可經由電子元件120的上部部分朝金屬板140順暢地輻射。
在相對於電子元件120而與金屬板140相對的一側處(即,圖3中電子元件120之下)可安置有重佈線層150,且重佈線層150可電性連接至電子元件120並被配置成對電子元件120的電極墊120P進行重佈線。具有各種功能的數十至數百個電極墊120P可端視其功能而藉由重佈線層150進行重佈線,且可在外部藉由連接端子190而進行實體連接或電性連接。重佈線層150可包括絕緣層151、形成於絕緣層151上的配線層152以及穿透過絕緣層151的導電介層窗153。重佈線層150可為單層或多個層。
可使用絕緣材料作為絕緣層151的材料。具體而言,在其中使用感光性樹脂作為絕緣層的材料的情形中,可以減小的厚度形成絕緣層151,且可易於實作精細的節距。若需要,則各絕緣層151的材料可彼此相同或可彼此不同。絕緣層151的厚度亦無特別限制。舉例而言,絕緣層151的除配線層152之外的厚度可為約5微米至20微米,且當將配線層152的厚度考慮在內時,絕緣層151的厚度可為約15微米至70微米。
配線層152可用作重佈線圖案,且可使用例如銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、鈦(Ti)或其合金等導電材料作為配線層152的材料。
若需要,則可在配線層152中的在外部暴露出的配線層上更形成表面處理層。表面處理層並無特別限制,只要所述表面處理層為相關技術中習知的即可,且表面處理層可由例如以下方法形成:電解鍍金、無電鍍金、有機可焊性保護(organic solderability preservative,OSP)或無電鍍錫、無電鍍銀、無電鍍鎳/置換鍍金、直接浸金(direct immersion gold,DIG)鍍覆、熱空氣焊料均塗(hot air solder leveling,HASL)等。此亦可被應用至其他配線層等。
導電介層窗153可將在不同層上形成的配線層152、電極墊120P等電性連接至彼此,從而在電子元件封裝100中形成電性路徑。可使用例如銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、鈦(Ti)或其合金等導電材料作為導電介層窗153的材料。導電介層窗153亦可被導電材料完全填充。作為另外一種選擇,導電材料可沿導電介層窗153的壁形成。另外,導電介層窗153可以例如錐形形狀、圓柱形形狀等相關技術中習知的橫截面形狀中的所有形狀形成。
金屬板140可如上所述用作在電子元件120等中產生的熱量的熱輻射路徑,且可阻擋電磁波。就此而言,可使用例如銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、鈦(Ti)或其合金等具有高的熱輻射性質的材料作為金屬板140的材料。
在金屬板140與電子元件120之間可夾置有第一黏合層161以將金屬板140固定至電子元件封裝100。第一黏合層161可由例如導電性環氧樹脂等具有高的熱輻射性質的絕緣材料形成。根據另一實施例,可以其中如在圖4所示經修改實例中一般使電子元件120直接接觸金屬板140而不使用第一黏合層161的形式來實作電子元件封裝。在此種情形中,熱輻射特性可進一步得以改良。在其中如在圖4所示的實例中一般,電子元件120與金屬板140之間不存在第一黏合層的情形中,金屬板140可藉由第二黏合層162而耦合至框架110。
再次參照圖3,在金屬板140與框架110之間可夾置有第二黏合層162以將金屬板140與框架110耦合至彼此。在此種情形中,第二黏合層162可由與第一黏合層161的材料不同的材料形成。舉例而言,第二黏合層162可由具有優異的導熱率的焊料形成。藉由上述形式,金屬板140可連接至框架110的貫穿配線115以用作使熱量輻射至電子元件120的下部部分的熱輻射路徑。與第一黏合層161相似,亦可在不使用第二黏合層162的條件下使用金屬板140,如在圖5所說明的形式中一般。在此種情形中,金屬板140可在藉由第一黏合層161耦合至電子元件120的同時直接接觸框架110的第一配線層113。
除上述熱輻射功能之外,金屬板140亦可用作在電子元件封裝中形成的訊號圖案等的接地端子。在此種情形中,金屬板140可電性連接至第一配線層113及第二配線層116的用作接地端子的某些部分。在其中金屬板140用作接地端子的情形中,金屬板140可電性連接至所述多個貫穿配線115中的僅某些貫穿配線115,且可自所述多個貫穿配線115中的其它貫穿配線115電性分離。就此而言,第二黏合層162的在金屬板140與框架110之間使用的一部分可由例如焊料等導電材料形成,且第二黏合層162的其他區可由例如絕緣樹脂等絕緣材料形成。同時,亦可僅設置金屬板140來提高熱輻射效率。在此種情形中,金屬板140可自電子元件120電性分離。為此,第二黏合層162可由絕緣材料形成,或者貫穿配線115等可不被配置成電性連接至電子元件120。
將參照圖3闡述其他另外的元件。保護層180可被配置成保護重佈線層150不受外部物理損壞或化學損壞等。保護層180可具有暴露出重佈線層150的配線層152的至少某些部分的開口181。儘管開口181暴露出配線層152的一個表面的某些部分,然而在某種情形中,開口181亦可暴露出配線層152的側表面。
保護層180的材料並無特別限制。舉例而言,可使用阻焊劑作為保護層180的材料。另外,亦可使用例如感光性樹脂等與重佈線層150的絕緣層151的材料相同的材料作為保護層180的材料。保護層180一般為單層,但亦可為多個層。
連接端子190可被配置成在外部對電子元件封裝100進行實體連接及電性連接。舉例而言,電子元件封裝100可經由連接端子190而安裝於電子裝置的主板上。連接端子190可安置於開口181上,且可連接至經由開口181而暴露出的配線層152。因此,連接端子190亦可電性連接至電子元件120。
連接端子190可由例如銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、焊料等導電材料形成。然而,該些材料僅為實例,且連接端子190的材料並非特別地限定於此。連接端子190可為焊盤(land)、球、引腳等。連接端子190可由多個層或單層形成。在其中連接端子190由多個層形成的情形中,連接端子190可包含銅柱及焊料,且在其中連接端子190由單層形成的情形中,連接端子190可包含錫-銀焊料或銅,但並非僅限於此。
連接端子190中的至少一者可安置於扇出區中。扇出區是排除其中安置有電子元件的區之外的區。亦即,根據實例的電子元件封裝100可為扇出型封裝。扇出型封裝可相較於扇入型封裝而具有優異的可靠性,扇出型封裝可實作多個輸入/輸出(input/output,I/O)端子且可便於進行3D互連。另外,相較於球柵陣列(ball grid array,BGA)封裝、焊盤柵陣列(land grid array,LGA)封裝等,扇出型封裝可安裝於電子裝置上而無需使用單獨的板。因此,扇出型封裝可被製造成薄的,且可具有價格競爭力。
連接端子190的數目、間隔、安置形式等並無特別限制,而是可由熟習此項技術者端視設計細節而作出充分修改。舉例而言,端視電子元件120的電極墊120P的數目而定,連接端子190的數目可為數十至數千。然而,連接端子190的數目並非僅限於此,而是亦可為數十至數千或以上或者數十至數千或以下。
圖6是說明電子元件封裝的另一實例的示意性剖視圖。
參照圖6,與上述示例性實施例相似,根據另一實例的電子元件封裝200可包括框架110、電子元件120、包封體130、金屬板240、重佈線層150等。在下文中,將闡述根據本經修改實例的電子元件封裝200的元件,且將不再對與上述內容重複的內容予以贅述,而是將主要闡述與上述內容不同的內容。
在本經修改實例中,在電子元件120上及金屬板240上可形成有絕緣層230。如在圖6所說明的形式中一般,在金屬板240上及金屬板240之下可形成有絕緣層230。因此,金屬板240可具有其中金屬板240嵌置於絕緣層230中的形式。在此種情形中,絕緣層230可由具有電性絕緣性質的習知材料(例如與包封體130的材料相同的材料)形成。作為更詳細的實例,絕緣層230可藉由將預浸體(PPG)層等堆疊若干次來實作。
在圖6所示示例性實施例中,在電子元件120上可另外地安置有另一封裝。因此,可實作堆疊封裝結構。為此,絕緣層230可包括導電介層窗210。導電介層窗210可連接至框架110的貫穿配線115,進而使得可獲得上部導電結構及下部導電結構。在此種情形中,如圖6中說明的形式一般,絕緣層230的導電介層窗210可穿透過金屬板240,且可自金屬板240電性分離。
如上所述,根據本發明中的示例性實施例,可提供一種能夠有效地輻射自電子元件產生的熱量的封裝技術。
在本發明中,已使用用語「下側」、「下部部分」、「下表面」等來表示相對於所述圖式的橫截面而言朝向電子元件封裝的安裝表面的方向,已使用用語「上側」、「上部部分」、「上表面」等來表示與由用語「下側」、「下部部分」、「下表面」等表示的方向相反的方向。然而,該些方向僅是出於解釋方便而定義的,且申請專利範圍並非特別受限於上述所定義的方向。
在本說明中元件與另一元件的「連接(connection)」的意義包括經由黏合層的間接連接以及兩個元件之間的直接連接。另外,「電性連接(electrically connected)」的意思包括實體連接及實體分離。應理解,當以「第一(first)」及「第二(second)」來指代組件時,所述組件並非受限於此。該些用語可能僅用於將所述組件與其他組件區分開的目的,且可不限制所述組件的順序或重要性。在某些情形中,在不背離本文所述申請專利範圍的範圍的條件下,第一組件可被稱作第二組件。相似地,第二組件亦可被稱作第一組件。
本文中所使用的用語「示例性實施例」並不始終指代同一示例性實施例,而是為強調與另一示例性實施例的特定特徵或特性不同的特定特徵或特性而提供。然而,本文中所提供的示例性實施例被視為能夠藉由彼此整體地或部分地組合來實作。舉例而言,即使並未在另一示例性實施例中闡述在特定示例性實施例中闡述的一個組件,然而除非在本文中提供了相反或矛盾的說明,否則所述組件亦可被理解為與另一示例性實施例相關的說明。
使用本文中所使用的用語僅是為了闡述示例性實施例而非限制本發明。在此種情形中,除非基於特定的上下文而另外進行必要的解釋,否則單數形式亦包括複數形式。
儘管以上已示出並闡述了各示例性實施例,然而對於熟習此項技術者而言將顯而易見,在不背離由隨附申請專利範圍所界定的本發明的範圍的條件下,可作出潤飾及變型。
100、200‧‧‧電子元件封裝110‧‧‧框架110A‧‧‧上表面110B‧‧‧下表面110X‧‧‧內壁113‧‧‧第一配線層114‧‧‧第三配線層115‧‧‧貫穿配線116‧‧‧第二配線層120、1120‧‧‧電子元件120P‧‧‧電極墊130‧‧‧包封體140、240‧‧‧金屬板150‧‧‧重佈線層151‧‧‧絕緣層152‧‧‧配線層153、210‧‧‧導電介層窗161‧‧‧第一黏合層162‧‧‧第二黏合層180‧‧‧保護層181‧‧‧開口190‧‧‧連接端子230‧‧‧絕緣層1000‧‧‧電子裝置1010‧‧‧母板1020‧‧‧晶片相關元件1030‧‧‧網路相關元件/元件1040‧‧‧其他元件1050、1130‧‧‧照相機模組1060‧‧‧天線1070‧‧‧顯示器1080‧‧‧電池1090‧‧‧訊號線1100‧‧‧智慧型電話1101‧‧‧主體1110‧‧‧主板
結合附圖閱讀以下詳細說明,將更清楚地理解本發明的以上及其他態樣、特徵及優點,在附圖中: 圖1是說明電子裝置系統的實例的示意性方塊圖。 圖2是說明在電子裝置中使用的電子元件封裝的實例的示意圖。 圖3是說明電子元件封裝的實例的示意性剖視圖。 圖4及圖5是說明圖3所示電子元件封裝的經修改型式的示意性剖視圖。 圖6是說明電子元件封裝的另一實例的示意性剖視圖。
100‧‧‧電子元件封裝
110‧‧‧框架
110A‧‧‧上表面
110B‧‧‧下表面
110X‧‧‧內壁
113‧‧‧第一配線層
114‧‧‧第三配線層
115‧‧‧貫穿配線
116‧‧‧第二配線層
120‧‧‧電子元件
120P‧‧‧電極墊
130‧‧‧包封體
140‧‧‧金屬板
150‧‧‧重佈線層
151‧‧‧絕緣層
152‧‧‧配線層
153‧‧‧導電介層窗
161‧‧‧第一黏合層
162‧‧‧第二黏合層
180‧‧‧保護層
181‧‧‧開口
190‧‧‧連接端子
Claims (7)
- 一種電子元件封裝,包括:框架,包括穿透過所述框架的至少一部分的貫穿孔;電子元件,安置於所述框架的所述貫穿孔中,以與所述框架間隔開;包封體,覆蓋所述框架及所述電子元件中的每一者的至少部分且填充於所述框架的所述貫穿孔的至少部分;金屬板,安置於所述電子元件及所述框架上;黏合層,安置於所述金屬板與所述電子元件之間且安置於所述金屬板與所述框架之間;重佈線層,安置於所述電子元件及所述框架下且電性連接至所述電子元件;以及第一金屬層,直接安置於所述框架的上表面,其中所述電子元件的多個側表面被所述框架的所述貫穿孔的多個內壁環繞。
- 如申請專利範圍第1項所述的電子元件封裝,更包括第二金屬層安置於所述框架的所述貫穿孔的所述多個內壁,其中所述第二金屬層環繞所述電子元件的所述多個側表面。
- 如申請專利範圍第1項所述的電子元件封裝,更包括第三金屬層安置於所述框架的下表面。
- 如申請專利範圍第1項所述的電子元件封裝,其中所述黏合層包括第一黏合層,且所述第一黏合層包括導電性環氧樹脂。
- 如申請專利範圍第1項所述的電子元件封裝,其中黏合層包括第二黏合層,且所述第二黏合層包括焊料。
- 如申請專利範圍第1項所述的電子元件封裝,其中所述金屬板電性絕緣於所述電子元件。
- 如申請專利範圍第1項所述的電子元件封裝,更包括穿透過所述框架的貫穿配線。
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US10978408B2 (en) * | 2018-06-07 | 2021-04-13 | Powertech Technology Inc. | Semiconductor package and manufacturing method thereof |
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