TWI679302B - 半導體基板及其製造方法 - Google Patents

半導體基板及其製造方法 Download PDF

Info

Publication number
TWI679302B
TWI679302B TW107139501A TW107139501A TWI679302B TW I679302 B TWI679302 B TW I679302B TW 107139501 A TW107139501 A TW 107139501A TW 107139501 A TW107139501 A TW 107139501A TW I679302 B TWI679302 B TW I679302B
Authority
TW
Taiwan
Prior art keywords
electroless
plating
plating film
film
semiconductor substrate
Prior art date
Application number
TW107139501A
Other languages
English (en)
Other versions
TW201928113A (zh
Inventor
渡辺拓人
Takuto WATANABE
土田克之
Katsuyuki Tsuchida
Original Assignee
日商Ｊｘ金屬股份有限公司
Jx Nippon Mining & Metals Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商Ｊｘ金屬股份有限公司, Jx Nippon Mining & Metals Corporation filed Critical 日商Ｊｘ金屬股份有限公司
Publication of TW201928113A publication Critical patent/TW201928113A/zh
Application granted granted Critical
Publication of TWI679302B publication Critical patent/TWI679302B/zh

Links

Classifications

    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/1601—Process or apparatus
    • C23C18/1633—Process of electroless plating
    • C23C18/1646—Characteristics of the product obtained
    • C23C18/165—Multilayered product
    • C23C18/1651—Two or more layers only obtained by electroless plating
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/1601—Process or apparatus
    • C23C18/1633—Process of electroless plating
    • C23C18/1635—Composition of the substrate
    • C23C18/1639—Substrates other than metallic, e.g. inorganic or organic or non-conductive
    • C23C18/1642—Substrates other than metallic, e.g. inorganic or organic or non-conductive semiconductor
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/18—Pretreatment of the material to be coated
    • C23C18/1803—Pretreatment of the material to be coated of metallic material surfaces or of a non-specific material surfaces
    • C23C18/1824—Pretreatment of the material to be coated of metallic material surfaces or of a non-specific material surfaces by chemical pretreatment
    • C23C18/1837—Multistep pretreatment
    • C23C18/1841—Multistep pretreatment with use of metal first
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/18—Pretreatment of the material to be coated
    • C23C18/1803—Pretreatment of the material to be coated of metallic material surfaces or of a non-specific material surfaces
    • C23C18/1824—Pretreatment of the material to be coated of metallic material surfaces or of a non-specific material surfaces by chemical pretreatment
    • C23C18/1837—Multistep pretreatment
    • C23C18/1844—Multistep pretreatment with use of organic or inorganic compounds other than metals, first
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/31—Coating with metals
    • C23C18/32—Coating with nickel, cobalt or mixtures thereof with phosphorus or boron
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/31—Coating with metals
    • C23C18/32—Coating with nickel, cobalt or mixtures thereof with phosphorus or boron
    • C23C18/34—Coating with nickel, cobalt or mixtures thereof with phosphorus or boron using reducing agents
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/31—Coating with metals
    • C23C18/42—Coating with noble metals
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/31—Coating with metals
    • C23C18/42—Coating with noble metals
    • C23C18/44—Coating with noble metals using reducing agents
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/54—Contact plating, i.e. electroless electrochemical plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/0218—Structure of the auxiliary member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H01L2224/03464—Electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0501—Shape
    • H01L2224/05016—Shape in side view
    • H01L2224/05017—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05073—Single internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05164—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05575—Plural external layers
    • H01L2224/05576—Plural external layers being mutually engaged together, e.g. through inserts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05664—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/11334—Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Organic Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrochemistry (AREA)
  • Chemically Coating (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

本發明之實施形態之目的在於提供一種具有Au電極墊且生產性優異的半導體基板及其製造方法。本發明之實施形態的半導體基板係在Au電極墊上具有無電解Ni鍍敷皮膜/無電解Pd鍍敷皮膜/無電解Au鍍敷皮膜、或無電解Ni鍍敷皮膜/無電解Au鍍敷皮膜。本發明之實施形態的半導體基板之製造方法係藉由下述(1)至(6)所記載的步驟，在Au電極墊上形成無電解Ni鍍敷皮膜/無電解Pd鍍敷皮膜/無電解Au鍍敷皮膜、或無電解Ni鍍敷皮膜/無電解Au鍍敷皮膜，下述(1)至(6)為：(1)脫脂步驟、(2)蝕刻步驟、(3)預浸漬步驟、(4)賦予Pd觸媒步驟、(5)無電解Ni鍍敷步驟、以及(6)無電解Pd鍍敷步驟及無電解Au鍍敷步驟、或無電解Au鍍敷步驟。

Description

半導體基板及其製造方法
本發明係有關半導體基板、及其製造方法。
本申請案係主張依據2017年11月16日申請之日本申請案第2017-221166號、及2018年9月5日申請之日本申請案第2018-166131號之優先權，且援用前述日本申請案所記載之全部記載內容者。
近年來，半導體裝置之輕薄短小化正在進展中，就將IC(Integrated Circuit；積體電路)與基板及IC彼此接合之方法而言係從以往之打線接合發展至覆晶化。
為了以覆晶將IC與基板及IC彼此接合，在已形成於IC上之Al、Cu、Au等之電極墊以蒸鍍或鍍敷而形成UBM(Under Bump Metallurgy；凸塊下冶金)，並在其上以印刷、球粒搭載或鍍敷而形成Sn-Ag、Sn-Ag-Cu等無鉛焊料。使用將其在同樣地形成之IC及基板上進行加熱接合之方法。
就在Al、Cu、Au等之電極墊上形成UBM之方法而言，最近，從生產性提升及降低成本之觀點而言，無電解Ni鍍敷正受到矚目。
就在Al電極墊上形成無電解Ni鍍敷皮膜之方法而言，正廣泛使用使用了Zn之置換鍍敷的鋅酸鹽法，就在Cu電極墊上形成無電解Ni鍍敷皮膜之方法而言，正廣泛使用Pd觸媒法。
然而，以GaAs基板為首之化合物半導體基板中，有在電極墊使用Au之情形。Au係化學上安定的金屬，即使使用已知的鋅酸鹽法或Pd觸媒法，亦難以形成無電解Ni鍍敷皮膜。例如，在Cu電極墊上形成無電解Ni鍍敷皮膜時，在Cu上即使為室溫之Pd處理，亦會析出Pd，其結果，可藉由無電解Ni鍍敷形成Ni皮膜，然而在Au上以室溫之Pd處理，不易析出Pd，藉由無電解Ni鍍敷會產生不形成Ni皮膜之處。因此，在Au電極墊上鍍敷形成Ni作為UBM時，主要使用電鍍。
電鍍時，為了進行選擇性鍍敷，必須有光製程，且必須有使電流在應被鍍敷之Au電極墊各者流動用之配線，而且每一片逐一處理，故有成本龐大且生產性低之問題。
就在Au上形成無電解Ni鍍敷皮膜之嘗試而言，在專利文獻1中揭示有在接觸特定的表面活性化液之後，賦予無電解鍍敷(也稱為無電鍍敷或化學鍍)用觸媒，然後進行無電解Ni鍍敷之方法。
[先前技術文獻] [專利文獻]
[專利文獻1]日本特開2007-177268號公報
本發明之實施形態之目的在於提供具有Au電極墊且生產性優異之半導體基板及其製造方法。
本發明人等致力研究之結果，發現在Au電極墊上，藉由無電解Ni鍍敷，Ni會安定地析出，並可得到可使用來作為UBM之半導體基板，其中該半導體基板具有無電解Ni鍍敷皮膜/無電解Pd鍍敷皮膜/無電解Au鍍敷皮膜、或無電解Ni鍍敷皮膜/無電解Au鍍敷皮膜，終於完成本發明。
亦即，本發明之實施形態包括下述構成。
[1]一種半導體基板，係具有Au電極墊，並且在前述Au電極墊上具有無電解Ni鍍敷皮膜/無電解Pd鍍敷皮膜/無電解Au鍍敷皮膜、或無電解Ni鍍敷皮膜/無電解Au鍍敷皮膜。
[2]如前述[1]項所述之半導體基板，其中，在前述無電解Ni鍍敷皮膜/無電解Pd鍍敷皮膜/無電解Au鍍敷皮膜、及無電解Ni鍍敷皮膜/無電解Au鍍敷皮膜中，無電解Ni鍍敷皮膜之膜厚為1.5μm至10μm，無電解Au鍍敷皮膜之膜厚為0.01μm至0.50μm，在前述無電解Ni鍍敷皮膜/無電解Pd鍍敷皮膜/無電解Au鍍敷皮膜中，無電解Pd鍍敷皮膜之膜厚為0.02μm至0.50μm。
[3]如前述[1]或[2]項所述之半導體基板，其中，前述無電解Ni鍍敷皮膜含有2質量%至15質量%之P。
[4]如前述[1]至[3]項中任一項所述之半導體基板，其中，前述半導體基板係具有鈍化膜，前述鈍化膜係形成於前述Au電極墊上，且具有使前述Au電極墊露出之開口部，在前述開口部之Au電極墊上，具有無電解Ni鍍敷皮膜/無電解Pd鍍敷皮膜/無電解Au鍍敷皮膜、或無電解Ni鍍敷皮膜/無電解Au鍍敷皮膜，在形成有前述無電解Ni鍍敷皮膜之區域中，前述Au電極墊被蝕刻1nm以上。
[5]如前述[1]至[4]項中任一項所述之半導體基板，其中，前述半導體基板為化合物半導體基板、或氧化物半導體基板。
[6]如前述[5]項所述之半導體基板，其中，前述化合物半導體基板之化合物半導體為選自II-VI族半導體、III-V族半導體、III-V族(氮化物系)半導體、IV-VI族半導體、IV-IV族半導體、I-III-VI族半導體、及II-IV-V族半導體之任一者。
[7]一種半導體基板之製造方法，係製造前述[1]至[6]項中任一項所述之半導體基板的方法，且該製造方法係藉由下述(1)至(6)所記載的步驟，在Au電極墊上形成無電解Ni鍍敷皮膜/無電解Pd鍍敷皮膜/無電解Au鍍敷皮膜、或無電解Ni鍍敷皮膜/無電解Au鍍敷皮膜， (1)脫脂步驟；(2)蝕刻步驟；(3)預浸漬步驟；(4)賦予Pd觸媒步驟；(5)無電解Ni鍍敷步驟；以及(6)無電解Pd鍍敷步驟及無電解Au鍍敷步驟、或無電解Au鍍敷步驟。
[8]如前述[7]項所述之半導體基板之製造方法，其中，在前述賦予Pd觸媒步驟中，使用處理液，並將賦予Pd觸媒時之處理液的溫度設為20℃至90℃。
[9]如前述[7]或[8]項所述之半導體基板之製造方法，其中，在前述蝕刻步驟中，將Au電極墊上之Au蝕刻成深度1nm以上。
若依據本發明之實施形態，可提供具有Au電極墊且生產性優異之半導體基板及其製造方法。
11‧‧‧鈍化膜
12‧‧‧Au電極墊
13‧‧‧無電解Ni鍍敷皮膜
x‧‧‧Au蝕刻量
第1A圖係在Au電極墊上進行無電解Ni鍍敷後之半導體基板的剖面STEM圖像之概略圖。
第1B圖係第1A圖之部分放大圖，且係表示蝕刻深度之圖。
本發明之半導體基板係具有Au電極墊，並 且在前述Au電極墊上具有無電解Ni鍍敷皮膜/無電解Pd鍍敷皮膜/無電解Au鍍敷皮膜、或無電解Ni鍍敷皮膜/無電解Au鍍敷皮膜。
又，在本發明中，「/」之記號係意指藉由各鍍敷處理步驟所形成之複數個鍍敷皮膜的構造，並以自電極墊起之鍍敷的次序為各鍍敷皮膜之標記順位。
本發明之半導體基板可藉由下述(1)至(6)的步驟，在Au電極墊上形成無電解Ni鍍敷皮膜/無電解Pd鍍敷皮膜/無電解Au鍍敷皮膜、或無電解Ni鍍敷皮膜/無電解Au鍍敷皮膜，藉此來製造。
(1)脫脂步驟；(2)蝕刻步驟；(3)預浸漬步驟；(4)賦予Pd觸媒步驟；(5)無電解Ni鍍敷步驟；以及(6)無電解Pd鍍敷步驟及無電解Au鍍敷步驟、或無電解Au鍍敷步驟。
在本發明中，半導體基板若為具有Au電極墊者即可，可舉例如化合物半導體基板或氧化物半導體基板。又，半導體基板若至少表面為半導體即可，例如設為亦包含具有已形成在異種基板上之磊晶膜等者。異種基板可舉例如藍寶石基板、尖晶石基板、鈣鈦礦系鋁酸釔(YAP)基板、SiC基板、Si基板等。
化合物半導體基板之化合物半導體可舉例如II-VI族 半導體、III-V族半導體、III-V族(氮化物系)半導體、IV-VI族半導體、IV-IV族半導體、I-III-VI族半導體、II-IV-V族半導體等。
II-VI族半導體可舉例如CdTe、CdZnTe、ZnTe、ZnO(亦被分類為氧化物半導體)、ZnS、ZnSe、CdS、HgCdTe等。
III-V族半導體可舉例如GaAs、GaP、AlAs、AlSb、InSb、InAs、GaAsP、InGaAs、InGaP、GaInAsP、AlGaP、AlGaAs、InP、InAlAs、AlGaInP等。
III-V族(氮化物系)半導體可舉例如GaN、GaInN、AlGaN、AlGaInN、AlN等。
IV-VI族半導體可舉例如SnTe、PbTe等。
IV-IV族半導體可舉例如SiC、SiGe等。
I-III-VI族半導體可舉例如CuGaS2、CuInS2、CuGaxIn1-xSe2等。
II-IV-V族半導體可舉例如ZnSiP2、ZnSnAs2等。
又，氧化物半導體基板之氧化物半導體可舉例如ZnO、Ga2O3、Cu2O等。
本發明之半導體基板係具有Au電極墊。Au係化學上安定的金屬，即使使用已知的鋅酸鹽法或Pd觸媒法，亦難以形成無電解Ni鍍敷皮膜。在Au上以室溫之賦予Pd觸媒，難以析出Pd，藉由無電解Ni鍍敷會產生不形成Ni皮膜之處，故無法安定操作。因此，在Au電極墊上鍍敷形成Ni作為UBM時，主要使用電鍍。
又，前述專利文獻1記載在Au上形成無電 解Ni鍍敷皮膜時使用特定之表面活性化液。專利文獻1所記載之表面活性化液係含有(i)錯合劑、(ii)選自由銅鹽及銀鹽所組成之群組的至少一種成分、以及(iii)醛類之水溶液，且使銅鹽或銀鹽吸附於Au表面，以使其後之Pd觸媒的賦予較容易。雖可藉由銅鹽或銀鹽將Pd觸媒賦予至Au上，藉此使Ni鍍敷可被進行，但活性化液中之銅鹽或銀鹽的安定性與在Au表面上之吸附為相反之特性，這2種特性難以併存，且不易控制。
本發明之半導體基板的製造方法係在Au電極墊上進行脫脂、蝕刻後，進行預浸漬，其後賦予觸媒(Pd觸媒)，然後，藉由無電解Ni鍍敷形成Ni皮膜。亦即，本發明係藉由將Au表面稍微蝕刻，而提高Au表面之反應性，使Au表面活性化，使Pd觸媒的賦予較容易。因此，即使在Au電極墊表面不吸附銅鹽或銀鹽，仍可賦予Pd觸媒。又，即使不進行如使用前述專利文獻1所記載之表面活性化液時之用以使銅鹽或銀鹽吸附之複雜的條件控制，仍可在Au電極墊上形成無電解Ni鍍敷皮膜。再者，不利用電鍍，而可利用無電解鍍敷，故可提供成本低且生產性優異之半導體基板的製造方法。
藉由進行蝕刻及預浸漬，可在Au電極墊上形成Pd之皮膜，然後，可形成無電解Ni鍍敷皮膜。
前述Au電極墊可為藉由公知的方法所形成者，墊之厚度較佳為0.05μm至10μm。
前述脫脂步驟、預浸漬步驟、賦予Pd觸媒 步驟、無電解Ni鍍敷步驟、無電解Pd鍍敷步驟、無電解Au鍍敷步驟可使用與在對Al電極墊或Cu電極墊進行無電解Ni鍍敷時相同的市售處理液。使用方法係除了賦予Pd觸媒以外，以製造商推薦之條件進行處理即可。
(脫脂步驟)
為了將半導體基板之Au電極墊上清浄化，首先，進行脫脂處理。有關脫脂步驟，可依附著於半導體基板之污垢種類、半導體基板之抗藥品性而從公知之藥品中選擇。例如，可舉例如鹼脫脂等，可使用WBD200、WBD400(JX金屬公司製)等公知之鹼脫脂劑。
(蝕刻步驟)
蝕刻可使用可蝕刻Au之氰系水溶液或碘水溶液。在前述蝕刻步驟中，為了使Au表面活性化，以將Au電極墊上之Au蝕刻成深度1nm以上為較佳，以1nm以上50nm以下為更佳。蝕刻之深度若為1nm以上，則可充分獲得表面之活性化。即使為50nm以上，亦可發揮效果，但即使蝕刻太多，效果亦不變。但，必須以使Au電極墊不會蝕刻過度而消失之方式控制濃度、時間。例如，使用氰系水溶液時，使用KCN=5g/L，處理30秒左右即可。
蝕刻之深度可藉由STEM分析剖面來測定。
於第1A圖表示在Au電極墊上進行無電解Ni鍍敷後的半導體基板剖面之STEM圖像的概略圖。第1B圖係第1A圖之以虛線包圍之部分的部分放大圖，且係顯示蝕刻深度之圖。
前述半導體基板具有鈍化膜(PV膜)11，且該鈍化膜11具有使前述Au電極墊12露出之開口部時，在未露出Au電極墊12之端部上形成有鈍化膜11。形成有鈍化膜11之部分(Au電極墊未露出之部分)即使進行蝕刻處理亦不會被蝕刻。因此，藉由觀察半導體基板之剖面，並且測定相對於形成有鈍化膜11之部分，未形成鈍化膜之部分的Au電極墊12被削掉何種程度，可求出Au蝕刻量x。無電解Ni鍍敷時Au未被蝕刻，故Au蝕刻量在鍍敷Ni之前後為相同。因此，在Au電極墊12上進行無電解Ni鍍敷而形成無電解Ni鍍敷皮膜13後，將半導體基板之剖面進行STEM分析而將形成有鈍化膜11之部分與未形成鈍化膜11之部分之Au電極墊表面的高度進行比較，藉此，可測定Au蝕刻量(蝕刻之深度)x。
又，亦可在形成無電解Au鍍敷皮膜之後測定Au蝕刻量。
又，構成鈍化膜之材料可為通常使用者，可舉例如氮化矽、氧化矽、聚醯亞胺等。關於鈍化膜之膜厚，氮化矽或氧化矽時若為1μm以下左右，聚醯亞胺時若為0.5μm至15μm左右即可。
又，鈍化膜之形成、在鈍化膜形成開口部而露出Au電極墊之方法係藉由公知之方法、條件進行即可。
(預浸漬步驟)
預浸漬係在賦予Pd觸媒之前浸漬於與賦予觸媒液幾乎相同之酸濃度的水溶液中之處理。預浸漬之功用係提高 親水性而提高對於賦予觸媒液中所含有的Pd離子之附著性、避免水洗水流入賦予觸媒液而可反覆再使用賦予觸媒液者。預浸漬液為鹽酸或硫酸等之水溶液，且依賦予Pd觸媒液之酸而異。又，預浸漬處理係在室溫浸漬數十秒至數分鐘即可，在預浸漬處理後不進行水洗。
(賦予Pd觸媒步驟)
就使用賦予Pd觸媒之處理液而形成Pd之皮膜的方法而言，藉由進行蝕刻及預浸漬，而可於Au電極墊上賦予Pd之觸媒。
有關賦予Pd觸媒，在本發明之半導體基板的製造方法中，從使鍍敷皮膜安定地形成於Au電極墊之觀點而言，較佳係使處理溫度為20℃至90℃。
賦予Pd觸媒之處理液若為市售者即可使用，但較佳係在使用溫度(20℃至90℃)下為安定，以含有作為Pd源之Pd鹽、鹽酸或硫酸、錯合劑等為較佳。
Pd鹽可使用氯化鈀、硫酸鈀、乙酸鈀等。Pd鹽之濃度較佳係在處理液中作為Pd金屬者為5ppm至200ppm，以20ppm至100ppm為更佳。
鹽酸或硫酸較佳係作為濃鹽酸或濃硫酸而以50ml/L至150ml/L被含有。
又，錯合劑可使用氯化銨、硫酸銨等，以含有1g/L至10g/L為較佳。
賦予Pd觸媒時之處理液的溫度以20℃至90℃為較佳，且為了使Pd安定地析出，以將處理時間設 為30秒以上為較佳。若處理溫度為20℃以上，則欲形成於其上之無電解Ni鍍敷容易安定地析出，故以設為20℃以上為較佳。另一方面，若處理溫度為90℃以下，則不會引起處理液之液分解。因此，較佳係將處理液之溫度設為20℃以上、90℃以下而進行，為了更安定地使Pd析出，以40℃至90℃之範圍為更佳，其中，以60℃至80℃之範圍為特佳。一般而言可使用會在室溫賦予Pd觸媒之市售的處理液，此時，處理液之溫度若是在使用溫度下為安定者，則以40℃至90℃之範圍為更佳，以60℃至80℃之範圍為特佳。
又，若處理時間為30秒以上，則欲形成於其上之無電解Ni鍍敷容易安定地析出，故以設為30秒以上為較佳。若考量生產效率，則較佳係將處理時間之上限設為1800秒。
處理方法較佳係Au電極墊接觸20℃至90℃之處理液30秒以上，例如以將Au電極墊浸漬於前述處理液中為較佳，以使用前述處理液作為無電解Pd鍍敷液之無電解鍍敷法為較佳。
在此條件的範圍中，附著於Au電極墊上之Pd雖為無法以STEM剖面觀察檢測出之程度，但繼而藉由無電解Ni鍍敷形成Ni皮膜，可獲得充分之效果。
(無電解Ni鍍敷步驟)
本發明之半導體基板的製造方法係在前述賦予Pd觸媒步驟後，具有無電解Ni鍍敷步驟。
可使用於本發明之無電解Ni鍍敷並無特別限定，但常使用Ni-P、Ni-P-B、Ni-B鍍敷。
無電解Ni鍍敷較佳係無電解Ni-P鍍敷、無電解Ni-P-B鍍敷，更佳為無電解Ni-P鍍敷。所得之Ni鍍敷皮膜較佳係含有15質量%以下之P，更佳係含有2質量%至15質量%之P。
若P為15質量%以下，則Pd鍍敷或Au鍍敷容易析出。
Ni鍍敷皮膜中之P濃度、各鍍敷皮膜的厚度可藉由試料剖面之STEM圖像的由能量分散型X射線分光法(EDX)所得的元素分析而求出。
(無電解Pd鍍敷步驟及無電解Au鍍敷步驟、或無電解Au鍍敷步驟)
本發明之半導體基板係在Au電極墊上具有無電解Ni鍍敷皮膜/無電解Pd鍍敷皮膜/無電解Au鍍敷皮膜、或無電解Ni鍍敷皮膜/無電解Au鍍敷皮膜。
前述無電解Au鍍敷皮膜之形成可設為無電解置換Au鍍敷/無電解還原Au鍍敷之2個階段。
就使用於前述無電解Au鍍敷、無電解Pd鍍敷之鍍敷液、鍍敷方法而言，可使用半導體基板之UBM形成用所使用之公知的鍍敷液、鍍敷方法。
無電解Au鍍敷液有置換Au鍍敷液與還原Au鍍敷液。置換Au鍍敷液可舉例如JX金屬公司製FA-210、FA-500、FA-501、CF-500、CF-500-SS等。其中，FA-210為Ni/Pd/Au 規格的置換Au鍍敷液。另一方面，FA-500、FA-501、CF-500、CF-500-SS為Ni/Au規格的置換Au鍍敷液。還原Au鍍敷液可使用例如JX金屬公司製RAP-13。
又，無電解Pd鍍敷液可較宜使用例如JX金屬公司製CA-400等。
各鍍敷之膜厚係依半導體基板之用途或要求的特性而改變，但無電解Ni鍍敷皮膜之膜厚，在焊接時，從防止焊料擴散的觀點而言，以1μm至15μm為較佳，更佳係1.5μm至10μm。又，關於無電解Au鍍敷皮膜之膜厚，在焊接中，從潤濕性的觀點而言，在Ni/Pd/Au規格及Ni/Au規格中，以0.01μm以上為較佳，兩規格的較佳之膜厚範圍為0.01μm至0.50μm。又，從防止Ni擴散之觀點而言，當使無電解Pd鍍敷皮膜介入而設為Ni/Pd/Au時，無電解Pd鍍敷皮膜之膜厚必須為0.02μm以上，較佳係0.02μm至0.50μm。
有關Au膜厚，在置換Au鍍敷中膜厚會出現限制。在Ni/Pd/Au規格的情況，成膜幾乎止於0.03μm，在Ni/Au規格的情況，成膜幾乎止於0.05μm，故當必須為其以上之膜厚時，則進行還原Au鍍敷，並進行厚膜化。
上述鍍敷皮膜之膜厚的測定係測定電極墊中央附近之鍍敷皮膜表面/界面會成為與電極墊平行的面之部分之膜厚。
藉由本發明而形成於Au電極墊上之無電解Ni鍍敷可適宜使用來作為防止焊料凸塊擴散至Au電極之 UBM。藉由使用由本發明所得之UBM，可抑制成本且製造生產性優異之半導體基板。
本發明係不受限於各實施形態，可在不超出其要旨之範圍內改變構成要素並具體化。又，可藉由各實施形態所記載之複數個構成要素的適當組合而形成各種發明。例如，亦可從實施形態所示之全部構成要素中刪除一些構成要素。亦可進一步適當組合相異之實施形態的構成要素。
[實施例]
以下表示本發明之具體例，但此等實施例係為了更充分理解本發明及其優點而說明者，並非意圖限定發明。
[實施例1]至[實施例11]、[比較例1]、[比較例2]
使用具有以下之電極墊及鈍化膜的GaAs晶圓，依據下述表1所記載之製程及條件而實施無電解鍍敷，獲得半導體基板。
GaAs晶圓
‧電極：Au電極墊、膜厚1μm、墊開口直徑80μm圓形
‧鈍化膜：SiN厚度0.5μm+聚醯亞胺厚度3μm
在表1中，「○」表示進行該處理。
又，比較例2係以一般的Al墊所使用的鋅酸鹽製程的前處理而進行脫脂、蝕刻後，將預浸漬、賦予Pd觸媒改為進行酸浸漬、一次鋅酸鹽處理、酸浸漬、二次鋅酸鹽 處理，然後，進行無電解Ni鍍敷。酸浸漬係使用30%硝酸，一次鋅酸鹽處理及二次鋅酸鹽處理係以表1所記載之條件進行。
為了確認所得之無電解鍍敷在Au電極墊上之析出性，進行鍍敷後之外觀的顯微鏡觀察及從剖面SEM之鍍敷皮膜狀態的觀察，測定鍍敷皮膜之膜厚。將其結果一併記載於表1。
藉由鍍敷後之剖面STEM觀察而求出Au蝕刻量。具有前述Au電極墊及鈍化膜之GaAs晶圓係在形成有Au電極墊之基板上表面形成鈍化膜後，在鈍化膜形成使前述Au電極墊露出之開口部(直徑80μm)者，在未露出Au電極墊之端部上形成鈍化膜。GaAs晶圓之形成有鈍化膜的部分(未被開口之部分)在蝕刻後Au亦未被蝕刻。因此，藉由觀察Au電極墊之端部的剖面，測定相對於形成有鈍化膜之部分(未被開口之部分)，未形成鈍化膜之部分(墊開口之部分)的Au被削去何種程度，求出Au蝕刻量。
又，藉由EDX分析來測定Ni皮膜中之P濃度。
將其結果一併記載於表1。
對於鍍敷良好地析出者係實施焊料特性評估。搭載Sn-3%Ag-0.5%Cu焊球(150μm徑)，以下述之條件回焊(1次、及5次)而形成焊料凸塊後，進行剖面SEM觀察，藉由辨別Ni鍍敷皮膜、及Ni與焊料之金屬間化合物，來確認焊料是否未擴散至Au電極墊(確認Ni是否作為阻隔層而發揮功能)。
又，實施焊料剪切試驗，從破壞界面評估鍍敷之密著性。
焊料特性之結果係僅回焊1次之情形與回焊5次之情形皆成為相同的結果。
回焊加熱條件
溫度：峰頂265℃、在260℃以上加熱40秒
環境：氮環境(氧濃度：600ppm至800ppm)
使用焊球：Sn-3%Ag-0.5%Cu(150μm徑)
焊料剪切試驗條件
焊料剪切速度：100μm/秒
焊料剪切高度：距離鍍敷/焊料接合面為10μm
如表1所示，在實施例1至11中無電解鍍敷良好地析出，焊料剪切試驗所致之破壞界面全部為焊料面，鍍敷/焊料界面之密著性亦良好，且為可充分使用來作為UBM者。
[實施例12]至[實施例22]、[比較例3]、[比 較例4]
除了在實施例1至實施例11、比較例1、及比較例2中，使用具有以下之電極墊及鈍化膜的SiC晶圓來取代前述GaAs晶圓以外，其餘係與實施例1至實施例11、比較例1、及比較例2同樣方式，獲得實施例12至實施例22、比較例3、及比較例4之半導體基板，並與實施例1同樣地評估。其結果，可獲得與實施例1至實施例11、比較例1、及比較例2同樣之評估結果。
SiC晶圓
‧電極：Au電極墊、膜厚1μm、墊開口1200μm×800μm長方形
‧鈍化膜：SiN厚度1.0μm+聚醯亞胺厚度5μm
[實施例23]至[實施例33]、[比較例5]、[比較例6]
除了在實施例1至實施例11、比較例1、及比較例2中，使用具有以下之電極墊及鈍化膜的在Si基板上形成有GaN磊晶膜的磊晶晶圓來取代前述GaAs晶圓以外，其餘係與實施例1至實施例11、比較例1、及比較例2同樣方式，獲得實施例23至實施例33、比較例5、及比較例6之半導體基板，並與實施例1同樣地評估。其結果，可獲得與實施例1至實施例11、比較例1、及比較例2同樣的評估結果。
在Si基板上形成有GaN磊晶膜之磊晶晶圓
‧電極：Au電極墊、膜厚1.5μm、 墊開口900μm×600μm長方形
‧鈍化膜：SiN厚度1.0μm+聚醯亞胺厚度5μm
[實施例34]至[實施例44]、[比較例7]、[比較例8]
除了在實施例1至實施例11、比較例1、及比較例2中，使用具有以下之電極墊及鈍化膜的在藍寶石基板上形成有GaN磊晶膜之磊晶晶圓來取代前述GaAs晶圓以外，其餘係與實施例1至實施例11、比較例1、及比較例2同樣方式，獲得實施例34至實施例44、比較例7、及比較例8之半導體基板，並與實施例1同樣地評估。其結果，可獲得與實施例1至實施例11、比較例1、及比較例2同樣的評估結果。
在藍寶石基板上形成有GaN磊晶膜之磊晶晶圓
‧電極：Au電極墊、膜厚0.5μm、墊開口60μm×60μm正方形
‧鈍化膜：SiN，厚度0.5μm
[實施例45]至[實施例55]、[比較例9]、[比較例10]
除了在實施例1至實施例11、比較例1、及比較例2中，使用具有以下之電極墊及鈍化膜的CdTe晶圓來取代前述GaAs晶圓以外，其餘係與實施例1至實施例11、比較例1、及比較例2同樣方式，獲得實施例45至實施例55、比較例9、及比較例10之半導體基板，並與實施例1同樣地評估。其結果，可獲得與實施例1至實施例11、比較例 1、及比較例2同樣的評估結果。
CdTe晶圓
‧電極：Au電極墊、膜厚0.1μm、墊開口直徑150μm圓形
‧鈍化膜：正型光阻，厚度3μm

Claims (9)

  1. 一種半導體基板，係具有Au電極墊，且在前述Au電極墊上具有無電解Ni鍍敷皮膜/無電解Pd鍍敷皮膜/無電解Au鍍敷皮膜、或無電解Ni鍍敷皮膜/無電解Au鍍敷皮膜。
  2. 如申請專利範圍第1項所述之半導體基板，其中，在前述無電解Ni鍍敷皮膜/無電解Pd鍍敷皮膜/無電解Au鍍敷皮膜、及無電解Ni鍍敷皮膜/無電解Au鍍敷皮膜中，無電解Ni鍍敷皮膜之膜厚為1.5μm至10μm，無電解Au鍍敷皮膜之膜厚為0.01μm至0.50μm，在前述無電解Ni鍍敷皮膜/無電解Pd鍍敷皮膜/無電解Au鍍敷皮膜中，無電解Pd鍍敷皮膜之膜厚為0.02μm至0.50μm。
  3. 如申請專利範圍第1或2項所述之半導體基板，其中，前述無電解Ni鍍敷皮膜含有2質量%至15質量%之P。
  4. 如申請專利範圍第1或2項所述之半導體基板，其中，前述半導體基板係具有鈍化膜，前述鈍化膜係形成於前述Au電極墊上，且具有使前述Au電極墊露出之開口部，在前述開口部之Au電極墊上，具有無電解Ni鍍敷皮膜/無電解Pd鍍敷皮膜/無電解Au鍍敷皮膜、或無電解Ni鍍敷皮膜/無電解Au鍍敷皮膜，在形成有前述無電解Ni鍍敷皮膜之區域中，前述Au電極墊被蝕刻1nm以上。
  5. 如申請專利範圍第1或2項所述之半導體基板，其中，前述半導體基板為化合物半導體基板、或氧化物半導體基板。
  6. 如申請專利範圍第5項所述之半導體基板，其中，前述化合物半導體基板之化合物半導體為選自II-VI族半導體、III-V族半導體、III-V族(氮化物系)半導體、IV-VI族半導體、IV-IV族半導體、I-III-VI族半導體、及II-IV-V族半導體之任一者。
  7. 一種半導體基板之製造方法，係製造申請專利範圍第1至6項中任一項所述之半導體基板的方法，且該製造方法係藉由下述(1)至(6)所記載的步驟，在Au電極墊上形成無電解Ni鍍敷皮膜/無電解Pd鍍敷皮膜/無電解Au鍍敷皮膜、或無電解Ni鍍敷皮膜/無電解Au鍍敷皮膜，(1)脫脂步驟；(2)蝕刻步驟；(3)預浸漬步驟；(4)賦予Pd觸媒步驟；(5)無電解Ni鍍敷步驟；以及(6)無電解Pd鍍敷步驟及無電解Au鍍敷步驟、或無電解Au鍍敷步驟。
  8. 如申請專利範圍第7項所述之半導體基板之製造方法，其中，在前述賦予Pd觸媒步驟中，使用處理液，並將賦予Pd觸媒時之處理液的溫度設為20℃至90℃。
  9. 如申請專利範圍第7或8項所述之半導體基板之製造方法，其中，在前述蝕刻步驟中，將Au電極墊上之Au蝕刻成深度1nm以上。
TW107139501A 2017-11-16 2018-11-07 半導體基板及其製造方法 TWI679302B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2017221166 2017-11-16
JP2017-221166 2017-11-16
JP2018-166131 2018-09-05
JP2018166131 2018-09-05

Publications (2)

Publication Number Publication Date
TW201928113A TW201928113A (zh) 2019-07-16
TWI679302B true TWI679302B (zh) 2019-12-11

Family

ID=66540185

Family Applications (1)

Application Number Title Priority Date Filing Date
TW107139501A TWI679302B (zh) 2017-11-16 2018-11-07 半導體基板及其製造方法

Country Status (5)

Country Link
EP (1) EP3712298A4 (zh)
KR (1) KR102435669B1 (zh)
CN (1) CN111315918B (zh)
TW (1) TWI679302B (zh)
WO (1) WO2019097979A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7441263B2 (ja) * 2021-05-27 2024-02-29 上村工業株式会社 無電解Ｃｏ－Ｗめっき皮膜、および無電解Ｃｏ－Ｗめっき液

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201343311A (zh) * 2012-03-28 2013-11-01 Senju Metal Industry Co 無鉛焊料錫球

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7413974B2 (en) * 2005-08-04 2008-08-19 Texas Instruments Incorporated Copper-metallized integrated circuits having electroless thick copper bond pads
JP2007177268A (ja) 2005-12-27 2007-07-12 Okuno Chem Ind Co Ltd 無電解ニッケルめっき用貴金属表面活性化液
CN101383335B (zh) * 2007-09-04 2010-06-23 全懋精密科技股份有限公司 半导体封装基板及其制作方法
JP2009263700A (ja) * 2008-04-23 2009-11-12 Bridgestone Corp 無電解めっき前処理剤、光透過性電磁波シールド材の製造方法、光透過性電磁波シールド材
CN101304076B (zh) * 2008-06-23 2010-09-01 中国科学院长春应用化学研究所 一种有机发光显示器件阴极隔离柱的加工方法
CN101634021B (zh) * 2008-07-24 2012-11-07 罗门哈斯电子材料有限公司 无电镀金液
TW201011878A (en) * 2008-09-03 2010-03-16 Phoenix Prec Technology Corp Package structure having substrate and fabrication thereof
JP2011003858A (ja) * 2009-06-22 2011-01-06 Seiko Epson Corp 半導体装置の製造方法
CN101950745A (zh) * 2009-07-10 2011-01-19 南茂科技股份有限公司 半导体封装结构及其制造方法
JP2011026680A (ja) * 2009-07-28 2011-02-10 Renesas Electronics Corp 半導体装置の製造方法及び半導体装置の製造装置
JP5669780B2 (ja) * 2012-03-21 2015-02-18 三菱電機株式会社 半導体装置の製造方法
EP2740818B1 (en) * 2012-12-05 2016-03-30 ATOTECH Deutschland GmbH Method for manufacture of wire bondable and solderable surfaces on noble metal electrodes
JP6232249B2 (ja) * 2013-02-27 2017-11-15 新光電気工業株式会社 半導体装置及び半導体装置の製造方法
EP3165947B1 (en) * 2014-07-03 2021-11-24 JX Nippon Mining & Metals Corporation Radiation detector ubm electrode structure body, radiation detector, and method of manufacturing same
CN105543818B (zh) * 2015-12-29 2017-12-26 潍坊学院 一种优化化学镍钯金镀层的方法及设备
JP6202505B1 (ja) 2016-06-17 2017-09-27 株式会社アイカムス・ラボ 細胞培養装置
JP2018166131A (ja) 2018-08-06 2018-10-25 京セラ株式会社 セルスタック装置、モジュールおよびモジュール収容装置

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201343311A (zh) * 2012-03-28 2013-11-01 Senju Metal Industry Co 無鉛焊料錫球

Also Published As

Publication number Publication date
CN111315918A (zh) 2020-06-19
EP3712298A1 (en) 2020-09-23
WO2019097979A1 (ja) 2019-05-23
TW201928113A (zh) 2019-07-16
KR20200087790A (ko) 2020-07-21
KR102435669B1 (ko) 2022-08-25
EP3712298A4 (en) 2021-08-11
CN111315918B (zh) 2022-07-08

Similar Documents

Publication Publication Date Title
US9564409B2 (en) Methods of forming semiconductor packages with an intermetallic layer comprising tin and at least one of silver, copper or nickel
US9627342B2 (en) Electronic component and method of manufacturing electronic component
TWI591687B (zh) 在貴金屬電極上製造可線接合及可焊接之表面的方法
US20070117475A1 (en) Prevention of Sn whisker growth for high reliability electronic devices
US6716738B2 (en) Method of fabricating multilayered UBM for flip chip interconnections by electroplating
US8426311B2 (en) Method and apparatus for manufacturing semiconductor device
US8338954B2 (en) Semiconductor apparatus and fabrication method thereof
JP2020534695A (ja) 合金拡散障壁層
TWI679302B (zh) 半導體基板及其製造方法
JPH04234126A (ja) 半導体装置の製造方法
JP2017128791A (ja) 無電解Ｎｉめっき皮膜を有する構造物、その製造方法および半導体ウェハ
JP6494899B1 (ja) 半導体基板、及びその製造方法
TWI677594B (zh) 半導體晶圓及其製造方法
CN111354626A (zh) 半导体器件及其制造方法
KR100922233B1 (ko) 무전해 니켈-팔라듐 합금도금을 포함하는 반도체 집적회로칩의 구리패드 구조
US8648466B2 (en) Method for producing a metallization having two multiple alternating metallization layers for at least one contact pad and semiconductor wafer having said metallization for at least one contact pad
Chen et al. Electroless nickel bath for wafer bumping: Influence of additives
Pathak et al. Non-Formaldehyde based electroless Cu deposition for Advanced Packaging
Yang et al. The impact of zincation on the electroless nickel UBM for low cost flip chip technology
JP2017022314A (ja) 半導体用ウェハの処理液、および処理された半導体用ウェハ並びに半導体用ウェハの処理方法
JP2016054179A (ja) 半導体デバイス
TWI409368B (zh) 一種發光元件之製造方法
TW201421636A (zh) 半導體元件中的銅線鍵接結構及其製造方法
Yang et al. Interface reaction of Pb-free Sn-3.5 Ag solder with Ni-Sn-P metallization
JPS63263733A (ja) 半導体装置の製造方法