TWI676210B - 半導體裝置之製造方法 - Google Patents

半導體裝置之製造方法 Download PDF

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Publication number
TWI676210B
TWI676210B TW104143853A TW104143853A TWI676210B TW I676210 B TWI676210 B TW I676210B TW 104143853 A TW104143853 A TW 104143853A TW 104143853 A TW104143853 A TW 104143853A TW I676210 B TWI676210 B TW I676210B
Authority
TW
Taiwan
Prior art keywords
adhesive sheet
semiconductor wafers
semiconductor
manufacturing
wafers
Prior art date
Application number
TW104143853A
Other languages
English (en)
Chinese (zh)
Other versions
TW201635360A (zh
Inventor
岡本直也
Naoya Okamoto
佐藤明徳
Akinori Sato
藤本泰史
Hironobu Fujimoto
毛受利彰
Toshiaki Menjo
山田忠知
Tadatomo Yamada
河崎仁彦
Kimihiko Kawasaki
Original Assignee
日商琳得科股份有限公司
Lintec Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商琳得科股份有限公司, Lintec Corporation filed Critical 日商琳得科股份有限公司
Publication of TW201635360A publication Critical patent/TW201635360A/zh
Application granted granted Critical
Publication of TWI676210B publication Critical patent/TWI676210B/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Dicing (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
TW104143853A 2014-12-26 2015-12-25 半導體裝置之製造方法 TWI676210B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2014266139A JP6482865B2 (ja) 2014-12-26 2014-12-26 半導体装置の製造方法
JP2014-266139 2014-12-26

Publications (2)

Publication Number Publication Date
TW201635360A TW201635360A (zh) 2016-10-01
TWI676210B true TWI676210B (zh) 2019-11-01

Family

ID=56358112

Family Applications (1)

Application Number Title Priority Date Filing Date
TW104143853A TWI676210B (zh) 2014-12-26 2015-12-25 半導體裝置之製造方法

Country Status (2)

Country Link
JP (1) JP6482865B2 (enExample)
TW (1) TWI676210B (enExample)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102571926B1 (ko) * 2017-05-22 2023-08-28 가부시끼가이샤 레조낙 반도체 장치의 제조 방법 및 익스팬드 테이프
JP2019012714A (ja) * 2017-06-29 2019-01-24 株式会社ディスコ 半導体パッケージの製造方法
KR102515684B1 (ko) * 2017-11-16 2023-03-30 린텍 가부시키가이샤 반도체 장치의 제조 방법
CN111295739B (zh) * 2017-11-16 2023-08-25 琳得科株式会社 半导体装置的制造方法
TWI785161B (zh) * 2017-12-07 2022-12-01 日商琳得科股份有限公司 黏著性層積體、黏著性層積體之使用方法及半導體裝置之製造方法
JP7084228B2 (ja) 2018-06-26 2022-06-14 日東電工株式会社 半導体装置製造方法
JP7250468B6 (ja) * 2018-10-12 2023-04-25 三井化学株式会社 電子装置の製造方法および粘着性フィルム
KR102123419B1 (ko) * 2018-10-29 2020-06-17 한국기계연구원 소자 간격 제어가 가능한 시트 및 이를 이용한 소자 간격 제어방법
WO2020158766A1 (ja) * 2019-01-31 2020-08-06 リンテック株式会社 エキスパンド方法及び半導体装置の製造方法
CN114823456B (zh) * 2021-01-19 2025-08-22 矽磐微电子(重庆)有限公司 转膜治具及芯片贴片方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010058646A1 (ja) * 2008-11-21 2010-05-27 インターナショナル・ビジネス・マシーンズ・コーポレーション 半導体パッケージおよびその製造方法
JP2011096961A (ja) * 2009-11-02 2011-05-12 Citizen Electronics Co Ltd Ｌｅｄ素子の製造方法
WO2014002535A1 (ja) * 2012-06-29 2014-01-03 シャープ株式会社 半導体装置の製造方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011077235A (ja) * 2009-09-30 2011-04-14 Nitto Denko Corp 素子保持用粘着シートおよび素子の製造方法
JP5460374B2 (ja) * 2010-02-19 2014-04-02 シチズン電子株式会社 半導体装置の製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010058646A1 (ja) * 2008-11-21 2010-05-27 インターナショナル・ビジネス・マシーンズ・コーポレーション 半導体パッケージおよびその製造方法
JP2011096961A (ja) * 2009-11-02 2011-05-12 Citizen Electronics Co Ltd Ｌｅｄ素子の製造方法
WO2014002535A1 (ja) * 2012-06-29 2014-01-03 シャープ株式会社 半導体装置の製造方法

Also Published As

Publication number Publication date
TW201635360A (zh) 2016-10-01
JP2016127115A (ja) 2016-07-11
JP6482865B2 (ja) 2019-03-13

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