JP6482865B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP6482865B2
JP6482865B2 JP2014266139A JP2014266139A JP6482865B2 JP 6482865 B2 JP6482865 B2 JP 6482865B2 JP 2014266139 A JP2014266139 A JP 2014266139A JP 2014266139 A JP2014266139 A JP 2014266139A JP 6482865 B2 JP6482865 B2 JP 6482865B2
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JP
Japan
Prior art keywords
adhesive sheet
semiconductor chips
pressure
sensitive adhesive
semiconductor
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Active
Application number
JP2014266139A
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English (en)
Japanese (ja)
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JP2016127115A (ja
JP2016127115A5 (enExample
Inventor
岡本　直也
直也 岡本
明徳 佐藤
明徳 佐藤
泰史 藤本
泰史 藤本
利彰 毛受
利彰 毛受
忠知 山田
忠知 山田
仁彦 河崎
仁彦 河崎
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Lintec Corp
Original Assignee
Lintec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
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Priority to JP2014266139A priority Critical patent/JP6482865B2/ja
Priority to TW104143853A priority patent/TWI676210B/zh
Publication of JP2016127115A publication Critical patent/JP2016127115A/ja
Publication of JP2016127115A5 publication Critical patent/JP2016127115A5/ja
Application granted granted Critical
Publication of JP6482865B2 publication Critical patent/JP6482865B2/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Dicing (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
JP2014266139A 2014-12-26 2014-12-26 半導体装置の製造方法 Active JP6482865B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2014266139A JP6482865B2 (ja) 2014-12-26 2014-12-26 半導体装置の製造方法
TW104143853A TWI676210B (zh) 2014-12-26 2015-12-25 半導體裝置之製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2014266139A JP6482865B2 (ja) 2014-12-26 2014-12-26 半導体装置の製造方法

Publications (3)

Publication Number Publication Date
JP2016127115A JP2016127115A (ja) 2016-07-11
JP2016127115A5 JP2016127115A5 (enExample) 2017-11-16
JP6482865B2 true JP6482865B2 (ja) 2019-03-13

Family

ID=56358112

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2014266139A Active JP6482865B2 (ja) 2014-12-26 2014-12-26 半導体装置の製造方法

Country Status (2)

Country Link
JP (1) JP6482865B2 (enExample)
TW (1) TWI676210B (enExample)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102571926B1 (ko) * 2017-05-22 2023-08-28 가부시끼가이샤 레조낙 반도체 장치의 제조 방법 및 익스팬드 테이프
JP2019012714A (ja) * 2017-06-29 2019-01-24 株式会社ディスコ 半導体パッケージの製造方法
KR102515684B1 (ko) * 2017-11-16 2023-03-30 린텍 가부시키가이샤 반도체 장치의 제조 방법
CN111295739B (zh) * 2017-11-16 2023-08-25 琳得科株式会社 半导体装置的制造方法
TWI785161B (zh) * 2017-12-07 2022-12-01 日商琳得科股份有限公司 黏著性層積體、黏著性層積體之使用方法及半導體裝置之製造方法
JP7084228B2 (ja) 2018-06-26 2022-06-14 日東電工株式会社 半導体装置製造方法
JP7250468B6 (ja) * 2018-10-12 2023-04-25 三井化学株式会社 電子装置の製造方法および粘着性フィルム
KR102123419B1 (ko) * 2018-10-29 2020-06-17 한국기계연구원 소자 간격 제어가 가능한 시트 및 이를 이용한 소자 간격 제어방법
WO2020158766A1 (ja) * 2019-01-31 2020-08-06 リンテック株式会社 エキスパンド方法及び半導体装置の製造方法
CN114823456B (zh) * 2021-01-19 2025-08-22 矽磐微电子(重庆)有限公司 转膜治具及芯片贴片方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010058646A1 (ja) * 2008-11-21 2010-05-27 インターナショナル・ビジネス・マシーンズ・コーポレーション 半導体パッケージおよびその製造方法
JP2011077235A (ja) * 2009-09-30 2011-04-14 Nitto Denko Corp 素子保持用粘着シートおよび素子の製造方法
JP5350980B2 (ja) * 2009-11-02 2013-11-27 シチズン電子株式会社 Ｌｅｄ素子の製造方法
JP5460374B2 (ja) * 2010-02-19 2014-04-02 シチズン電子株式会社 半導体装置の製造方法
WO2014002535A1 (ja) * 2012-06-29 2014-01-03 シャープ株式会社 半導体装置の製造方法

Also Published As

Publication number Publication date
TWI676210B (zh) 2019-11-01
TW201635360A (zh) 2016-10-01
JP2016127115A (ja) 2016-07-11

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