JP6482865B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  In recent years, electronic devices have been reduced in size, weight, and functionality. Semiconductor devices mounted on electronic devices are also required to be smaller, thinner, and higher in density. A semiconductor chip may be mounted in a package close to its size. Such a package may be referred to as a chip scale package (CSP). As one of CSPs, there is a wafer level package (WLP). In WLP, before dicing into individual pieces, external electrodes and the like are formed on the wafer, and finally the wafer is diced into individual pieces. Examples of WLP include a fan-in type and a fan-out type. In a fan-out type WLP (hereinafter sometimes abbreviated as FO-WLP), a semiconductor chip sealing body is formed by covering a semiconductor chip with a sealing member so as to be an area larger than the chip size. The rewiring layer and the external electrode are formed not only on the circuit surface of the semiconductor chip but also on the surface region of the sealing member.

  For example, in Patent Document 1, an extended wafer is formed by enclosing a plurality of semiconductor chips separated from a semiconductor wafer, leaving a circuit formation surface thereof, and surrounding with a mold member, in a region outside the semiconductor chip. A method for manufacturing a semiconductor package formed by extending a rewiring pattern is described. In the manufacturing method described in Patent Document 1, before enclosing a plurality of individual semiconductor chips with a mold member, the semiconductor chip is replaced with an expandable wafer mount tape, and the wafer mount tape is spread to expand the plurality of semiconductor chips. The distance between them is expanding.

International Publication No. 2010/058646

  There is a possibility that the distance between the plurality of semiconductor chips cannot be sufficiently increased only by performing the expanding process once after the separation. On the other hand, if a sheet for supporting a plurality of semiconductor chips is forcibly extended in one expanding process, the sheet may be broken or torn. As a result, the semiconductor chips on the sheet may be spaced apart from each other, or the semiconductor chips may be detached from the sheet, and the handling of the semiconductor chips may be reduced.

  An object of the present invention is to provide a method of manufacturing a semiconductor device that can greatly increase the interval between a plurality of semiconductor chips without deteriorating the handling of the semiconductor chips.

According to one aspect of the present invention, the step of dicing the wafer attached to the first pressure-sensitive adhesive sheet to form a plurality of semiconductor chips, and extending the first pressure-sensitive adhesive sheet, the plurality of semiconductors stretching a step of widening the interval between chips, the plurality of semiconductor chips, a step of transferring the second tacky Chakushi over preparative, a step of peeling the first adhesive sheet, the second adhesive sheet And a step of further widening the interval between the plurality of semiconductor chips.

According to such an aspect of the present invention, even when a cut is formed in the first pressure-sensitive adhesive sheet beyond the thickness of the wafer when the wafer is diced, in the step of stretching the first pressure-sensitive adhesive sheet, It is possible to prevent the first pressure-sensitive adhesive sheet from tearing as a result of the incision. Furthermore, according to one aspect of the present invention, the interval between the plurality of semiconductor chips transferred to the second pressure-sensitive adhesive sheet can be further expanded. After the dicing process, if the interval between the plurality of semiconductor chips is to be greatly expanded only by one expansion process, the pressure-sensitive adhesive sheet may be broken or torn. As a result, the intervals between the plurality of semiconductor chips on the pressure-sensitive adhesive sheet vary, or the plurality of semiconductor chips are detached from the pressure-sensitive adhesive sheet, so that the handling of the semiconductor chips in the subsequent process is deteriorated.
According to the above-described aspect of the present invention, since the process of extending the pressure-sensitive adhesive sheet is provided over a plurality of stages, the interval between the plurality of semiconductor chips can be greatly widened without reducing the handleability of the semiconductor chips.

  According to one embodiment of the present invention described above, a plurality of semiconductor chips formed by dicing are picked up, and the interval between the plurality of semiconductor chips is increased without going through a process of widening the interval and rearranging the chips on the support member. Can be expanded. Therefore, the above-described method for manufacturing a semiconductor device according to one embodiment of the present invention is excellent in adaptability to a WLP manufacturing process, and particularly excellent in adaptability to a fan-out type wafer level package manufacturing process. Specifically, according to one embodiment of the present invention, the uniformity and accuracy of chip intervals in FO-WLP can be improved.

In one aspect of the present invention, the first pressure-sensitive adhesive sheet has a first base film and a first pressure-sensitive adhesive layer, and the second pressure-sensitive adhesive sheet has a second base film, A second pressure-sensitive adhesive layer, and the plurality of semiconductor chips are arranged in the second direction so that the MD direction of the first base film and the MD direction of the second base film are orthogonal to each other. It is also preferable to transfer to an adhesive sheet.
According to this aspect, in the first expanding step of stretching the first pressure-sensitive adhesive sheet and the second expanding step of stretching the second pressure-sensitive adhesive sheet, a plurality of semiconductor chips are arranged so that the MD directions of the base film are orthogonal to each other. Transcript. Since the direction in which the base film is easily stretched is orthogonal in the first expanding process and the second expanding process, the interval between the plurality of semiconductor chips is expanded more uniformly after the second expanding process is performed. . For example, when the semiconductor chips are divided into a plurality of semiconductor chips along the grid-like division lines, according to this aspect, the intervals between the plurality of semiconductor chips are more uniformly extended in the vertical direction and the horizontal direction.
In the present specification, the “MD direction” is used as a word indicating a direction parallel to the longitudinal direction of the original fabric giving the base film (the feed direction during the production of the original fabric), and the same applies to the following. . In this specification, MD is an abbreviation for Machine Direction.

1 aspect of this invention WHEREIN: It is also preferable that said 2nd adhesive sheet has a tensile elasticity modulus smaller than said 1st adhesive sheet.
According to this aspect, in the second expanding step of extending the second pressure-sensitive adhesive sheet, it is easy to greatly increase the interval between the plurality of semiconductor chips.

1 aspect of this invention WHEREIN: After extending said 2nd adhesive sheet and expanding the space | interval of these semiconductor chips, it further includes the process of leaving the circuit surface of these semiconductor chips, and covering with a sealing member. It is also preferable.
According to this aspect, it is possible to cover the plurality of semiconductor chips with the sealing member after greatly increasing the interval between the plurality of semiconductor chips without reducing the handling of the semiconductor chips. Moreover, according to this aspect, the separated semiconductor chips can be sealed one by one with the sealing member without being rearranged by pick and place from the first adhesive sheet to another adhesive sheet or support. Can be covered. Soreyu example, according to this embodiment, it is possible to simplify the manufacturing process step of the WLP.

In one aspect of the present invention, after extending the second pressure-sensitive adhesive sheet to increase the interval between the plurality of semiconductor chips, the step of transferring the plurality of semiconductor chips to a holding surface of a holding member; and the holding surface Inserting a contact means between the plurality of semiconductor chips held in the step, relatively moving the contact means and the holding surface, and aligning the semiconductor chips on the holding surface, It is also preferable to further comprise.
According to this aspect, after the second expanding step of extending the second pressure-sensitive adhesive sheet, the plurality of semiconductor chips are transferred to the holding surface of the holding member, and the contact means and the holding surface are relatively moved to move the semiconductor chip. Can be aligned. Without being affected by the stress of the second pressure-sensitive adhesive sheet in the second expanding step, the interval between the semiconductor chips can be adjusted more accurately or further expanded.
According to this aspect, since the plurality of semiconductor chips are transferred to the holding surface of the holding member after the second expanding step, the interval between the plurality of semiconductor chips transferred to the holding surface is large. Therefore, when the contact means is inserted between the plurality of semiconductor chips, the contact means can be prevented from coming into contact with the surface of the semiconductor chip.

Sectional drawing explaining the manufacturing method which concerns on 1st embodiment. Sectional drawing explaining the manufacturing method which concerns on 1st embodiment following FIG. The top view explaining the manufacturing method concerning a first embodiment. Sectional drawing explaining the manufacturing method which concerns on 1st embodiment following FIG. Sectional drawing explaining the manufacturing method which concerns on 1st embodiment following FIG. Sectional drawing explaining the manufacturing method which concerns on 1st embodiment following FIG. The side view explaining the manufacturing method which concerns on 3rd embodiment. The side view explaining the manufacturing method which concerns on 4th embodiment. The top view explaining the manufacturing method concerning a fourth embodiment. It is a side view explaining the manufacturing method which concerns on the modification of embodiment.

[First embodiment]
Hereinafter, a method for manufacturing the semiconductor device according to the present embodiment will be described.

FIG. 1A shows a semiconductor wafer W adhered to the first pressure-sensitive adhesive sheet 10. The semiconductor wafer W has a circuit surface W1, and a circuit W2 is formed on the circuit surface W1. The first adhesive sheet 10 is attached to the back surface W3 of the semiconductor wafer W opposite to the circuit surface W1.
The semiconductor wafer W may be, for example, a silicon wafer or a compound semiconductor wafer such as gallium / arsenic. Examples of a method for forming the circuit W2 on the circuit surface W1 of the semiconductor wafer W include a widely used method, and examples thereof include an etching method and a lift-off method.
The semiconductor wafer W is ground to a predetermined thickness in advance, and is attached to the first adhesive sheet 10 with the back surface W3 exposed. The method for grinding the semiconductor wafer W is not particularly limited, and examples thereof include a known method using a grinder. When grinding the semiconductor wafer W, a surface protective sheet is adhered to the circuit surface W1 in order to protect the circuit W2. In the backside grinding of the wafer, the circuit surface W1 side of the semiconductor wafer W, that is, the surface protection sheet side is fixed by a chuck table or the like, and the backside where no circuit is formed is ground by a grinder. The thickness of the semiconductor wafer W after grinding is not particularly limited, and is usually 20 μm or more and 500 μm or less.

The first pressure-sensitive adhesive sheet 10 has a first base film 11 and a first pressure-sensitive adhesive layer 12. The first pressure-sensitive adhesive layer 12 is laminated on the first base film 11.
The first adhesive sheet 10 may be attached to the semiconductor wafer W and the first ring frame. In this case, the first ring frame and the semiconductor wafer W are placed on the first pressure-sensitive adhesive layer 12 of the first pressure-sensitive adhesive sheet 10, and these are lightly pressed and fixed.

  The material of the first base film 11 is not particularly limited. Examples of the material of the first base film 11 include polyvinyl chloride resin, polyester resin (polyethylene terephthalate, etc.), acrylic resin, polycarbonate resin, polyethylene resin, polypropylene resin, acrylonitrile / butadiene / styrene resin, polyimide resin, and polyurethane. Examples thereof include resins and polystyrene resins.

  The pressure-sensitive adhesive contained in the first pressure-sensitive adhesive layer 12 is not particularly limited and can be widely applied. Examples of the pressure-sensitive adhesive contained in the first pressure-sensitive adhesive layer 12 include rubber-based, acrylic-based, silicone-based, polyester-based, and urethane-based materials. In addition, the kind of adhesive is selected in consideration of the use, the kind of adherend to be attached, and the like.

  When the energy ray polymerizable compound is blended in the first pressure-sensitive adhesive layer 12, the first pressure-sensitive adhesive layer 12 is irradiated with energy rays from the first base film 11 side, and the energy ray polymerizable compound is irradiated. Is cured. When the energy beam polymerizable compound is cured, the cohesive force of the first pressure-sensitive adhesive layer 12 is increased, and the pressure-sensitive adhesive force between the first pressure-sensitive adhesive layer 12 and the semiconductor wafer W can be reduced or eliminated. Examples of the energy rays include ultraviolet rays (UV) and electron beams (EB), and ultraviolet rays are preferable.

[Dicing process]
FIG. 1B shows a plurality of semiconductor chips CP held on the first pressure-sensitive adhesive sheet 10.
The semiconductor wafer W held on the first adhesive sheet 10 is divided into pieces by dicing, and a plurality of semiconductor chips CP are formed. A cutting means such as a dicing saw is used for dicing. The cutting depth at the time of dicing is set to a depth that takes into account the total thickness of the semiconductor wafer W, the first pressure-sensitive adhesive layer 12, and the wear of the dicing saw. The first pressure-sensitive adhesive layer 12 is also cut into the same size as the semiconductor chip CP by dicing. Furthermore, a cut may be formed in the first base film 11 by dicing.

  Irradiation of energy rays to the first pressure-sensitive adhesive layer 12 is performed at any stage after the semiconductor wafer W is adhered to the first pressure-sensitive adhesive sheet 10 and before the first pressure-sensitive adhesive sheet 10 is peeled off. May be. Irradiation of energy rays may be performed after dicing, for example, or may be performed after an expanding step described later. The energy rays may be irradiated in a plurality of times.

[First expanding process]
FIG. 1C shows a diagram illustrating a process of extending the first adhesive sheet 10 that holds a plurality of semiconductor chips CP (sometimes referred to as a first expanding process).
After dicing into several semiconductor chips CP by dicing, the 1st adhesive sheet 10 is extended and the space | interval between several semiconductor chips CP is expanded. The method for extending the first pressure-sensitive adhesive sheet 10 in the first expanding step is not particularly limited. Examples of the method of stretching the first pressure-sensitive adhesive sheet 10 include a method of stretching the first pressure-sensitive adhesive sheet 10 by pressing an annular or circular expander, and an outer periphery of the first pressure-sensitive adhesive sheet 10 using a gripping member or the like. For example, a method of grasping and extending the part.

  In this embodiment, as shown in FIG. 1C, the distance between the semiconductor chips CP is D1. The distance D1 is preferably 15 μm or more and 110 μm or less, for example.

[Transfer process]
FIG. 2A shows a diagram for explaining a process of transferring a plurality of semiconductor chips CP to the second adhesive sheet 20 (sometimes referred to as a transfer process) after the first expanding process. Yes. After extending the first adhesive sheet 10 to increase the distance D1 between the plurality of semiconductor chips CP, the second adhesive sheet 20 is adhered to the circuit surface W1 of the semiconductor chip CP.

The second pressure-sensitive adhesive sheet 20 has a second base film 21 and a second pressure-sensitive adhesive layer 22. It is preferable that the 2nd adhesive sheet 20 is stuck so that the circuit surface W1 may be covered with the 2nd adhesive layer 22. FIG.
The material of the second base film 21 is not particularly limited. Examples of the material of the second base film 21 include the same materials as those exemplified for the first base film 11.

  The second pressure-sensitive adhesive layer 22 is laminated on the second base film 21. The pressure-sensitive adhesive contained in the second pressure-sensitive adhesive layer 22 is not particularly limited and can be widely applied. As an adhesive contained in the 2nd adhesive layer 22, the adhesive similar to the adhesive demonstrated about the 1st adhesive layer 12 is mentioned, for example. In addition, the kind of adhesive is selected in consideration of the use, the kind of adherend to be attached, and the like. The second pressure-sensitive adhesive layer 22 may also contain an energy ray polymerizable compound.

  The second pressure-sensitive adhesive sheet 20 preferably has a smaller tensile elastic modulus than the first pressure-sensitive adhesive sheet 10. The tensile modulus of the second pressure-sensitive adhesive sheet 20 is preferably 10 MPa or more and 2000 MPa or less. The breaking elongation of the second pressure-sensitive adhesive sheet 20 is also preferably 50% or more.

  The adhesive force of the second pressure-sensitive adhesive layer 22 is preferably larger than the pressure-sensitive adhesive force of the first pressure-sensitive adhesive layer 12. If the adhesive force of the second pressure-sensitive adhesive layer 22 is greater, the first pressure-sensitive adhesive sheet 10 can be easily peeled after the plurality of semiconductor chips CP are transferred to the second pressure-sensitive adhesive sheet 20.

  The second pressure-sensitive adhesive sheet 20 preferably has heat resistance. When the sealing member to be described later is a thermosetting resin, for example, the curing temperature is about 120 ° C. to 180 ° C., and the heating time is about 30 minutes to 2 hours. The second pressure-sensitive adhesive sheet 20 preferably has heat resistance such that wrinkles do not occur when the sealing member is thermoset. Moreover, it is preferable that the 2nd adhesive sheet 20 is comprised with the material which can peel from the semiconductor chip CP after a thermosetting process.

  The second adhesive sheet 20 may be attached to the plurality of semiconductor chips CP and the second ring frame. In this case, the second ring frame is placed on the second pressure-sensitive adhesive layer 22 of the second pressure-sensitive adhesive sheet 20, and this is lightly pressed and fixed. Thereafter, the second pressure-sensitive adhesive layer 22 exposed inside the ring shape of the second ring frame is pressed against the circuit surface W1 of the semiconductor chip CP to fix the plurality of semiconductor chips CP to the second pressure-sensitive adhesive sheet 20. To do.

FIG. 3 shows a plan view of the plurality of semiconductor chips CP attached to the first adhesive sheet 10 and the second adhesive sheet 20 as viewed from the second adhesive sheet 20 side. When sticking the 2nd adhesive sheet 20 on the circuit surface W1, it is preferable to make MD direction M1 of the 1st base film 11 and MD direction M2 of the 2nd base film 21 orthogonal. By sticking in this way, the direction in which the base film is easily stretched is orthogonal to the first expanding step and the second expanding step of stretching the second adhesive sheet 20 described later. Therefore, the interval between the plurality of semiconductor chips CP is more uniformly expanded by performing the second expanding step.
For example, the amount of extension extending along a direction that is easily stretched in the first expanding step (sometimes referred to as a first direction) and a direction orthogonal to the first direction (a direction that is less likely to stretch than the first direction). In the second expanding step, it may be referred to as the second direction.) When the amount of extension extending along the second direction is different, the direction in which the second base film 21 is easily extended is matched with the second direction. The extension amount in the second direction can be made larger than that in the first direction, and the intervals between the plurality of semiconductor chips CP can be adjusted more uniformly. For example, when the semiconductor chips CP are separated into pieces along the grid-like division planned lines, according to this aspect, the intervals between the semiconductor chips CP are more uniformly expanded in the vertical direction and the horizontal direction. Is done.
In addition, MD direction M1 of the 1st base film 11 and MD direction M2 of the 2nd base film 21 are not limited to the direction of each arrow shown by FIG.

  When the first pressure-sensitive adhesive sheet 10 is peeled off after the second pressure-sensitive adhesive sheet 20 is adhered, the back surfaces W3 of the plurality of semiconductor chips CP are exposed. Even after the first pressure-sensitive adhesive sheet 10 is peeled, it is preferable that the distance D1 between the plurality of semiconductor chips CP expanded in the first expanding step is maintained. When the energy ray polymerizable compound is blended in the first pressure-sensitive adhesive layer 12, the first pressure-sensitive adhesive layer 12 is irradiated with energy rays from the first base film 11 side, and the energy ray polymerizable compound is irradiated. It is preferable to peel the first pressure-sensitive adhesive sheet 10 after curing.

[Second expanding process]
FIG. 2B shows a diagram for explaining a process of extending the second adhesive sheet 20 holding the plurality of semiconductor chips CP (sometimes referred to as a second expanding process).
In the second expanding step, the interval between the plurality of semiconductor chips CP is further expanded. The method of extending the second adhesive sheet 20 in the second expanding step is not particularly limited. Examples of the method of stretching the second pressure-sensitive adhesive sheet 20 include a method of stretching the second pressure-sensitive adhesive sheet 20 by pressing an annular or circular expander, and an outer peripheral portion of the second pressure-sensitive adhesive sheet using a gripping member or the like. For example, a method of grabbing and stretching.

  In the present embodiment, as shown in FIG. 2B, the interval between the semiconductor chips CP after the second expanding process is D2. The distance D2 is larger than the distance D1. For example, the distance D2 is preferably 200 μm or more and 5000 μm or less.

[Sealing process]
FIG. 4 is a diagram illustrating a process of sealing a plurality of semiconductor chips CP using the sealing member 30 (sometimes referred to as a sealing process).
The sealing step is performed after the second expanding step. The sealing body 3 is formed by covering the plurality of semiconductor chips CP with the sealing member 30 while leaving the circuit surface W1. A sealing member 30 is also filled between the plurality of semiconductor chips CP. In this embodiment, since the circuit surface W1 and the circuit W2 are covered with the second adhesive sheet 20, it is possible to prevent the circuit surface W1 from being covered with the sealing member 30.

By the sealing process, the sealing body 3 in which a plurality of semiconductor chips CP separated by a predetermined distance are embedded in the sealing member is obtained. In the sealing step, the plurality of semiconductor chips CP are preferably covered with the sealing member 30 in a state where the distance D2 is maintained.
A method for covering the plurality of semiconductor chips CP with the sealing member 30 is not particularly limited. For example, a method in which a plurality of semiconductor chips CP are accommodated in a mold while the circuit surface W1 is covered with the second adhesive sheet 20, a fluid resin material is injected into the mold, and the resin material is cured. It may be adopted. Further, a method of embedding the plurality of semiconductor chips CP in the sealing resin by placing the sheet-shaped sealing resin so as to cover the back surfaces W3 of the plurality of semiconductor chips CP and heating the sealing resin is adopted. May be. Examples of the material of the sealing member 30 include an epoxy resin. The epoxy resin used as the sealing member 30 may include, for example, a phenol resin, an elastomer, an inorganic filler, a curing accelerator, and the like.

  After the sealing step, when the second pressure-sensitive adhesive sheet 20 is peeled off, the surface 3A that has been in contact with the circuit surface W1 of the semiconductor chip CP and the second pressure-sensitive adhesive sheet 20 of the sealing body 3 is exposed.

[Semiconductor package manufacturing process]
5 and 6 are diagrams for explaining a process for manufacturing a semiconductor package using a plurality of semiconductor chips CP. The present embodiment preferably includes a manufacturing process of such a semiconductor package.

[Rewiring layer formation process]
FIG. 5A shows a cross-sectional view of the sealing body 3 after the second pressure-sensitive adhesive sheet 20 is peeled off. In this embodiment, it is preferable to further include a rewiring layer forming step of forming a rewiring layer on the sealing body 3 after the second pressure-sensitive adhesive sheet 20 is peeled off. In the rewiring layer forming step, rewirings connected to the circuits W2 of the plurality of exposed semiconductor chips CP are formed on the circuit surface W1 and the surface 3A of the sealing body 3. In forming the rewiring, first, an insulating layer is formed on the sealing body 3.

  FIG. 5B is a cross-sectional view illustrating a process of forming the first insulating layer 41 on the circuit surface W1 of the semiconductor chip CP and the surface 3A of the sealing body 3. A first insulating layer 41 containing an insulating resin is formed on the circuit surface W1 and the surface 3A so as to expose the circuit W2 or the internal terminal electrode W4 of the circuit W2. Examples of the insulating resin include polyimide resin, polybenzoxazole resin, and silicone resin. The material of the internal terminal electrode W4 is not limited as long as it is a conductive material, and examples thereof include gold, silver, metals such as copper and aluminum, and alloys.

  FIG. 5C is a cross-sectional view illustrating a process of forming the rewiring 5 that is electrically connected to the semiconductor chip CP sealed in the sealing body 3. In the present embodiment, the rewiring 5 is formed following the formation of the first insulating layer 41. The material of the rewiring 5 is not limited as long as it is a conductive material, and examples thereof include gold, silver, metals such as copper and aluminum, and alloys. The rewiring 5 can be formed by a known method.

  FIG. 6A is a cross-sectional view illustrating a process of forming the second insulating layer 42 that covers the rewiring 5. The rewiring 5 has external electrode pads 5A for external terminal electrodes. The second insulating layer 42 is provided with an opening or the like to expose the external electrode pad 5A for the external terminal electrode. In the present embodiment, the external electrode pad 5A is exposed in the region of the semiconductor chip CP of the sealing body 3 (region corresponding to the circuit surface W1) and outside the region (region corresponding to the surface 3A on the sealing member 30). I am letting. The rewiring 5 is formed on the surface 3A of the sealing body 3 so that the external electrode pads 5A are arranged in an array. In the present embodiment, since the external electrode pad 5A is exposed outside the region of the semiconductor chip CP of the sealing body 3, a fan-out type WLP can be obtained.

[Connection process with external terminal electrode]
FIG. 6B is a cross-sectional view illustrating a process of connecting the external terminal electrode to the external electrode pad 5A of the sealing body 3. The external terminal electrode 6 such as a solder ball is placed on the external electrode pad 5A exposed from the second insulating layer 42, and the external terminal electrode 6 and the external electrode pad 5A are electrically connected by solder bonding or the like. The material of the solder ball is not particularly limited, and examples thereof include lead-containing solder and lead-free solder.

[Second dicing process]
FIG. 6C shows a cross-sectional view for explaining a process of separating the sealing body 3 to which the external terminal electrode 6 is connected (sometimes referred to as a second dicing process). In the second dicing process, the sealing body 3 is separated into individual semiconductor chips CP. The method for dividing the sealing body 3 into individual pieces is not particularly limited. For example, the sealing body 3 can be separated into pieces by adopting a method similar to the method of dicing the semiconductor wafer W described above. The step of dividing the sealing body 3 into pieces may be performed by sticking the sealing body 3 to an adhesive sheet such as a dicing sheet.

  By separating the sealing body 3 into pieces, the semiconductor package 1 in units of the semiconductor chip CP is manufactured. As described above, the semiconductor package 1 in which the external terminal electrode 6 is connected to the external electrode pad 5A fanned out outside the region of the semiconductor chip CP is manufactured as a fan-out type wafer level package (FO-WLP).

[Mounting process]
In the present embodiment, it is also preferable to include a step of mounting the separated semiconductor package 1 on a printed wiring board or the like.

  According to the present embodiment, when the semiconductor wafer W is diced, even if the first adhesive sheet 10 has a cut exceeding the thickness of the semiconductor wafer W, in the process of extending the first adhesive sheet 10 The first pressure-sensitive adhesive sheet 10 can be prevented from tearing due to the incision. The interval between the plurality of semiconductor chips CP transferred to the second pressure-sensitive adhesive sheet 20 can be further increased.

After the dicing process, if the interval between the plurality of semiconductor chips CP is to be greatly expanded by only one expansion process, the pressure-sensitive adhesive sheet may be broken or torn. As a result, the intervals between the plurality of semiconductor chips CP on the pressure-sensitive adhesive sheet vary, or the plurality of semiconductor chips CP are detached from the pressure-sensitive adhesive sheet, so that the handling of the semiconductor chips in the subsequent process is deteriorated.
On the other hand, according to this embodiment, the process of extending an adhesive sheet over two steps is provided. Therefore, it is possible to greatly increase the interval between the plurality of semiconductor chips CP without deteriorating the handleability of the semiconductor chip CP.

  The method according to the present embodiment is excellent in adaptability to the process of manufacturing the FO-WLP type semiconductor package 1. Specifically, according to the present embodiment, the uniformity and accuracy of the chip interval in the FO-WLP type semiconductor package 1 can be improved.

[Second Embodiment]
2nd embodiment is the same as that of 1st embodiment regarding the process until it implements the 2nd expanding process in 1st embodiment. Hereinafter, the point which concerns on difference with 1st embodiment among 2nd embodiment is demonstrated.

  The second embodiment includes a step of picking up the plurality of semiconductor chips CP without performing the sealing step after performing the second expanding step and expanding the interval between the plurality of semiconductor chips CP. As the pickup, a pickup device that has been conventionally used can be used. In the present embodiment, it is preferable that the picked-up semiconductor chip CP further includes a step of mounting on a printed wiring board or the like. The mounted semiconductor chip CP is sealed and packaged with a sealing member or the like, for example.

  According to the present embodiment, the semiconductor chip CP can be picked up after greatly increasing the interval between the plurality of semiconductor chips CP without deteriorating the handleability of the semiconductor chip CP. Therefore, when picking up, it becomes easy to prevent the semiconductor chip CP gripped by the pickup device from coming into contact with another semiconductor chip or the pickup device from coming into contact with another semiconductor chip.

[Third embodiment]
The third embodiment is different from the first embodiment in that it includes a further step after the second expanding step in the first embodiment until the sealing step is performed. Since the third embodiment is the same as the first embodiment in other points, the description is omitted or simplified.

In the present embodiment, after performing the second expanding step, the plurality of semiconductor chips CP (see FIG. 2B) held by the second adhesive sheet 20 and exposed from the back surface W3 are placed on the holding surface of the holding member. A step of transferring the toner (sometimes referred to as a second transfer step).
FIG. 7 shows a plurality of semiconductor chips CP transferred to the holding member 200. The holding member 200 has a holding surface 201 capable of attracting and holding the semiconductor chip CP by a decompression unit (not shown) such as a decompression pump or a vacuum ejector. The plurality of semiconductor chips CP placed on the holding surface 201 have their back surfaces W3 in contact with the holding surface 201. The plurality of semiconductor chips CP are attracted and held on the holding surface 201 by driving the decompression means.

  Next, a step of aligning a plurality of semiconductor chips CP (sometimes referred to as an alignment step) is performed using partition means 101 as shown in FIG. The partition means 101 has a drive mechanism. With this drive mechanism, the partition unit 101 can insert the blade 102 as the contact unit between the plurality of semiconductor chips CP. In the alignment step, the partition means 101 is driven, and the blade 102 is inserted between the semiconductor chips CP. Subsequently, the blade 102 is moved by the driving mechanism and brought into contact with the side surface of the semiconductor chip CP. Further, the blade 102 is moved to move the semiconductor chip CP to a predetermined position on the holding surface 201. When a plurality of semiconductor chips CP are transferred onto the holding surface 201 in a lattice pattern, the blades 102 may be used to move the semiconductor chips CP for each column. Moreover, you may move for every semiconductor chip CP. When moving the semiconductor chip CP, the suction holding may be released. Note that the position of the semiconductor chip CP placed on the holding surface 201 may be detected by a detection means (not shown). The partition unit 101 may include a control unit that controls the amount and direction of movement of the semiconductor chip CP based on the detection result of the detection unit. In the partition unit 101, the detection unit, the control unit, and the drive mechanism may be interlocked.

  The method for aligning the plurality of semiconductor chips CP is not limited to the method described above, and for example, the holding surface 201 may be moved in addition to moving the blade 102. That is, it is only necessary that the semiconductor chip CP can be aligned by relatively moving the blade 102 and the holding surface 201.

  In the present embodiment, after the alignment process is performed, a semiconductor package in units of the semiconductor chip CP can be manufactured by performing a sealing process, a rewiring layer forming process, and the like as in the first embodiment. In this embodiment, in order to obtain the sealing body 3, it is preferable to transfer a plurality of semiconductor chips CP to the adhesive sheet after the alignment step. After the plurality of semiconductor chips CP are transferred, the manufacturing process of the semiconductor package and the semiconductor device can be performed as in the first embodiment.

  According to the present embodiment, after the second expanding step, the plurality of semiconductor chips CP are transferred to the holding member 200 on the holding surface of the holding member, and the blade 102 as the contact means is moved to move the semiconductor chip CP. Can be aligned. Therefore, the interval between the semiconductor chips CP can be more accurately adjusted or further expanded without being affected by the stress of the second adhesive sheet 20 in the second expanding step.

  According to this embodiment, since the plurality of semiconductor chips CP are transferred to the holding surface 201 of the holding member 200 after the second expanding step, the interval between the plurality of semiconductor chips CP transferred to the holding surface 201 is large. . Therefore, when the blade 102 is inserted between the plurality of semiconductor chips CP, the blade 102 contacts the side surface of the semiconductor chip CP, so that the blade 102 contacts the surface of the semiconductor chip CP (circuit surface W1 and circuit W2). Can be prevented.

  In the present embodiment, the distance between the plurality of semiconductor chips is greatly expanded, and the positions of the plurality of semiconductor chips are aligned, so that the method according to the present embodiment is compatible with the manufacturing process of FO-WFL. Excellent.

[Fourth embodiment]
The fourth embodiment is different from the first embodiment in that it includes a further step after the second expanding step in the first embodiment until the sealing step is performed. Moreover, it differs from the third embodiment in that the means for performing the alignment step is different. Since the fourth embodiment is the same as the first embodiment and the third embodiment in other points, the description is omitted or simplified.

FIG. 8 is a diagram illustrating a process of aligning a plurality of semiconductor chips CP using the partition unit 101A according to the present embodiment.
In the present embodiment, the alignment step is performed using the partitioning means 101A instead of the partitioning means 101 described above. The partition unit 101A includes a lattice member 103 as a contact unit. The grid member 103 includes a base plate 103A and a grid portion 103C formed to protrude in a grid pattern on the lower surface 103B of the base plate 103A. The lattice portion 103C is formed so as to be insertable between all of the plurality of semiconductor chips CP. Since the lower end portion of the lattice portion 103C is tapered, the lattice portion 103C can be easily inserted between the semiconductor chips CP. When the partitioning means 101A is used, the lattice member 103 is driven to insert the lattice portion 103C between the plurality of semiconductor chips CP. Thereafter, the semiconductor chip CP is aligned by relatively moving the lattice member 103 and the holding surface 201. By this relative movement, the plurality of semiconductor chips CP are in contact with and aligned with the lattice portion 103C as shown in FIG. Similar to the third embodiment, the partition unit 101A may include a drive mechanism, a detection unit, and a control unit.

  According to this embodiment, the same effects as those of the third embodiment described above can be obtained. Furthermore, according to the present embodiment, since the semiconductor chip CP can be aligned by inserting the lattice portion 103C between all of the plurality of semiconductor chips CP at a time, the processing capacity per unit time can be improved. .

[Modification of Embodiment]
The present invention is not limited to the above-described embodiment. The present invention includes a modification of the above-described embodiment as long as the object of the present invention can be achieved.

  For example, a circuit or the like in a semiconductor wafer or a semiconductor chip is not limited to the illustrated arrangement or shape. The connection structure with the external terminal electrode in the semiconductor package is not limited to the mode described in the above embodiment. In the above-described embodiment, the aspect of manufacturing the FO-WLP type semiconductor package has been described as an example. However, the present invention can also be applied to an aspect of manufacturing other semiconductor packages such as a fan-in type WLP.

  For example, in the above-described embodiment, the embodiment in which the first expanding process and the second expanding process are performed has been described as an example. However, the expanding process may be performed once or more. When carrying out a plurality of expanding steps, the plurality of semiconductor chips CP held by the second adhesive sheet 20 are transferred to another expanding sheet while maintaining the expanded interval, and the expanding sheet is stretched, The interval between the plurality of semiconductor chips CP can be further increased.

In the said embodiment, although demonstrated that it was preferable that the 2nd adhesive sheet 20 had heat resistance, in this invention, a 2nd adhesive sheet is not limited to such a property.
Further, for example, a third pressure-sensitive adhesive sheet having heat resistance may be prepared separately, and a plurality of semiconductor chips CP may be transferred to the third pressure-sensitive adhesive sheet. The above-described sealing step may be performed in a state where the surface (circuit surface W1 and circuit W2) of the semiconductor chip CP is covered with the third adhesive sheet. In this case, it is preferable that the third pressure-sensitive adhesive sheet has heat resistance so as not to cause wrinkles when the sealing member is thermoset. Moreover, it is preferable that the 3rd adhesive sheet is comprised with the material which can peel from semiconductor chip CP after a thermosetting process.

For example, FIG. 10 shows a modification of the alignment process in the fourth embodiment.
As shown in FIG. 10, the holding surface 201 may be inclined to align the semiconductor chips CP. In the fourth embodiment, after the lattice member 103 is inserted between the plurality of semiconductor chips CP held by the holding surface 201 of the holding member 200, at least one of the holding surface 201 and the partition unit 101A is inclined, You may align in the holding surface 201. FIG.
The partitioning means is not limited to the grid member 103 but may be a blade 102.

  The present invention can be used as a method for manufacturing a semiconductor device.

  DESCRIPTION OF SYMBOLS 10 ... 1st adhesive sheet, 11 ... 1st base film, 12 ... 1st adhesive layer, 20 ... 2nd adhesive sheet, 21 ... 2nd base film, 22 ... 2nd adhesive Layer 30, sealing member 102, blade (contact means) 103, lattice member (contact means) 200, holding member 201, holding surface, CP semiconductor chip, W semiconductor wafer

Claims (4)

Separating the wafer affixed to the first pressure-sensitive adhesive sheet by dicing and forming a plurality of semiconductor chips;
Extending the first pressure-sensitive adhesive sheet and widening the interval between the plurality of semiconductor chips; and
Transferring the plurality of semiconductor chips to a second adhesive sheet;
Peeling the first pressure-sensitive adhesive sheet;
Extending the second pressure-sensitive adhesive sheet and further expanding the interval between the plurality of semiconductor chips , and
The first pressure-sensitive adhesive sheet has a first base film and a first pressure-sensitive adhesive layer,
The second pressure-sensitive adhesive sheet has a second base film and a second pressure-sensitive adhesive layer,
And MD direction of the first base film, so that the MD direction of the second base film are orthogonal, transfer a plurality of semiconductor chips in the second adhesive sheet, production of a semiconductor device Method. The second adhesive sheet has a smaller tensile elastic modulus than the first adhesive sheet,
A method for manufacturing a semiconductor device according to claim 1 . After extending the second pressure-sensitive adhesive sheet and expanding the interval between the plurality of semiconductor chips, further comprising a step of covering with a sealing member leaving the circuit surface of the plurality of semiconductor chips,
The method of manufacturing a semiconductor device according to claim 1 or claim 2. Extending the second pressure-sensitive adhesive sheet and expanding the interval between the plurality of semiconductor chips, and then transferring the plurality of semiconductor chips to a holding surface of a holding member;
Inserting contact means between the plurality of semiconductor chips held by the holding surface;
Further comprising the step of relatively moving the contact means and the holding surface to align the semiconductor chips on the holding surface, respectively.
The method of manufacturing a semiconductor device as claimed in any one of claims 3.

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