TWI670395B - 採用無電解鍍敷液之貫通電極的形成方法 - Google Patents

採用無電解鍍敷液之貫通電極的形成方法 Download PDF

Info

Publication number
TWI670395B
TWI670395B TW104103990A TW104103990A TWI670395B TW I670395 B TWI670395 B TW I670395B TW 104103990 A TW104103990 A TW 104103990A TW 104103990 A TW104103990 A TW 104103990A TW I670395 B TWI670395 B TW I670395B
Authority
TW
Taiwan
Prior art keywords
plating solution
electroless
hole
cobalt
copper
Prior art date
Application number
TW104103990A
Other languages
English (en)
Other versions
TW201534760A (zh
Inventor
田中圭一
柏達那 普特拉 普林安加
Original Assignee
日商三菱瓦斯化學股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商三菱瓦斯化學股份有限公司 filed Critical 日商三菱瓦斯化學股份有限公司
Publication of TW201534760A publication Critical patent/TW201534760A/zh
Application granted granted Critical
Publication of TWI670395B publication Critical patent/TWI670395B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846Layer combinations
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/1601Process or apparatus
    • C23C18/1633Process of electroless plating
    • C23C18/1646Characteristics of the product obtained
    • C23C18/165Multilayered product
    • C23C18/1651Two or more layers only obtained by electroless plating
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/18Pretreatment of the material to be coated
    • C23C18/1851Pretreatment of the material to be coated of surfaces of non-metallic or semiconducting in organic material
    • C23C18/1872Pretreatment of the material to be coated of surfaces of non-metallic or semiconducting in organic material by chemical pretreatment
    • C23C18/1875Pretreatment of the material to be coated of surfaces of non-metallic or semiconducting in organic material by chemical pretreatment only one step pretreatment
    • C23C18/1879Use of metal, e.g. activation, sensitisation with noble metals
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/31Coating with metals
    • C23C18/32Coating with nickel, cobalt or mixtures thereof with phosphorus or boron
    • C23C18/34Coating with nickel, cobalt or mixtures thereof with phosphorus or boron using reducing agents
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/31Coating with metals
    • C23C18/38Coating with copper
    • C23C18/40Coating with copper using reducing agents
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/48Coating with alloys
    • C23C18/50Coating with alloys with alloys based on iron, cobalt or nickel
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76867Barrier, adhesion or liner layers characterized by methods of formation other than PVD, CVD or deposition from a liquids
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76871Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76873Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76871Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76874Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroless plating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481Internal lead connections, e.g. via connections, feedthrough structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1068Formation and after-treatment of conductors
    • H01L2221/1073Barrier, adhesion or liner layers
    • H01L2221/1084Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16135Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06513Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06517Bump or bump-like direct electrical connections from device to substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06541Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657Stacked arrangements of devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Materials Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemically Coating (AREA)
  • Ceramic Engineering (AREA)

Abstract

依據本發明可提供一種貫通電極之形成方法,包含對於形成於基板之孔的側壁實施以下步驟:(1)使用至少含有鈷離子或鎳離子、錯化劑、還原劑及pH調整劑之無電解鈷鍍敷液或無電解鎳鍍敷液,自該孔的入口至該孔的中央部形成對於銅之擴散防止層即金屬合金膜;(2)使用至少含有鈷離子或鎳離子、錯化劑、還原劑、pH調整劑及具胺基之聚合物的無電解鈷鍍敷液或無電解鎳鍍敷液,自該孔的中央部至該孔的底部形成擴散防止層即金屬合金膜;及(3)使用無電解銅鍍敷液,在(1)步驟及(2)步驟形成之擴散防止層上疊層銅種層。

Description

採用無電解鍍敷液之貫通電極的形成方法
本發明係關於在矽基板上形成貫通電極的方法,詳細地說,係關於在形成於基板之孔的側壁上藉由無電解鍍敷法形成對於銅之擴散防止層,再於該擴散防止層上疊層銅種層的方法。
Si貫通電極(through-silicon via,TSV)為係電子零件之半導體的一種安裝技術之一,係垂直貫通矽製半導體晶片的內部之電極。 為了應付安裝面積的省空間化、處理速度的改善、消耗電力的降低之課題,有人提出於矽、玻璃、陶瓷等形成貫通電極並疊層半導體晶片的方法,其中以基材使用矽的矽貫通導孔(TSV)為主的研究相當興盛。TSV係於矽基板開設貫通孔後,於貫通孔側壁形成矽氧化膜或聚亞醯胺等絕緣層,並在貫通孔內填充為導電體的銅而形成。 圖1係表示TSV形成步驟的一例。首先,於已形成配線層之晶圓上用DRIE等形成導通孔(圖1a),並於形成絕緣用氧化膜、阻隔金屬層、進而導電用種層成膜後(圖1b),藉由電氣鍍敷於導通孔內部填充銅(圖1c)。將於晶圓表層析出之多餘的銅以CMP去除的同時進行平坦化(圖1d),其後削除晶圓背側面而薄層化,並形成貫通直到背側面的TSV(圖1e)。將其介隔焊料等接合層堆積而成為一個包裝體(圖1f)。
由於為導電體的銅一般係藉由電氣銅鍍敷來填充,為了防止用於開始電氣銅鍍敷所形成的銅種層及銅擴散到矽內,必須於絕緣層與銅種層之間形成鉭(Ta)或鈦(Ti)合金等的擴散防止層。擴散防止層一般係藉由物理蒸鍍(物理氣相沉積,PVD)或化學蒸鍍(化學氣相沉積,CVD)而成膜,然而金屬易於沉積在貫通孔的上部,膜的階梯覆蓋(step coverage)(貫通孔底部的膜厚與孔上部的膜厚的比)低會成為問題,因而據說需要有足夠的階梯覆蓋。 又,作為替換PVD或CVD的方法,有人提出藉由無電解鍍敷法對於貫通孔側壁形成擴散防止層、銅種層的成膜方法(專利文獻1),然而無電解鍍敷法金屬仍然易沉積在貫通孔上部,必須改善階梯覆蓋。
為了使貫通孔側壁的膜厚均勻並改善階梯覆蓋,通常會使用底部上移劑(bottom-up agent)。專利文獻2中使用如雙-(3-磺丙基)二硫醚之硫系有機化合物作為底部上移劑。又,專利文獻3提出在無電解鎳鍍敷液中添加聚乙烯亞胺的方法。
利用無電解鍍敷法所得之擴散防止層,專利文獻4中記載可藉由邊調整硫系底部上移劑的添加量邊進行處理而在貫通孔側壁形成膜厚均勻的層。但是,在擴散防止層形成時使用了硫系底部上移劑後,下一步驟即疊層銅種層時,會抑制銅朝向擴散防止層上的無電解沉積反應,與銅相比為卑金屬之鈷合金或鎳合金會因為銅造成的氧化而溶解且成為擴散防止層與銅種層之疊層不良的原因。因此深切的期望有不使擴散防止層消失且疊層銅種層的方法。 [先前技術文獻] [專利文獻]
[專利文獻1]日本特開2003-203914號公報 [專利文獻2]日本特開2010-185113號公報 [專利文獻3]日本特表2014-513213號公報 [專利文獻4]日本特開2013-251344號公報
[發明所欲解決之課題]
本發明以解決上述習知技術的問題之至少一個作為課題。此外,作為本發明之課題係提供對形成於基板之孔的側壁疊層厚度均勻的擴散防止層及銅種層,而形成具有足夠的階梯覆蓋之貫通電極的方法。 [解決課題之手段]
本案發明人們為了解決上述問題,深入研究了在擴散防止層形成時使用的添加劑種類、無電解鍍敷液的組成、成膜程序後,發現可藉由以下本發明而在孔側壁以良好再現性沉積厚度均勻的金屬合金膜(擴散防止層)。 亦即本發明如以下所述。 <1>一種貫通電極之形成方法,包含對於形成於基板之孔的側壁實施以下步驟:(1)使用至少含有鈷離子或鎳離子、錯化劑、還原劑及pH調整劑之無電解鈷鍍敷液或無電解鎳鍍敷液,自該孔的入口至該孔的中央部形成對於銅之擴散防止層即金屬合金膜; (2)使用至少含有鈷離子或鎳離子、錯化劑、還原劑、pH調整劑及具胺基之聚合物的無電解鈷鍍敷液或無電解鎳鍍敷液,自該孔的中央部至該孔的底部形成擴散防止層即金屬合金膜;及 (3)使用無電解銅鍍敷液,在(1)步驟及(2)步驟形成之擴散防止層上疊層銅種層。 <2>如上述<1>之貫通電極之形成方法,其中,該具胺基之聚合物之含量相對於鍍敷液全量為0.0001質量%~0.02質量%。 <3>如上述<1>或<2>之貫通電極之形成方法,其中,該具胺基之聚合物為烯丙胺聚合物、二烯丙胺聚合物、或含有烯丙胺或二烯丙胺之共聚物。 <4>如上述<1>至<3>中任一項之貫通電極之形成方法,其中,於(1)步驟及(2)步驟使用之鍍敷液含有鎢及/或鉬。 <5>如上述<1>至<4>中任一項之貫通電極之形成方法,其中,該孔之底部之金屬合金膜之膜厚(S)與該孔之入口之金屬合金膜之膜厚(C)之比(階梯覆蓋(S/C)×100%)為30~300%。 [發明之效果]
藉由使用本發明的無電解鍍敷液及配線形成方法,可對形成於基板之孔的側壁疊層厚度均勻的擴散防止層、銅種層。
以下詳細地說明本發明。 本發明所使用的擴散防止層形成用之無電解鍍敷液係含有金屬鹽、錯化劑、還原劑及pH調整劑之水溶液,各別以任意的比例混合而使用。金屬鹽可列舉鈷化合物或鎳化合物,又,為了將金屬膜合金化有時會有含有鎢及/或鉬的情況。錯化劑係將金屬離子予以錯合物化,以使金屬離子不會以氫氧化物的形式沉澱,使其在無電解鍍敷液中的安定性提昇者。還原劑係為了將金屬離子還原者;pH調整劑係調整鍍敷液的pH者。
可使用水溶性鈷鹽當作作為本發明所使用之鈷離子供給源之鈷化合物。宜使用例如:硫酸鈷、氯化鈷、乙酸鈷、硝酸鈷等鈷鹽,並不限定僅為該等之化合物,釋放出鈷離子的化合物均包括。 無電解鍍敷液所含的鈷離子濃度在0.005~0.5mol/L較合適,0.01~0.4mol/L更佳,0.02~0.3mol/L特佳,但不限定於該等濃度,可適當地決定合適的濃度。
可使用水溶性鎳鹽當作作為本發明所使用之鎳離子供給源之鎳化合物。宜使用例如:硫酸鎳、氯化鎳、乙酸鎳、硝酸鎳等鎳鹽,並不限定僅為該等之化合物,釋放出鎳離子的化合物均包括。 無電解鍍敷液所含有的鎳離子濃度在0.005~0.5mol/L較合適,0.01~0.4mol/L更佳,0.02~0.3mol/L特佳,但不限定於該等濃度,可適當地決定合適的濃度。
可使用例如:鎢酸、鎢酸鈉、鎢酸銨作為本發明所使用之鎢酸離子的供給源之鎢化合物較為理想,但不限定僅為該等化合物,所有放出鎢酸離子的化合物皆包含。 無電解鍍敷液所含的鎢酸離子濃度在0.005~0.5mol/L較合適,0.01~0.4mol/L更佳,0.05~0.3mol/L特佳,但不限定於該等濃度,可適當地決定合適的濃度。
宜使用例如:鉬酸、鉬酸鈉、鉬酸銨當作作為本發明所使用之鉬酸離子供給源之鉬化合物,但不限定僅為該等化合物,所有釋放出鉬酸離子的化合物皆包含。 無電解鍍敷液所含的鉬酸離子濃度在0.005~0.5mol/L較合適,0.01~0.4mol/L更佳,0.05~0.3mol/L特佳,但不限定於該等濃度,可適當地決定合適的濃度。
可使用與鈷離子或鎳離子形成錯合物者作為本發明所使用的錯化劑。作為錯化劑並無特別限制,可適當地使用例如:檸檬酸、酒石酸、葡萄糖酸、蘋果酸之類的羥基羧酸等。 無電解鍍敷液所含的錯化劑濃度相對於鈷離子、鎳離子濃度必須為1倍當量以上的濃度,2倍以上較合適。具體而言在0.01~1mol/L較合適,0.05~0.8mol/L更佳,0.1~0.6mol/L特佳。錯化劑的濃度在0.01~1mol/L時,可安定地實施鍍敷操作。
可使用例如:次亞磷酸、烷基硼烷類等作為本發明所使用的還原劑。烷基硼烷類可列舉例如:單烷基胺硼烷、二烷基胺硼烷、三烷基胺硼烷等。 無電解鍍敷液所含的還原劑濃度在0.001~0.6mol/L較合適,0.005~0.5mol/L更佳,0.01~0.4mol/L特佳。還原劑的濃度在0.001~0.6mol/L時,可安定地實施鍍敷膜的形成。
可使用鹼性的化合物作為本發明所使用的pH調整劑。可使用例如:氫氧化鉀、氫氧化鈉、氫氧化四甲基銨(TMAH)等。 作為無電解鍍敷液的pH值在7~13較合適,7.5~12更佳,8~11特佳。pH值在7~13時,可安定地實施鍍敷膜的形成。
此外本發明所使用的無電解鍍敷液中可添加烷基硫酸鹽、烷基磷酸鹽、烷基磺酸鹽等界面活性劑;聚乙二醇等水溶性高分子。 該等添加劑發揮作為提昇鍍敷被膜的平滑性之平整劑(leveler)的作用。無電解鍍敷液所含的界面活性劑或水溶性高分子的濃度在1ppm~5000ppm較合適。
作為在本發明使用的無電解鈷鍍敷液或無電解鎳鍍敷液所添加的具胺基之聚合物可列舉:烯丙胺聚合物、二烯丙胺聚合物、或含有烯丙胺或二烯丙胺之共聚物較為理想。該等聚合物可將一種單獨使用,亦可將兩種以上混合使用。該等聚合物可使用已知的市售品,可列舉例如:日東紡醫療股份有限公司(NITTOBO MEDICAL CO., LTD.)製的聚烯丙胺(PAA系列)、多元胺(PAS系列)等較為理想。 具胺基之聚合物的平均分子量並無特別限制但在300~200000較合適,500~100000更佳。 無電解鍍敷液中的具胺基之聚合物的濃度在0.0001~0.02質量%較合適,0.0002~0.01質量%更佳,0.0003~0.005質量%特佳。具胺基之聚合物的濃度未達0.0001質量%時會無法得到抑制膜沉積在孔上部的效果,不能成膜為均勻的膜。又,具胺基之聚合物的濃度超過0.02質量%時,除了產生降低底部上移效果的缺點之外,亦會產生聚合物在鍍敷液中之溶解性不良的問題。
本發明所使用的銅種層形成用無電解銅鍍敷液為含銅鹽、錯化劑、還原劑及pH調整劑之水溶液,並以各別任意之比例混合使用。銅鹽為銅化合物,係供應銅離子者。錯化劑係將銅離子予以錯合物化,以使銅離子不會以氫氧化物的形式沉澱,使其在無電解銅鍍敷液中的安定性提昇者。還原劑係為了將銅離子還原者;pH調整劑係調整鍍敷液的pH者。
作為本發明所使用的銅離子供應源之銅化合物可使用水溶性的銅鹽。宜使用例如:硫酸銅、氯化銅、乙酸銅、硝酸銅等銅鹽,並不限定僅為該等之化合物,包含釋放出銅離子之化合物的全部。 作為無電解鍍敷液所含之銅離子濃度0.001~0.5mol/L較合適,0.005~0.4 mol/L更佳,0.01~0.3mol/L特佳,但不限定於該等濃度,可適當地決定合適的濃度。
作為本發明所使用的錯化劑可使用和銅離子形成錯合物者。作為錯化劑並無特別限制,但可適當地使用例如:乙二胺四乙酸、乙二胺四乙酸鈉鹽之類的乙二胺四乙酸化合物或檸檬酸、酒石酸之類的羥基羧酸等。 無電解鍍敷液所含的錯化劑的濃度,相對於銅離子濃度必須為1倍當量以上的濃度,1.5倍以上較合適。具體而言,0.0015~1mol/L較合適,0.0075~0.8mol/L更佳,0.015~0.6mol/L特佳。錯化劑的濃度在0.0015~1mol/L時,可安定地實施鍍敷操作。
作為本發明所使用的還原劑,可使用例如:甲醛、乙醛酸、次亞磷酸、烷基硼烷類等。烷基硼烷類可列舉例如:單烷基胺硼烷、二烷基胺硼烷、三烷基胺硼烷等。 無電解鍍敷液所含的還原劑的濃度為0.001~0.8mol/L較合適,0.005~0.7 mol/L更佳,0.01~0.6mol/L特佳。還原劑的濃度在0.001~0.8mol/L時,可安定地實施鍍敷膜的形成。
作為本發明所使用的pH調整劑可使用鹼性的化合物。可使用例如:氫氧化鉀、氫氧化鈉、氫氧化四甲基銨(TMAH)等。 作為無電解鍍敷液的pH值較合適為9~14,10~13.5更佳,10.5~13特佳。pH值在9~14時,可安定地實施鍍敷膜的形成。
此外本發明所使用的無電解銅鍍敷液中可添加烷基硫酸鹽、烷基磷酸鹽、烷基磺酸鹽等界面活性劑;聚乙二醇等水溶性高分子;2,2‘-聯吡啶、啡啉等。 該等添加劑發揮作為使鍍敷被膜的平滑性提昇之平整劑的作用。無電解銅鍍敷液所含的界面活性劑或水溶性高分子的濃度為1ppm~5000ppm較合適。
本發明的鍍敷處理方法只要是鍍敷液接觸被鍍敷位置的方法即無特別限制,一次處理多片的批式、一次處理一片的單片式中任一者皆無妨。 作為無電解鍍敷處理溫度宜為40℃~90℃,45℃~80℃更佳,50℃~70℃特佳。
依據本發明的方法,孔的底部之金屬合金膜(擴散防止層)的膜厚與孔的入口之金屬合金膜(擴散防止層)的膜厚之比即階梯覆蓋((S/C)×100%)宜為30%~300%,40%~250%更佳,50%~200%特佳。 作為測量金屬合金膜之膜厚的方法,可將金屬合金膜形成後的評估基材在相對於孔為垂直方向上切斷,使用掃描型電子顯微鏡(SEM) 觀察合金膜剖面,並測量長度以求得膜厚。 [實施例]
以下藉由本發明的實施例與比較例,對其實施形態與效果進行具體地說明,但本發明並不限定於該等的實施例。
實施例1~11 [評估基板] 做為評估用的基材,在使用乾蝕刻技術於矽晶圓所形成的直徑10μm、深100μm的孔(L/D=10)的側壁,形成矽氧化膜作為絕緣層。然後,在矽氧化膜上藉由偶合劑形成吸附層後,使其浸漬於鈀(Pd)膠體溶液中,以形成附著了反應開始觸媒即Pd的晶圓。 [無電解鈷鍍敷液] 製備含有2質量%(0.13mol/L)的硫酸鈷、6質量%(0.32mol/L)之作為錯化劑的檸檬酸、5質量%(0.2mol/L)的鎢酸、0.4質量%(0.07mol/L)之作為還原劑的二甲基胺硼烷,並以氫氧化四甲基銨作為pH調整劑將pH值調整為9.5之水溶液。 [無電解銅鍍敷液] 製備含有0.5質量%(0.03mol/L)的硫酸銅、4質量%(0.14mol/L)的乙二胺四乙酸、1質量%(0.14mol/L)的乙醛酸、0.005質量%(50ppm)的2,2’聯吡啶、0.05質量%(500ppm)的聚乙二醇,並以氫氧化四甲基銨將pH值調整為12.5之水溶液。
[擴散防止層(鈷合金膜)形成處理] 圖2係表示擴散防止層及銅種層疊層時的剖面示意圖。將具有孔的評估基材1於60℃在無電解鈷鍍敷液(圖2A的2)中浸漬10分鐘(第1段處理),自孔側壁的入口至中央部形成鈷合金膜(擴散防止層)3。 然後,於無電解鈷鍍敷液2中添加添加劑4(下述表1所記載的具胺基之聚合物),將已完成第1段處理的上述基材於60℃浸漬30分鐘(第2段處理,圖2B),自孔的側壁的中央部至底部形成鈷合金膜(擴散防止層)3。另外,本實施例所用的具胺基之聚合物皆為日東紡醫療股份有限公司(NITTOBO MEDICAL CO., LTD.)製的市售品。 [銅種層疊層處理] 將已完成第2段處理的上述基材於45℃在無電解銅鍍敷液5中浸漬15分鐘,在鈷合金膜3上形成銅種層6(圖2C的6)。 [鈷合金膜的膜厚測量] 將鈷合金膜形成後的評估基材在相對於孔成垂直方向上切斷,並使用掃描型電子顯微鏡(SEM)觀察鈷合金膜剖面,並測量長度以求得膜厚。又,孔的底部之金屬合金膜(擴散防止層)的膜厚與孔的入口之金屬合金膜(擴散防止層)的膜厚之比即階梯覆蓋((S/C)×100%)依下述(1)式求得。 階梯覆蓋30%~300%判定為合格。
【數式1】 階梯覆蓋(%)={孔的底部的膜厚(nm)}/{孔的入口的膜厚(nm)}×100 ・・・(1) [銅種層成膜確認] 將擴散防止層(鈷合金膜)上已疊層銅種層後的晶圓在相對於孔成垂直方向上切斷,並使用掃描型電子顯微鏡觀察銅的成膜狀態及鈷合金膜的殘存狀態。
表1顯示已添加表1中作為第2段處理時之無電解鈷鍍敷液添加劑的各種具胺基之聚合物時的鈷合金膜厚及階梯覆蓋、銅種層沉積的有無、銅種層成膜時鈷合金膜消失的有無。
【表1】
於實施例1~11形成了階梯覆蓋30%以上、300%以下之均勻的鈷合金膜。又,鈷合金膜並未消失而形成銅種層。
實施例12、13 使用下述的無電解鎳鍍敷液替換無電解鈷鍍敷液,除此之外與實施例1同樣地實施。 [無電解鎳鍍敷液] 製備含有2質量%(0.13mol/L)的硫酸鎳、4質量%(0.21mol/L)之作為錯化劑的檸檬酸、0.3質量%(0.05mol/L)之作為還原劑的二甲基胺硼烷,並以作為pH調整劑之氫氧化四甲基銨將pH值調整為8.5之水溶液。 [鎳合金膜的膜厚測量] 將鎳合金膜形成後的評估基材相對於孔在垂直方向上切斷,並使用掃描型電子顯微鏡(SEM)觀察鎳合金膜剖面,並測量長度以求得膜厚。 又,孔的底部之金屬合金膜(擴散防止層)的膜厚與孔的入口之金屬合金膜(擴散防止層)的膜厚之比即階梯覆蓋((S/C)×100%)依上述(1)式求得。 階梯覆蓋30%~300%判定為合格。 [銅種層成膜確認] 將擴散防止層(鎳合金膜)上已疊層銅種層後的晶圓相對於孔在垂直方向上切斷,並使用掃描型電子顯微鏡觀察銅的成膜狀態及鎳合金膜的殘存狀態。
實施例12、13的無電解鍍敷處理結果如表2所示。表示鎳合金膜厚及階梯覆蓋、銅種層沉積的有無、銅種層成膜時鎳合金膜消失的有無。
於實施例12及13可成膜為階梯覆蓋30%以上之均勻的鎳合金膜。又,鎳合金膜並未消失,可成膜為銅種層。
比較例1 使用無電解鈷鍍敷液之第2段處理時不添加添加劑(具胺基之聚合物),除此之外與實施例1同樣地實施。於表3表示無電解鍍敷處理結果。
於比較例1之成膜的結果,無法抑制孔的入口之膜厚成長,成膜為階梯覆蓋未達30%之不均勻的鈷合金膜。
比較例2~7 於使用無電解鈷鍍敷液之第2段處理時的添加劑中添加具胺基之聚合物以外的胺化合物,除此之外與實施例1同樣地實施。表4表示於無電解鈷鍍敷液添加劑中添加各種胺化合物時的鈷合金膜厚及階梯覆蓋、銅種層沉積的有無、銅種層成膜時鈷合金膜消失的有無。
【表4】
於比較例2~7之成膜的結果,無法抑制孔的入口之膜厚成長,成膜為階梯覆蓋未達30%之不均勻的鈷合金膜,為不合格。
比較例8~10 於使用無電解鈷鍍敷液之第2段處理時的添加劑中添加硫系化合物,除此之外與實施例1同樣地實施。表5表示以硫系化合物作為無電解鈷鍍敷液添加劑而添加時的鈷合金膜厚及階梯覆蓋、銅種層沉積的有無、銅種層成膜時鈷合金膜消失的有無。
【表5】
於比較例8~10實施無電解銅鍍敷處理的結果,銅鍍敷膜有沉積,但確認了鈷合金膜的消失。
比較例11 於實施例1之擴散防止層的形成中,僅實施無電解鈷鍍敷處理的第1段處理。使用的評估用基材、鈷鍍敷液與實施例1所使用的相同。成膜後的膜厚測量結果如表6所示。
於比較例11之孔的側壁底部的膜無沉積,成膜為階梯覆蓋未達30%之不均勻的鈷合金膜。
比較例12、13 於實施例1之擴散防止層的形成中,僅實施無電解鈷鍍敷處理的第2段處理。使用的評估用基材、鈷鍍敷液與實施例1所使用的相同,並添加表7記載的具胺基之聚合物。成膜後的膜厚測量結果如表7所示。
於比較例12及13確認貫通孔入口的膜無沉積,孔的側壁入口的膜無法形成。
A‧‧‧擴散防止層形成步驟(第1段)
B‧‧‧擴散防止層形成步驟(第2段)
C‧‧‧銅種層疊層步驟
1‧‧‧評估基板
2‧‧‧無電解鈷鍍敷液或無電解鎳鍍敷液
3‧‧‧擴散防止層
4‧‧‧無電解鍍敷液添加劑
5‧‧‧無電解銅鍍敷液
6‧‧‧銅種層
[圖1]係表示習知技術的TSV形成步驟的一例之概略圖。 [圖2]的圖2A係表示利用無電解鍍敷液在形成於基材的貫通孔中之難形成側壁的孔的入口至中央部形成擴散防止層的狀態的概略圖。圖2B係表示藉由添加了具胺基之聚合物的無電解鍍敷液,自孔的中央部至底部形成擴散防止層的狀態之概略圖。圖2C係表示藉由無電解銅鍍敷液於擴散防止層上形成銅種層的狀態之概略圖。

Claims (3)

  1. 一種貫通電極之形成方法,包含對於形成於基板之孔的側壁實施以下步驟:(1)使用至少含有鈷離子或鎳離子、錯化劑、還原劑及pH調整劑之無電解鈷鍍敷液或無電解鎳鍍敷液,自該孔的入口至該孔的中央部形成對於銅之擴散防止層即金屬合金膜;(2)使用至少含有鈷離子或鎳離子、錯化劑、還原劑、pH調整劑及具胺基之聚合物的無電解鈷鍍敷液或無電解鎳鍍敷液,自該孔的中央部至該孔的底部形成擴散防止層即金屬合金膜;及(3)使用無電解銅鍍敷液,在(1)步驟及(2)步驟形成之擴散防止層上疊層銅種層;該具胺基之聚合物為烯丙胺聚合物、二烯丙胺聚合物、或含有烯丙胺或二烯丙胺之共聚物;該無電解鍍敷液中含有的錯化劑的濃度為0.01~1mol/L,該無電解鍍敷液中含有的還原劑的濃度為0.001~0.6mol/L,該具胺基之聚合物之含量相對於鍍敷液全量為0.0001質量%~0.02質量%。
  2. 如申請專利範圍第1項之貫通電極之形成方法,其中,於(1)步驟及(2)步驟使用之無電解鈷鍍敷液或無電解鎳鍍敷液含有鎢及/或鉬。
  3. 如申請專利範圍第1或2項之貫通電極之形成方法,其中,該孔之底部之金屬合金膜之膜厚(S)與該孔之入口之金屬合金膜之膜厚(C)之比(階梯覆蓋(S/C)×100%)為30~300%。
TW104103990A 2014-02-21 2015-02-06 採用無電解鍍敷液之貫通電極的形成方法 TWI670395B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2014-031241 2014-02-21
JP2014031241 2014-02-21

Publications (2)

Publication Number Publication Date
TW201534760A TW201534760A (zh) 2015-09-16
TWI670395B true TWI670395B (zh) 2019-09-01

Family

ID=53882925

Family Applications (1)

Application Number Title Priority Date Filing Date
TW104103990A TWI670395B (zh) 2014-02-21 2015-02-06 採用無電解鍍敷液之貫通電極的形成方法

Country Status (5)

Country Link
US (1) US9401307B2 (zh)
JP (1) JP6394429B2 (zh)
KR (1) KR102264033B1 (zh)
CN (1) CN104862675B (zh)
TW (1) TWI670395B (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11133218B1 (en) * 2020-01-23 2021-09-28 Tae Young Lee Semiconductor apparatus having through silicon via structure and manufacturing method thereof
CN111816608B (zh) * 2020-07-09 2023-05-09 电子科技大学 玻璃盲孔加工方法
KR102423936B1 (ko) 2020-11-20 2022-07-22 한국생산기술연구원 전해 구리 도금액 및 이를 이용한 실리콘 관통전극의 충전방법

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070166991A1 (en) * 2003-09-23 2007-07-19 Nishant Sinha Methods for forming conductive vias in semiconductor device components
CN103502509A (zh) * 2011-05-05 2014-01-08 埃其玛公司 将基于镍或钴的金属层沉积在半导体固体衬底上的方法以及用来应用该方法的试剂盒

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002093747A (ja) * 2000-09-19 2002-03-29 Sony Corp 導体構造の形成方法及び導体構造、並びに半導体装置の製造方法及び半導体装置
JP3567377B2 (ja) 2002-01-09 2004-09-22 独立行政法人 科学技術振興機構 半導体集積回路装置の製造方法
KR100767942B1 (ko) * 2003-10-17 2007-10-17 닛코킨조쿠 가부시키가이샤 무전해 구리도금액
JP5525762B2 (ja) * 2008-07-01 2014-06-18 上村工業株式会社 無電解めっき液及びそれを用いた無電解めっき方法、並びに配線基板の製造方法
JP5486821B2 (ja) 2009-02-12 2014-05-07 学校法人 関西大学 無電解銅めっき方法、及び埋め込み配線の形成方法
CN102534582A (zh) * 2010-12-25 2012-07-04 管静 无电镀铜溶液
JP2012175073A (ja) * 2011-02-24 2012-09-10 Tokyo Electron Ltd 成膜方法および記憶媒体
JP5917297B2 (ja) 2012-05-30 2016-05-11 東京エレクトロン株式会社 めっき処理方法、めっき処理装置および記憶媒体

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070166991A1 (en) * 2003-09-23 2007-07-19 Nishant Sinha Methods for forming conductive vias in semiconductor device components
CN103502509A (zh) * 2011-05-05 2014-01-08 埃其玛公司 将基于镍或钴的金属层沉积在半导体固体衬底上的方法以及用来应用该方法的试剂盒

Also Published As

Publication number Publication date
CN104862675B (zh) 2018-07-31
US9401307B2 (en) 2016-07-26
TW201534760A (zh) 2015-09-16
JP6394429B2 (ja) 2018-09-26
JP2015172239A (ja) 2015-10-01
CN104862675A (zh) 2015-08-26
KR20150099392A (ko) 2015-08-31
US20150243553A1 (en) 2015-08-27
KR102264033B1 (ko) 2021-06-11

Similar Documents

Publication Publication Date Title
US7815786B2 (en) Copper electrodeposition in microelectronics
JP6367322B2 (ja) 湿式ウエハバックコンタクトを使用したシリコンビアを通した銅メッキのための方法
US6398855B1 (en) Method for depositing copper or a copper alloy
WO2015172089A1 (en) Super conformal plating
TW200907104A (en) Self-initiated alkaline metal ion free electroless deposition composition for thin co-based and ni-based alloys
EP2963158A1 (en) Plating method
TWI670395B (zh) 採用無電解鍍敷液之貫通電極的形成方法
TW201821648A (zh) 在微電子件中的銅的電沉積
TWI737880B (zh) 用於高縱橫比模式之銅電沉積溶液及方法
KR101092667B1 (ko) 니켈-인-텅스텐 삼원합금 무전해 도금액, 이를 이용한 무전해 도금 공정 및 이에 의해 제조된 니켈-인-텅스텐 삼원합금피막
JP2017503929A (ja) 銅の電析
EP1215305B1 (en) Method for preparing an electroplating bath and related copper plating process
JP4202016B2 (ja) 電気めっき浴を準備する方法および関連した銅めっきプロセス
US20150322587A1 (en) Super conformal plating
TWI633627B (zh) 用於銅金屬化之方法及用於形成鈷或鎳矽化物之方法
KR101096812B1 (ko) 무전해 니켈-코발트-붕소 삼원합금 도금액, 이를 이용한 무전해 도금공정, 이에 의해 제조된 니켈-코발트-붕소 삼원합금 피막
TWI638424B (zh) 利用濕式晶圓背側接觸進行銅電鍍矽穿孔的方法
EP1022355B1 (en) Deposition of copper on an activated surface of a substrate
KR101224205B1 (ko) 반도체 배선용 무전해 은 도금액, 이를 이용한 무전해 도금 공정 및 이에 의해 제조된 은 피막
KR20110087715A (ko) 무전해 코발트-텅스텐-인 삼원합금 도금액, 이를 이용한 무전해 도금공정 및 이에 의해 제조된 코발트-텅스텐-인 삼원합금 피막
TW201619445A (zh) 銅之電沉積