CN104862675A - 使用化学镀液的贯通电极的形成方法 - Google Patents

使用化学镀液的贯通电极的形成方法 Download PDF

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CN104862675A
CN104862675A CN201510083537.3A CN201510083537A CN104862675A CN 104862675 A CN104862675 A CN 104862675A CN 201510083537 A CN201510083537 A CN 201510083537A CN 104862675 A CN104862675 A CN 104862675A
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cobalt
hole
alloy film
plating
ion
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CN104862675B (zh
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田中圭一
普林安加·柏达那·普特拉
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Mitsubishi Gas Chemical Co Inc
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Mitsubishi Gas Chemical Co Inc
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    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
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Abstract

本发明提供使用化学镀液的贯通电极的形成方法，上述贯通电极的形成方法具有如下工序：对于形成于基板的孔的侧壁，(1)使用至少含有钴离子或镍离子、络合剂、还原剂以及pH调节剂的化学镀钴液或化学镀镍液，在前述孔的入口至前述孔的中央部形成作为防止铜扩散的层的金属合金膜的工序；(2)使用至少含有钴离子或镍离子、络合剂、还原剂、pH调节剂以及具有氨基的聚合物的化学镀钴液或化学镀镍液，在前述孔的中央部至前述孔的底形成作为防扩散层的金属合金膜的工序；以及(3)使用化学镀铜液，在(1)工序以及(2)工序形成的防扩散层上层叠铜晶种层的工序。

Description

使用化学镀液的贯通电极的形成方法
技术领域
本发明涉及在硅基板上形成贯通电极的方法，详细而言，涉及在形成于基板的孔的侧壁利用化学镀法形成防止铜扩散的层、进而在该防扩散层上层叠铜晶种层的方法。
背景技术
Si贯通电极(through-silicon via、TSV)是指作为电子部件的半导体的安装技术之一，垂直地贯通硅制半导体芯片的内部的电极。
为了对应安装面积的省空间化、处理速度的改善、消耗电量的降低的课题，提出了在硅、玻璃、陶瓷等中形成贯通电极，层叠半导体芯片的方法，其中，盛行以在基材中使用硅的硅贯通导通孔(TSV)为中心的研究。TSV通过如下而形成：在硅基板中开贯通孔之后，在贯通孔侧壁形成硅氧化膜、聚酰亚胺等绝缘层，并在贯通孔内填充作为导电体的铜。
图1中示出TSV形成工序的一个例子。首先，在形成有布线层的晶圆中由DRIE等形成导通孔(图1的a)、形成绝缘用氧化膜、势垒金属层、进而对导通用晶种进行成膜之后(图1的b)，通过电镀在导通孔内部填充铜(图1的c)。用CMP去除在晶圆表层析出的多余的铜并且平坦化(图1的d)，然后切削晶圆背面进行薄层化，形成贯通至背面的TSV(图1的e)。将其介由焊料等的接合层沉积从而制成一个封装体(图1的f)。
作为导电体的铜通常通过电镀铜而填充，因此为了用于开始电镀铜的铜晶种层的形成以及防止铜在硅内扩散，需要在绝缘层与铜晶种层之间形成钽(Ta)、钛(Ti)合金等的防扩散层。防扩散层通常通过物理沉积(PVD)、化学沉积(CVD)而成膜，但存在在贯通孔的上部金属容易沉积，膜的阶梯覆盖率(贯通孔底部的膜厚与孔上部的膜厚的比)低的问题，足够的阶梯覆盖率是必要的。
此外，作为代替PVD、CVD的方法，提出了基于化学镀法的对于贯通孔侧壁的防扩散层、铜晶种层的成膜方法(专利文献1)，但即便在化学镀法中，在贯通孔上部金属容易沉积的情况也未发生变化，阶梯覆盖率的改善是必要的。
为了使贯通孔侧壁的膜厚均匀、改善阶梯覆盖率，通常使用自下而上剂(bottom-up agent)。专利文献2中作为自下而上剂，使用双-(3-磺基丙基)二硫醚那样的硫系有机化合物。此外，专利文献3提出了在化学镀镍液中添加聚亚乙基亚胺的方法。
对于基于化学镀法的防扩散层，在专利文献4中边调整硫系自下而上剂的添加量边进行处理，从而可以在贯通孔侧壁形成均匀膜厚的层。但是，在防扩散层形成时使用硫系自下而上剂之后，作为下一工序层叠铜晶种层时，向防扩散层上的铜的化学沉积反应受到抑制，抑制与铜相比更容易氧化的金属钴合金或镍合金由于铜的氧化而溶解、成为防扩散层与铜晶种层的层叠不良的原因。因此，渴望不使防扩散层消失、并且用于层叠铜晶种层的方法。
现有技术文献
专利文献
专利文献1：日本特开2003-203914号公报
专利文献2：日本特开2010-185113号公报
专利文献3：日本特表2014-513213号公报
专利文献4：日本特开2013-251344号公报
发明内容
发明要解决的问题
本发明的课题在于，解决上述现有技术中的问题的至少一个。进而，本发明的课题在于提供对形成于基板的孔的侧壁层叠均匀厚度的防扩散层以及铜晶种层，形成具有足够的阶梯覆盖率的贯通电极的方法。
用于解决问题的方案
本发明人等为了解决上述课题，深入研究防扩散层形成时使用的添加剂的种类、化学镀液的组成、成膜顺序，结果，发现根据以下的本发明可以在孔侧壁再现性良好地沉积均匀厚度的金属合金膜(防扩散层)。
即本发明如以下所述。
<1>一种贯通电极的形成方法，其中，所述贯通电极的形成方法具有如下工序：对于形成于基板的孔的侧壁，
(1)使用至少含有钴离子或镍离子、络合剂、还原剂以及pH调节剂的化学镀钴液或化学镀镍液，从所述孔的入口至所述孔的中央部形成作为防止铜扩散的层的金属合金膜的工序；
(2)使用至少含有钴离子或镍离子、络合剂、还原剂、pH调节剂以及具有氨基的聚合物的化学镀钴液或化学镀镍液，在所述孔的中央部至所述孔的底形成作为防扩散层的金属合金膜的工序；以及
(3)使用化学镀铜液，在(1)工序以及(2)工序形成的防扩散层上层叠铜晶种层的工序。
<2>根据<1>所述的贯通电极的形成方法，其中，所述具有氨基的聚合物的含量相对于镀液总量为0.0001质量％～0.02质量％。
<3>根据<1>或<2>所述的贯通电极的形成方法，其中，所述具有氨基的聚合物为烯丙基胺聚合物、二烯丙基胺聚合物、或包含烯丙基胺或者二烯丙基胺的共聚物。
<4>根据<1>～<3>中任一项所述的贯通电极的形成方法，其中，(1)工序以及(2)工序中使用的镀液含有钨和/或钼。
<5>根据<1>～<4>中任一项所述的贯通电极的形成方法，其中，所述孔的底的金属合金膜的膜厚S与所述孔的入口的金属合金膜的膜厚C的比、即阶梯覆盖率S/C×100％为30～300％。
发明的效果
通过使用本发明中的化学镀液以及布线形成方法，从而可以对形成于基板的孔的侧壁层叠均匀厚度的防扩散层、铜晶种层。
附图说明
图1为表示现有技术中的TSV形成工序的一个例子的示意图。
图2的A为表示利用化学镀液在形成于基材的贯通孔中自侧壁形成困难的孔的入口至中央部形成防扩散层的情况的示意图。图2的B为表示利用添加有具有氨基的聚合物的化学镀液自孔的中央部至底形成防扩散层的情况的示意图。图2的C为表示在防扩散层上利用化学镀铜液形成铜晶种层的情况的示意图。
具体实施方式
以下，详细地说明本发明。
本发明中所使用的防扩散层形成用的化学镀液为包含金属盐、络合剂、还原剂以及pH调节剂的水溶液，分别以任意的比例混合来使用。金属盐可以列举出钴化合物或镍化合物、此外为了将金属膜合金化也存在含有钨和/或钼的情况。络合剂是将金属离子络合物化使得金属离子不作为氢氧化物沉淀，从而提高金属离子在化学镀液中的稳定性的物质。还原剂用于还原金属离子，pH调节剂用于调整镀液的pH。
作为本发明中使用的钴离子的供给源的钴化合物，可以使用水溶性的钴盐。例如，优选使用硫酸钴、氯化钴、醋酸钴、硝酸钴等钴盐，并不限定于它们，包括所有的放出钴离子的化合物。
作为化学镀液中含有的钴离子浓度，0.005～0.5mol/L是适宜的，更优选为0.01～0.4mol/L、特别优选为0.02～0.3mol/L，并不限定于这些浓度，可以决定适宜的浓度。
作为本发明中使用的镍离子的供给源的镍化合物，可以使用水溶性的镍盐。例如，优选使用硫酸镍、氯化镍、醋酸镍、硝酸镍等镍盐，并不限定于它们，包括所有的放出镍离子的化合物。
作为化学镀液中含有的镍离子浓度，0.005～0.5mol/L是适宜的、更优选为0.01～0.4mol/L，特别优选为0.02～0.3mol/L，并不限定于这些浓度，可以决定适宜的浓度。
作为本发明中优选使用的钨酸离子的供给源的钨化合物，例如，使用钨酸、钨酸钠、钨酸铵，并不限定于它们，包括所有的放出钨酸离子的化合物。
作为化学镀液中含有的钨酸离子浓度，0.005～0.5mol/L是适宜的，更优选为0.01～0.4mol/L、特别优选为0.05～0.3mol/L，并不限定于这些浓度，可以决定适宜的浓度。
作为本发明中优选使用的钼酸离子的供给源的钼化合物，例如，使用钼酸、钼酸钠、钼酸铵，并不限定于它们，包括所有的放出钼酸离子的化合物。
作为化学镀液中含有的钼酸离子浓度，0.005～0.5mol/L是适宜的，更优选为0.01～0.4mol/L、特别优选为0.05～0.3mol/L，并不限定于这些浓度，可以决定适宜的浓度。
作为本发明中所使用的络合剂，使用与钴离子或镍离子形成络合物的物质。作为络合剂没有特别限定，例如，可以适宜地使用柠檬酸、酒石酸、葡糖酸、苹果酸那样的羟基羧酸等。
化学镀液中含有的络合剂的浓度需要相对于钴离子、镍离子浓度为1倍等量以上的浓度，适宜为2倍以上。具体而言，适宜为0.01～1mol/L、更优选为0.05～0.8mol/L、特别优选为0.1～0.6mol/L。络合剂的浓度为0.01～1mol/L时，可以稳定地进行镀覆操作。
作为本发明中所使用的还原剂，例如，可以使用次磷酸、烷基硼烷类等。烷基硼烷类例如可以列举出单烷基胺基硼烷、二烷基胺基硼烷、三烷基胺基硼烷等。
化学镀液中含有的还原剂的浓度适宜为0.001～0.6mol/L、更优选为0.005～0.5mol/L、特别优选为0.01～0.4mol/L。还原剂的浓度为0.001～0.6mol/L时，可以稳定地进行镀覆膜的形成。
作为本发明中所使用的pH调节剂，可以使用碱性的化合物。例如，可以使用氢氧化钾、氢氧化钠、氢氧化四甲基铵(TMAH)等。
作为化学镀液的pH值适宜为7～13、更优选为7.5～12、特别优选为8～11。pH值为7～13时，可以稳定地进行镀覆膜的形成。
进而，本发明中所使用的化学镀液中，可以添加烷基硫酸盐、烷基磷酸盐、烷基磺酸盐等表面活性剂，聚乙二醇等水溶性高分子。
这些添加剂发挥作为提高镀覆被膜的平滑性的整平剂的效果。化学镀液中含有的表面活性剂、水溶性高分子的浓度适宜为1ppm～5000ppm。
作为在本发明中所使用的化学镀钴液或化学镀镍液中所添加的、具有氨基的聚合物，优选可以列举出烯丙基胺聚合物、二烯丙基胺聚合物、或包含烯丙基胺或者二烯丙基胺的共聚物。这些聚合物可以单独使用1种、也可以混合使用2种以上。这些聚合物可以使用公知市售品，例如，优选可以列举出Nittobo Medical Co.,Ltd.制造的聚烯丙基胺(PAA系列)、多胺(PAS系列)等。
具有氨基的聚合物的平均分子量没有特别限制，适宜为300～200000、更优选为500～100000。
化学镀液中的具有氨基的聚合物的浓度适宜为0.0001～0.02质量％、更优选为0.0002～0.01质量％、特别优选为0.0003～0.005质量％。具有氨基的聚合物的浓度不足0.0001质量％时，不能得到在孔上部的膜生长抑制效果，不能成膜均匀膜。此外，具有氨基的聚合物的浓度超过0.02质量％时，也产生自下而上效果降低的不良、并且聚合物在镀液中的溶解性恶化的问题。
本发明中所使用的铜晶种层形成用的化学镀铜液为包含铜盐、络合剂、还原剂以及pH调节剂的水溶液，分别以任意的比例混合来使用。铜盐为铜化合物，供给铜离子。络合剂是将铜离子络合物化使得铜离子不作为氢氧化物沉淀，从而提高铜离子在化学镀铜液中的稳定性的物质。还原剂用于还原铜离子，pH调节剂用于调整镀液的pH。
作为本发明中所使用的铜离子的供给源的铜化合物，可以使用水溶性的铜盐。例如，优选使用硫酸铜、氯化铜、醋酸铜、硝酸铜等铜盐，并不限定于它们，包括所有的放出铜离子的化合物。
作为化学镀液中含有的铜离子浓度，0.001～0.5mol/L是适宜的、更优选为0.005～0.4mol/L、特别优选为0.01～0.3mol/L，并不限定于这些浓度，可以决定适宜的浓度。
作为本发明中所使用的络合剂，使用与铜离子形成络合物的物质。作为络合剂没有特别限定，例如，可以适宜地使用乙二胺四醋酸、乙二胺四醋酸钠盐那样的乙二胺四醋酸化合物、柠檬酸、酒石酸那样的羟基羧酸等。
化学镀液中含有的络合剂的浓度需要相对于铜离子浓度为1倍等量以上的浓度、适宜为1.5倍以上。具体而言，适宜为0.0015～1mol/L，更优选为0.0075～0.8mol/L、特别优选为0.015～0.6mol/L。络合剂的浓度为0.0015～1mol/L时，可以稳定地进行镀覆操作。
作为本发明中所使用的还原剂，例如，可以使用甲醛、乙醛酸、次磷酸、烷基硼烷类等。烷基硼烷类例如可以列举出单烷基胺基硼烷、二烷基胺基硼烷、三烷基胺基硼烷等。
化学镀液中含有的还原剂的浓度适宜为0.001～0.8mol/L、更优选为0.005～0.7mol/L、特别优选为0.01～0.6mol/L。还原剂的浓度为0.001～0.8mol/L时，可以稳定地进行镀覆膜的形成。
作为本发明中所使用的pH调节剂，可以使用碱性的化合物。例如，可以使用氢氧化钾、氢氧化钠、氢氧化四甲基铵(TMAH)等。
作为化学镀液的pH值适宜为9～14、更优选为10～13.5、特别优选为10.5～13。pH值为9～14时，可以稳定地进行镀覆膜的形成。
进而，在本发明中所使用的化学镀铜液中，可以添加烷基硫酸盐、烷基磷酸盐、烷基磺酸盐等表面活性剂、聚乙二醇等水溶性高分子、2,2'-联吡啶、菲咯啉等。
这些添加剂发挥作为提高镀覆被膜的平滑性的整平剂的效果。化学镀铜液中含有的表面活性剂、水溶性高分子的浓度适宜为1ppm～5000ppm。
本发明中的镀覆处理方法若为使被镀覆位置接触镀液的方法则没有特别限定，可以为一次性进行多张处理的批量式、也可以为每次对1张进行处理的单片式。
作为化学镀处理温度，优选为40℃～90℃、更优选为45℃～80℃、特别优选为50℃～70℃。
根据本发明的方法，孔的底中的金属合金膜(防扩散层)的膜厚与孔的入口的金属合金膜(防扩散层)的膜厚的比即阶梯覆盖率((S/C)×100％)优选为30％～300％、进一步优选为40％～250％、特别优选为50％～200％。
作为测定金属合金膜的膜厚的方法，将金属合金膜形成后的评价基材在相对于孔的垂直方向上截断，使用扫描电子显微镜(SEM)观察合金膜截面，测量长度，从而可以求出膜厚。
实施例
以下通过本发明的实施例与比较例，对于该实施方式与效果进行具体地说明，但本发明不限定于这些实施例。
实施例1～11
评价基板
作为评价用的基材，在对硅片使用干蚀刻技术而形成的直径10μm、深度100μm的孔(L/D＝10)的侧壁作为绝缘层成膜硅氧化膜。接着，在硅氧化膜上利用偶联剂形成吸附层之后，使其浸渍于钯(Pd)胶体溶液中，从而形成附着有反应引发催化剂Pd的晶片。
化学镀钴液
调制含有2质量％(0.13mol/L)硫酸钴、6质量％(0.32mol/L)作为络合剂的柠檬酸、5质量％(0.2mol/L)钨酸、0.4质量％(0.07mol/L)作为还原剂的二甲基胺基硼烷，并且用pH调节剂氢氧化四甲基铵将pH值调为9.5的水溶液。
化学镀铜液
调制含有0.5质量％(0.03mol/L)硫酸铜、4质量％(0.14mol/L)乙二胺四醋酸、1质量％(0.14mol/L)乙醛酸、0.005质量％(50ppm)2,2’-联吡啶、0.05质量％(500ppm)聚乙二醇，并且用氢氧化四甲基铵将pH值调为12.5的水溶液。
防扩散层(钴合金膜)形成处理
图2中示出层叠防扩散层以及铜晶种层时的截面示意图。将具有孔的评价基材1在化学镀钴液(图2的A的2)中在60℃下浸渍10分钟(第1阶段处理)，自孔侧壁的入口至中央部形成钴合金膜(防扩散层)3。
接着，在化学镀钴液2中添加添加剂4(下述表1中记载的具有氨基的聚合物)，将第1阶段处理过的上述基材在60℃下浸渍30分钟(第2阶段处理、图2的B)，自孔的侧壁的中央部至底形成钴合金膜(防扩散层)3。需要说明的是，本实施例中使用的具有氨基的聚合物全部为Nittobo Medical Co.,Ltd.制造的市售品。
铜晶种层层叠处理
将第2阶段处理过的上述基材在化学镀铜液5中在45℃下浸渍15分钟，在钴合金膜3上形成铜晶种层6(图2的C的6)。
钴合金膜的膜厚测定
将钴合金膜形成后的评价基材在相对于孔垂直方向上截断，使用扫描电子显微镜(SEM)观察钴合金膜截面，测量长度从而求出膜厚。此外，孔的底的金属合金膜(防扩散层)的膜厚与孔的入口的金属合金膜(防扩散层)的膜厚之比即阶梯覆盖率((S/C)×100％)根据下述(1)式求出。
将阶梯覆盖率为30％～300％判定为合格。
阶梯覆盖率(％)＝{孔的底的膜厚(nm)}/{孔的入口的膜厚(nm)}×100…(1)
铜晶种层成膜确认
将在防扩散层(钴合金膜)上层叠铜晶种层之后的晶片在相对于孔垂直方向上截断，使用扫描电子显微镜，观察铜的成膜状态以及钴合金膜的残存状态。
表1中示出作为第2阶段处理时的化学镀钴液添加剂添加各种具有氨基的聚合物时的、钴合金膜厚以及阶梯覆盖率、铜晶种层有无生长、铜晶种层成膜时有无钴合金膜的消失。
表1
实施例1～11中，形成阶梯覆盖率为30％以上且300％以下的均匀钴合金膜。此外，钴合金膜未消失、形成铜晶种层。
实施例12、13
使用下述的化学镀镍液代替化学镀钴液，除此以外与实施例1同样地进行。
化学镀镍液
调制含有2质量％(0.13mol/L)硫酸镍、4质量％(0.21mol/L)作为络合剂的柠檬酸、0.3质量％(0.05mol/L)作为还原剂的二甲基胺基硼烷，并且用pH调节剂的氢氧化四甲基铵将pH值调为8.5的水溶液。
镍合金膜的膜厚测定
将镍合金膜形成后的评价基材在相对于孔垂直方向上截断，使用扫描电子显微镜(SEM)观察钴合金膜截面，测量长度从而求出膜厚。
此外，将孔的底的金属合金膜(防扩散层)的膜厚与孔的入口的金属合金膜(防扩散层)的膜厚之比即阶梯覆盖率((S/C)×100％)根据上述(1)式求出。
将阶梯覆盖率为30％～300％判定为合格。
铜晶种层成膜确认
将在防扩散层(镍合金膜)上层叠铜晶种层之后的晶片在相对于孔垂直方向上截断，使用扫描电子显微镜，观察铜的成膜状态以及镍合金膜的残存状态。
将实施例12、13的化学镀处理结果在表2中示出。示出镍合金膜厚以及阶梯覆盖率、铜晶种层有无生长、铜晶种层成膜时镍合金膜有无消失。
表2
实施例12以及13中，阶梯覆盖率30％以上的均匀的镍合金膜可以成膜。此外，不使镍合金膜消失，铜晶种层的成膜是可能的。
比较例1
在使用化学镀钴液的第2阶段处理时不添加添加剂(具有氨基的聚合物)，除此以外与实施例1同样地进行。在表3中示出化学镀处理结果。
表3
比较例1中，成膜的结果，不能抑制孔的入口的膜厚生长、成膜阶梯覆盖率不足30％的不均匀的钴合金膜。
比较例2～7
在使用化学镀钴液的第2阶段处理时的添加剂中，添加具有氨基的聚合物以外的胺基化合物，除此以外与实施例1同样地进行。表4中示出在化学镀钴液添加剂中添加各种胺基化合物时的、钴合金膜厚以及阶梯覆盖率、铜晶种层有无生长、铜晶种层成膜时钴合金膜有无消失。
表4
比较例2～7中，成膜的结果，不能抑制孔的入口的膜厚生长，成膜阶梯覆盖率不足30％不均匀的钴合金膜是不合格的。
比较例8～10
在使用化学镀钴液的第2阶段处理时的添加剂中添加硫系化合物，除此以外与实施例1同样地进行。在表5中示出添加作为化学镀钴液添加剂的硫系化合物时的、钴合金膜厚以及阶梯覆盖率、铜晶种层有无生长、铜晶种层成膜时钴合金膜有无消失。
表5
比较例8～10中，进行化学镀铜处理的结果，铜镀覆膜生长、但确认到钴合金膜消失。
比较例11
在实施例1的防扩散层形成中，仅实施化学镀钴处理的第1阶段处理。使用的评价用基材、钴镀液使用与实施例1同样的物质。在表6中示出成膜后的膜厚测定结果。
表6
比较例11中，在孔的侧壁底部膜不生长、成膜阶梯覆盖率不足30％的不均匀的钴合金膜。
比较例12，13
在实施例1的防扩散层的形成中，仅实施化学镀钴处理的第2阶段处理。使用的评价用基材、钴镀液使用与实施例1同样的物质，添加表7记载的具有氨基的聚合物。在表7中示出成膜后的膜厚测定结果。
表7
比较例12以及13中，在贯通孔入口中，未确认到膜的生长，不能在孔的侧壁入口形成膜。
附图标记说明
A  防扩散层形成工序(第1阶段)
B  防扩散层形成工序(第2阶段)
C  铜晶种层层叠工序
1  评价基板
2  化学镀钴液或化学镀镍液
3  防扩散层
4  化学镀液添加剂
5  化学镀铜液
6  铜晶种层

Claims (5)

1.一种贯通电极的形成方法，其中，所述贯通电极的形成方法具有如下工序：对于形成于基板的孔的侧壁，
(1)使用至少含有钴离子或镍离子、络合剂、还原剂以及pH调节剂的化学镀钴液或化学镀镍液，在所述孔的入口至所述孔的中央部形成作为防止铜扩散的层的金属合金膜的工序；
(2)使用至少含有钴离子或镍离子、络合剂、还原剂、pH调节剂以及具有氨基的聚合物的化学镀钴液或化学镀镍液，在所述孔的中央部至所述孔的底形成作为防扩散层的金属合金膜的工序；以及
(3)使用化学镀铜液，在(1)工序以及(2)工序形成的防扩散层上层叠铜晶种层的工序。
2.根据权利要求1所述的贯通电极的形成方法，其中，所述具有氨基的聚合物的含量相对于镀液总量为0.0001质量％～0.02质量％。
3.根据权利要求1或2所述的贯通电极的形成方法，其中，所述具有氨基的聚合物为烯丙基胺聚合物、二烯丙基胺聚合物、或包含烯丙基胺或者二烯丙基胺的共聚物。
4.根据权利要求1～3中任一项所述的贯通电极的形成方法，其中，(1)工序以及(2)工序中使用的镀液含有钨和/或钼。
5.根据权利要求1～4中任一项所述的贯通电极的形成方法，其中，所述孔的底的金属合金膜的膜厚S与所述孔的入口的金属合金膜的膜厚C的比、即阶梯覆盖率S/C×100％为30～300％。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111816608A (zh) * 2020-07-09 2020-10-23 电子科技大学 玻璃盲孔加工方法

Families Citing this family (2)

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Publication number Priority date Publication date Assignee Title
US11133218B1 (en) * 2020-01-23 2021-09-28 Tae Young Lee Semiconductor apparatus having through silicon via structure and manufacturing method thereof
KR102423936B1 (ko) 2020-11-20 2022-07-22 한국생산기술연구원 전해 구리 도금액 및 이를 이용한 실리콘 관통전극의 충전방법

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1867698A (zh) * 2003-10-17 2006-11-22 株式会社日矿材料 无电镀铜溶液
US20070166991A1 (en) * 2003-09-23 2007-07-19 Nishant Sinha Methods for forming conductive vias in semiconductor device components
JP2010185113A (ja) * 2009-02-12 2010-08-26 Kansai Univ 無電解銅めっき液、無電解銅めっき方法、及び埋め込み配線の形成方法
CN102534582A (zh) * 2010-12-25 2012-07-04 管静 无电镀铜溶液
CN103502509A (zh) * 2011-05-05 2014-01-08 埃其玛公司 将基于镍或钴的金属层沉积在半导体固体衬底上的方法以及用来应用该方法的试剂盒

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002093747A (ja) * 2000-09-19 2002-03-29 Sony Corp 導体構造の形成方法及び導体構造、並びに半導体装置の製造方法及び半導体装置
JP3567377B2 (ja) 2002-01-09 2004-09-22 独立行政法人 科学技術振興機構 半導体集積回路装置の製造方法
JP5525762B2 (ja) * 2008-07-01 2014-06-18 上村工業株式会社 無電解めっき液及びそれを用いた無電解めっき方法、並びに配線基板の製造方法
JP2012175073A (ja) 2011-02-24 2012-09-10 Tokyo Electron Ltd 成膜方法および記憶媒体
JP5917297B2 (ja) 2012-05-30 2016-05-11 東京エレクトロン株式会社 めっき処理方法、めっき処理装置および記憶媒体

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070166991A1 (en) * 2003-09-23 2007-07-19 Nishant Sinha Methods for forming conductive vias in semiconductor device components
CN1867698A (zh) * 2003-10-17 2006-11-22 株式会社日矿材料 无电镀铜溶液
JP2010185113A (ja) * 2009-02-12 2010-08-26 Kansai Univ 無電解銅めっき液、無電解銅めっき方法、及び埋め込み配線の形成方法
CN102534582A (zh) * 2010-12-25 2012-07-04 管静 无电镀铜溶液
CN103502509A (zh) * 2011-05-05 2014-01-08 埃其玛公司 将基于镍或钴的金属层沉积在半导体固体衬底上的方法以及用来应用该方法的试剂盒

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111816608A (zh) * 2020-07-09 2020-10-23 电子科技大学 玻璃盲孔加工方法
CN111816608B (zh) * 2020-07-09 2023-05-09 电子科技大学 玻璃盲孔加工方法

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