TWI668869B - 半導體裝置及半導體裝置之製造方法 - Google Patents

半導體裝置及半導體裝置之製造方法 Download PDF

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TWI668869B
TWI668869B TW104126662A TW104126662A TWI668869B TW I668869 B TWI668869 B TW I668869B TW 104126662 A TW104126662 A TW 104126662A TW 104126662 A TW104126662 A TW 104126662A TW I668869 B TWI668869 B TW I668869B
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insulating film
film
region
recessed portion
substrate
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TW104126662A
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TW201614845A (en
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滿生彰
中山知士
清水繁明
奧秋廣幸
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日商瑞薩電子股份有限公司
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Abstract

本發明之課題係抑制在凹部附近發生電場集中。於基板SUB形成有閘極絕緣膜GI1。再者，於基板SUB形成有汲極區域DR1。於基板SUB形成有凹部RD。凹部RD位於閘極絕緣膜GI1與汲極區域DR1之間。於凹部RD埋置有絕緣膜DF。在閘極絕緣膜GI1側於絕緣膜DF形成有凹部RD1。又，在汲極區域DR1之閘極絕緣膜GI1側，以凹部RD之內側面及基板SUB之表面形成的角CR1呈圓形。

Description

半導體裝置及半導體裝置之製造方法
本發明係有關於半導裝置及半導體裝置之製造方法，例如可應用於功率電晶體之技術。
在半導體裝置中，有時會在半導體基板上形成複數電晶體。此時，為了使各電晶體電性絕緣，有時會使用STI(Shallow Trench Isolation：淺溝槽隔離)。
專利文獻1記載有STI之一例。在專利文獻1中，首先，於矽基板之表面形成凹部。其次，將絕緣膜埋置於凹部。接著，蝕刻矽基板之表面。藉此，可使上述絕緣膜之上面位於矽基板的表面之上方。然後，藉由熱氧化於矽基板之表面形成氧化膜。之後，去除氧化膜。接著，藉由熱氧化於矽基板之表面形成閘極絕緣膜。於專利文獻1記載有在上述絕緣膜(凹部)附近氧濃度比其他區域高。又，於專利文獻1記載有閘極絕緣膜之膜厚在凹部附近比其他區域厚。
[先前技術文獻]
[專利文獻]
[專利文獻1]
日本專利公開公報2005-19703號
有在STI中形成之凹部附近形成閘極電極及閘極絕緣膜之情形。再者，有對上述凹部附近施加高電壓之情形。此時，需抑制在凹部附近發生電場集中。其他課題及新特徵從本說明書之記述及隨附圖式應可明白。
根據一實施形態，半導體裝置包含有基板及第1電晶體。第1電晶體具有閘極絕緣膜。再者，電晶體具有作為汲極及源極其中一者之第1雜質區域。於基板形成有第1凹部。第1凹部位於閘極絕緣膜與第1雜質區域之間。又，在第1凹部之該閘極絕緣膜側，以第1凹部之內側面及基板的表面形成之第1角呈圓形。
根據該一實施形態，可抑制在凹部附近發生電場集中。
ANC‧‧‧類比電路
ANR‧‧‧類比區域
ARC‧‧‧防反射膜
CON‧‧‧凸部
CR1‧‧‧角
CR2‧‧‧角
CT1‧‧‧接點
CT2‧‧‧接點
DF‧‧‧絕緣膜
DGC‧‧‧數位電路
DGR‧‧‧數位區域
DR1‧‧‧汲極區域
DR2‧‧‧汲極區域
GE‧‧‧導電膜
GE1‧‧‧閘極電極
GE2‧‧‧閘極電極
GI1‧‧‧閘極絕緣膜
GI2‧‧‧閘極絕緣膜
IL‧‧‧絕緣層
IR‧‧‧分離區域
LD1‧‧‧LDD區域
LD2‧‧‧LDD區域
LS1‧‧‧LDS區域
LS2‧‧‧LDS區域
MK1‧‧‧遮罩膜
MK2‧‧‧遮罩膜
NT1‧‧‧氮化膜
NT2‧‧‧氮化膜
OP1‧‧‧開口
OP2‧‧‧開口
OP3‧‧‧開口
OX1‧‧‧氧化膜
OX2‧‧‧氧化膜
OX3‧‧‧氧化膜
PRO‧‧‧突出部
RD‧‧‧凹部
RD1‧‧‧凹部
RE1‧‧‧凹部
REC‧‧‧凹部
RG1‧‧‧第1區域
RG2‧‧‧第2區域
RS‧‧‧凹部
RS1‧‧‧凹部
SR1‧‧‧源極區域
SR2‧‧‧源極區域
SUB‧‧‧基板
SW1‧‧‧側壁
SW2‧‧‧側壁
TR1‧‧‧電晶體
TR2‧‧‧電晶體
T1‧‧‧膜厚
T2‧‧‧膜厚
WL1‧‧‧阱
WL2‧‧‧阱
α‧‧‧部份
β‧‧‧部份
圖1係顯示用於第1實施形態之半導體裝置的電晶體之結構的俯視圖。
圖2係圖1之A-A'剖面圖。
圖3(a)~(b)係放大圖2所示之凹部的圖。
圖4(a)~(b)係放大圖2所示之凹部的圖。
圖5係顯示圖2之變形例的圖。
圖6係顯示圖3所示之半導體裝置之製造方法的剖面圖。
圖7係顯示圖3所示之半導體裝置之製造方法的剖面圖。
圖8係顯示圖3所示之半導體裝置之製造方法的剖面圖。
圖9係顯示圖3所示之半導體裝置之製造方法的剖面圖。
圖10係顯示圖3所示之半導體裝置之製造方法的剖面圖。
圖11係顯示圖3所示之半導體裝置之製造方法的剖面圖。
圖12係顯示圖3所示之半導體裝置之製造方法的剖面圖。
圖13係顯示圖3所示之半導體裝置之製造方法的剖面圖。
圖14係顯示圖3所示之半導體裝置之製造方法的剖面圖。
圖15係顯示比較例之半導體裝置之製造方法的剖面圖。
圖16係顯示比較例之半導體裝置之製造方法的剖面圖。
圖17係顯示比較例之半導體裝置之製造方法的剖面圖。
圖18係顯示比較例之半導體裝置之製造方法的剖面圖。
圖19係顯示比較例之半導體裝置之製造方法的剖面圖。
圖20係顯示圖6至圖14所示之方法的變形例之圖。
圖21係顯示圖6至圖14所示之方法的變形例之圖。
圖22係顯示圖6至圖14所示之方法的變形例之圖。
圖23係顯示圖6至圖14所示之方法的變形例之圖。
圖24係顯示圖6至圖14所示之方法的變形例之圖。
圖25係顯示圖6至圖14所示之方法的變形例之圖。
圖26係顯示第2實施形態之半導體裝置的結構之俯視圖。
圖27係顯示電晶體之結構的剖面圖。
圖28係顯示電晶體之結構的俯視圖。
圖29係顯示圖27所示之半導體製造裝置之製造方法的剖面圖。
圖30係顯示圖27所示之半導體製造裝置之製造方法的剖面圖。
圖31係顯示圖27所示之半導體製造裝置之製造方法的剖面圖。
圖32係顯示圖27所示之半導體製造裝置之製造方法的剖面圖。
圖33係顯示圖27所示之半導體製造裝置之製造方法的剖面圖。
圖34係顯示圖27所示之半導體製造裝置之製造方法的剖面圖。
圖35係顯示圖27所示之半導體製造裝置之製造方法的剖面圖。
圖36係顯示圖27所示之半導體製造裝置之製造方法的剖面圖。
圖37係顯示圖27所示之半導體製造裝置之製造方法的剖面圖。
圖38係顯示圖27所示之半導體製造裝置之製造方法的剖面圖。
圖39係顯示圖27所示之半導體製造裝置之製造方法的剖面圖。
[用以實施發明之形態]
以下，就實施形態，參照圖式來說明。此外，在所有圖式中，對相同之構成要件附上相同之標號，而適宜省略說明。
(第1實施形態)
圖1係顯示用於第1實施形態之半導體裝置的電晶體TR1之結構的俯視圖。圖2係圖1之A-A'剖面圖。如圖2所示，電晶體TR1係使用基板SUB而形成。具體而言，於基板SUB形成有阱WL1。然後，電晶體TR1係使用阱WL1而形成。如本圖所示，電晶體TR1具有閘極電極GE1、閘極絕緣膜GI1、汲極區域DR1(第1雜質區域)、源極區域SR1(第2雜質區域)、LDD(Lightly-Doped Drain：輕摻雜汲極)區域LD1、LDS(Lightly-Doped Source：輕摻雜源極)區域LS1、及側壁SW1。
參照圖1，就電晶體TR1之俯視配置作說明。在電晶體TR1，汲極(汲極區域DR1)、閘極電極GE1、及源極(源極區域SR1)於第1方向(X1方向)依序排列。又，汲極區域DR1、閘極電極GE1、及源極區域SR1分別在垂直於第1方向(X1方向)之第2方向(Y1方向)延伸。
於基板SUB形成有分離區域IR。如參照圖2在之後所述，分離區域IR為埋置於基板SUB之凹部REC(圖2)的絕緣膜DF(圖2)。換言之，分離區域IR以STI形成。如圖1所示，汲極區域DR1及源極區域SR1以俯視觀之由分離區域IR包圍。此時，如參照圖2在之後所述，於汲極區域DR1與閘極電極GE1之間形成有凹部RD(分離區域IR)。同樣地，於源極區域SR1與閘極電極GE1之間形成有凹部RS(分離區域IR)。
如圖1所示，於汲極區域DR1設有複數接點CT1。該等接點CT1沿著第2方向(Y1方向)配置。於源極區域SR1設有複數接點CT1。該等接點CT1沿著第2方向(Y1方向)配置。
如本圖所示，LDD區域LD1以俯視觀之，內側包含汲極區域DR1。同樣地，LDS區域LS1以俯視觀之，內側包含源極區域SR1。再者，LDD區域LD1之源極區域SR1側的側面進入閘極電極GE1。同樣地，LDS區域LS1之汲極區域DR1側的側面進入閘極電極GE1。
接著，參照圖2，就電晶體TR1之剖面構造作說明。如本圖所示，於阱WL1形成有LDD區域LD1及LDS區域LS1。於LDD區域LD1形成有汲極區域DR1。於LDS區域LS1形成有源極區域SR1。於LDD區域LD1及LDS區域LS1之間形成有閘極絕緣膜GI1。又，凹部RD(第1凹部)位於汲極區域DR1與閘極絕緣膜GI1之間。另一方面，凹部RS(第3凹部)位於源極區域SR1與閘極絕緣膜GI1之間。
此外，LDD區域LD1及LDS區域LS1為具有與阱WL1相反導電型態的區域。又，汲極區域DR1比LDD區域LD1淺且雜質濃度高於LDD區域LD1。同樣地，源極區域SR1比LDS區域LS1淺且雜質濃度高於LDS區域LS1。
於凹部RD埋置有絕緣膜DF(第1絕緣膜)。同樣地，於凹部RS埋置有絕緣膜DF(第2絕緣膜)。絕緣膜DF為例如氧化矽膜。在本圖所示之例中，凹部RD之絕 緣膜DF及凹部RS之絕緣膜DF與閘極絕緣膜GI1一體。又，凹部RD之絕緣膜DF於閘極絕緣膜GI1側之區域具有凹部RD1(第2凹部)。同樣地，凹部RS之絕緣膜DF於閘極絕緣膜GI1側之區域具有凹部RS1(第4凹部)。於凹部RD1及凹部RS1分別埋置有閘極電極GE1之一部份。
閘極電極GE1位於基板SUB上。再者，於閘極電極GE1之側面形成有側壁SW1。此外，閘極電極GE1以例如多晶矽形成。側壁SW1以例如氧化矽膜或氮化矽膜形成。
電晶體TR1以絕緣層IL覆蓋。於絕緣層IL埋置有接點CT1。汲極區域DR1側之接點CT1連接於汲極區域DR1。源極區域SR1側之接點CT1連接於源極區域SR1。
圖3(a)係放大圖2所示之凹部RD的圖。圖3(b)係圖3(a)之α部份的放大圖。如本圖(a)所示，以凹部RD之內側面及基板SUB之表面形成的角(角CR1)位在凹部RD之閘極絕緣膜GI1側。又，如本圖(b)所示，角CR1呈圓形。藉此，可抑制在角CR1之電場集中。
詳細而言，如本圖(a)所示，基板SUB之表面除了角CR1外，其餘位於一直線(第1直線)上。同樣地，凹部RD中閘極絕緣膜GI1側之內側面除了角CR1外，其餘位在一直線(第2直線)上。此時，角CR1便位於上述第1直線及上述第2直線構 成之角的內側。此外，第1直線及第2直線構成之角度為例如90度以上、120度以下。
再者，如本圖(a)所示，閘極絕緣膜GI1及絕緣膜DF形成為一體。又，在凹部RD之閘極絕緣膜GI1側，構成閘極絕緣膜GI1及絕緣膜DF之絕緣膜沿著角CR1形成。藉此，凹部RD1在內側面便具有上述絕緣膜中沿著角CR1形成之部份。
此外，凹部RD之深度(在本圖(a)中，在基板SUB之厚度方向，汲極區域DR1之上面與凹部RD的底面之間的距離)為例如200nm以上、400nm以下。再者，上述第1直線(沿著基板SUB之表面的直線)及上述第2直線(沿著凹部RD之內側面的直線)構成之角度如上述，為例如90度以上120度以下。又，凹部RD之深度及上述角度如上述時，角CR1形成曲率半徑之最小值為例如10nm以上、200nm以下的圓。
圖4(a)係放大圖2所示之凹部RS的圖。圖4(b)係圖4(a)之β部份的放大圖。如本圖(a)所示，以凹部RS之內側面與基板SUB之表面形成的角(角CR2)位在凹部RS之閘極絕緣膜GI1側。又，如本圖(b)所示，角CR2呈圓形。藉此，可抑制在角CR2之電場集中。
詳細而言，如本圖(a)所示，基板SUB之表面除了角CR2外，其餘位於一直線(第3直線)上。同樣地，凹部RS中閘極絕緣膜GI1側之內側面除了角CR2外，其餘 位於一直線(第4直線)上。此時，角CR2便位於上述第3直線及上述第4直線構成之角的內側。此外，第3直線及第4直線構成之角度為例如90度以上、120度以下。
再者，如本圖(a)所示，閘極絕緣膜GI1及絕緣膜DF形成為一體。又，在凹部RS之閘極絕緣膜G11側，構成閘極絕緣GI1及絕緣膜DF之絕緣膜沿著角CR2形成。藉此，凹部RS1於內側面便具有上述絕緣膜中沿著角CR2形成之部份。
此外，凹部RS之深度(在本圖(a)中在基板SUB之厚度方向中源極區域SR1的上面與凹部RD之底面之間的距離)為例如200nm以上、400nm以下。再者，上述第3直線(沿著基板SUB之表面的直線)及上述第4直線(沿著凹部RS之內側面的直線)構成之角如上述為例如90度以上、120度以下。又，凹部RS之深度及上述角度如上述時，角CR2形成曲率半徑之最小值為例如10nm以上、200nm以下的圓。
圖5係顯示圖2之變形例的圖。有時在源極區域SR1與阱WL1之間不要求高耐電壓。此時，如本圖所示，亦可不形成LDS區域LS1(圖2)及凹部RS(圖2)。在本圖所示之例中，閘極絕緣膜GI1之汲極區域DR1側的端部到達汲極區域DR1。
圖6至圖14係顯示圖3所示之半導體裝置之製造方法的剖面圖。首先，如圖2所示，於基板SUB形成阱WL1。接著，於阱WL1形成LDD區域LD1及LDS區域LS1。
接著，如圖6所示，於基板SUB上依序層積氧化膜OX1(例如氧化矽膜)、氮化膜NT1(例如氮化矽膜)(第1絕緣膜)、防反射膜ARC、及遮罩膜MK1。然後，以微影方式，於遮罩膜MK1形成開口OP1。
之後，如圖7所示，將遮罩膜MK1作為遮罩，蝕刻氮化膜NT1、氧化膜OX1、及基板SUB。藉此，於氮化膜NT1及氧化膜OX1形成開口OP2。進一步，藉由開口OP2於基板SUB形成凹部RD。然後，去除遮罩膜MK1及防反射膜ARC。
接著，如圖8所示，於基板SUB上及氮化膜NT1上形成絕緣膜DF(例如氧化矽膜)(第2絕緣膜)。藉此，以絕緣膜DF埋置凹部RD及開口OP2。進一步，於氮化膜NT1上形成絕緣膜DF。此外，絕緣膜DF藉由例如CVD(Chemical Vapor Deposition：化學氣相沉積)形成。
然後，如圖9所示，去除絕緣膜DF之表層。藉此，可去除氮化膜NT1上之絕緣膜DF。絕緣膜DF之去除使用例如CMP(Chemical Mechanical Polishing：化學機械研磨)。
接著，如圖10所示，進一步去除絕緣膜DF之表層。藉此，可使絕緣膜DF之上面的高度低於氮化膜NT1之上面的高度。再者，在本圖所示之例中，絕緣膜DF之上面的高度高於基板SUB之表面。此外，絕緣膜DF之去除使用例如濕式蝕刻。
接著，如圖11所示，於絕緣膜DF上及氮化膜NT1上形成氮化膜NT2(例如氮化矽膜)(第3絕緣膜)。此時，如本圖所示，氮化膜NT2在與凹部RD重疊之區域具有凹部RE1。此是因絕緣膜DF之上面低於氮化膜NT1的上面之故。此時，於絕緣膜DF之上面與氮化膜NT1的上面之間產生階差。藉此階差，於氮化膜NT2之上面如上述形成凹部RE1。此外，凹部RE1之深度為例如10nm以上、100nm以下。
然後，如圖12所示，於氮化膜NT2上形成遮罩膜MK2。此時，遮罩膜MK2覆蓋「以俯視觀之，內側包含凹部RE1之一部份的區域(第1區域RG1)」。換言之，遮罩膜MK2未覆蓋「以俯視觀之，內側包含凹部RE1之剩餘部份的區域(第2區域RG2)」。此時，第2區域RG2為在之後的步驟中形成閘極絕緣膜GI1(圖3)之區域。
接著，如圖13所示，將遮罩膜MK2作為遮罩，蝕刻氮化膜NT2、氮化膜NT1、氧化膜OX1、及絕緣膜DF。藉此，在第2區域RG2中，去除氮化膜NT2、氮化膜NT1、及氧化膜OX1。進一步，在第2區域RG2中，使絕緣膜DF之上面位於凹部RD之上端的下方。此時，在第2區域RG2中，去除基板SUB之一部份。此時，如之後細節所述，在第2區域RG2中，以凹部RD之內側面及基板SUB的表面形成之角(角CR1)呈圓形。之後，去除遮罩膜MK2。
就角CR1呈圓形之理由作說明。如圖12所示，於氮化膜NT2之上面因凹部RE1而產生階差。又，在圖12及圖13所示之例中，基板SUB之厚度方向的蝕刻在任一區域皆大致均一地進行。此時，氮化膜NT2之上述階差的形狀會轉印於基板SUB之表面。藉此，角CR1呈圓形。
然後，如圖14所示，在第1區域RG1仍殘留氮化膜NT2之狀態下，在第2區域RG2，藉例如熱氧化，於基板SUB形成氧化膜OX2。氧化膜OX2係作為閘極絕緣膜GI1的絕緣膜。此時，於凹部RD之絕緣膜DF形成側面具有氧化膜OX2(閘極絕緣膜GI2)之凹部(凹部RD1)。接著，形成閘極電極GE1及側壁SW1。藉此，可製造圖3所示之半導體裝置。
圖15至圖19係顯示比較例之半導體裝置之製造方法的剖面圖。比較例除了以下點外，其餘與本實施形態相同。首先，在比較例中，與本實施形態同樣地，實施圖6至圖9所示之步驟。
接著，如圖15所示，去除氮化膜NT1(圖9)。藉此，絕緣膜DF之上面得以位於氧化膜OX1(基板SUB)之上面的上方。
然後，如圖16所示，於氧化膜OX1(基板SUB)上及絕緣膜DF上形成氮化膜NT2。此時，如本圖所示，氮化膜NT2之上面在凹部RD上具有凸部CON。此係因絕緣膜DF之上面低於氧化膜OX1(基板SUB)的上面之故。此時，於絕緣膜DF之上面與氧化膜OX1(基板SUB)的上面之間產生階差。又，藉此階差而於氮化膜NT2之上面如上述形成凸部CON。
接著，如圖17所示，在氮化膜NT2上形成遮罩膜MK2。此時，遮罩膜MK2覆蓋「以俯視觀之，內側包含凹部RD之一部份的區域(第1區域RG1)」。換言之， 遮罩膜MK2未覆蓋「以俯視觀之，內側包含凹部RD之剩餘部份的區域(第2區域RG2)」。此時，第2區域RG2係在之後的步驟形成閘極絕緣GI1(圖3)之區域。
然後，如圖18所示，將遮罩膜MK2作為遮罩，來蝕刻氮化膜NT2、氧化膜OX1及絕緣膜DF。藉此，在第2區域RG2，可去除氮化膜NT2及氧化膜OX1。進一步，在第2區域RG2中，使絕緣膜DF之上面位於凹部RD之上端的下方。此時，在第2區域RG2，去除基板SUB之一部份。此時，如之後細節所述，在第2區域RG2，於「以凹部RD之內側面與基板SUB的表面形成之角(角CR1)」會形成突出部PRO。突出部PRO從基板SUB之表面往上突出。接著，去除遮罩膜MK2。
就形成突出部PRO之理由作說明。如圖17所示，於氮化膜NT2之上面因凸部CON而產生階差。在圖17及圖18所示之例中，基板SUB之厚度方向的蝕刻在任一區域皆大致均一地進行。又，如圖17所示，氮化膜NT2之形成有上述階差的部份之膜厚(基板SUB之厚度方向的厚度)比其他部份之膜厚(基板SUB之厚度方向的厚度)厚。此時，「形成有上述階差之區域」的蝕刻比剩餘區域之蝕刻晚到達基板SUB。因此，在「形成有上述階差之區域」與剩餘區域之間，基板SUB之蝕刻量產生差異。結果，形成突出部PRO。
然後，如圖19所示，在第1區域RG1仍殘留氮化膜NT2之狀態下，在第2區域RG2，藉由例如熱氧化，於基板SUB形成氧化膜OX2。氧化膜X2係作為閘極絕緣膜GI1之絕緣膜。此時，於基板SUB之表面殘留有突出部PRO。此種突出部PRO可能為電場集中之原因。
對比本實施形態(圖6~圖14)與比較例(圖15至圖19)。在本實施形態中，如圖11所示，氮化膜NT2之上面在凹部RD上具有凹部RE1。又，如上述，以凹部RD之內側面及基板SUB之表面形成的角(角CR1)因凹部RE1而呈圓形(圖13)。相對於此，在比較例中，如圖16所示，氮化膜NT2之上面在凹部RD上具有凸部CON。又，如上述，角CR1因凸部CON而具有突出部PRO(圖18)。從此對比可明瞭，角CR1呈圓形或具有突出部PRO係根據氮化膜NT2之上面的形狀決定。
再者，如上述，在本實施形態中，如圖13所示，角CR1呈圓形。藉此，在本實施形態中，可抑制在角CR1之電場集中。相對於此，在比較例中，如圖18所示，角CR1具有突出部PRO。因此在比較例中，突出部PRO可能為電場集中之原因。從此對比可明瞭，在本實施形態，比起比較例，更可抑制在角CR1之電場集中。
以上，根據本實施形態，以凹部RD之內側面及基板SUB之表面形成的角(角CR1)呈圓形。藉此，可有效地抑制在角CR1之電場集中。
圖20至圖25係顯示圖6至圖14所示之方法的變形例之圖。本變形例除了以下之點外，其餘與本實施形態相同。首先，在本變形例中，與本實施形態同樣地，實施圖6至圖9所示之步驟。
接著，如圖20所示，進一步去除絕緣膜DF之表層。藉此，可使絕緣膜DF之上面的高度低於凹部RD之上端的高度。此外，絕緣膜DF之去除使用例如濕式蝕刻。
然後，如圖21所示，去除氮化膜NT1(圖20)。
之後，如圖22所示，於氧化膜OX1(基板SUB)上及絕緣膜DF上形成氮化膜NT2(第3絕緣膜)。此時，如本圖所示，氮化膜NT2在與凹部RD重疊之區域具有凹部RE1。此係因絕緣膜DF之上面低於氧化膜OX1(基板SUB)的上面之故。此時，於絕緣膜DF之上面與氧化膜OX1(基板SUB)的上面之間產生階差。又，藉此階差，而於氮化膜NT2之上面如上述形成凹部RE1。
接著，如圖23所示，於氮化膜NT2上形成遮罩膜MK2。此時，遮罩膜MK2覆蓋「以俯視觀之，內側包含凹部RE1之一部份的區域(第1區域RG1)」。換言之，遮罩膜MK2未覆蓋「以俯視觀之，內側具有凹部RE1之剩餘部份的區域(第2區域RG2)」。此時，第2區域RG2為在之後的步驟形成閘極絕緣膜GI1(圖3)之區域。
然後，如圖24所示，將遮罩膜MK2作為遮罩，來蝕刻氮化膜NT2、氧化膜OX1及絕緣膜DF。藉此，在第2區域RG2，可去除氮化膜NT2及氧化膜OX1。進一步，在第2區域RG2，使絕緣膜DF之上面位於凹部RD的上端之下方。此時，在第2區域RG2中，去除基板SUB之一部份。又，此時，與本實施形態(例如圖13) 同樣地，在第2區域RG2，以凹部RD之內側面與基板SUB之表面形成的角(角CR1)呈圓形。接著，去除遮罩膜MK2。
接著，如圖25所示，在第1區域RG1仍殘留氮化膜NT2之狀態下，在第2區域RG2中，藉例如熱氧化於基板SUB形成氧化膜OX2。氧化膜OX2係作為閘極絕緣膜GI1之絕緣膜。此時，於凹部RD之絕緣膜DF形成「側面具有氧化膜OX2(閘極絕緣膜GI2)之凹部(凹部RD1)」。
在本變形例中，也與本實施形態同樣地，以凹部RD之內側面及基板SUB之表面形成的角(角CR1)呈圓形。藉此，可有效地抑制在角CR1之電場集中。
(第2實施形態)
圖26係顯示第2實施形態之半導體裝置的結構之俯視圖。本實施形態之半導體裝置除了以下之點外，其餘為與第1實施形態之半導體裝置相同的結構。
在本圖所示之例中，半導體裝置為LCD(Liquid Crystal Display：液晶顯示器)驅動器。詳細言之，如本圖所示，半導體裝置於同一基板SUB具有類比區域ANR及數位區域DGR。基板SUB為半導體基板，為例如矽基板或SOI(Silicon On Insulator：矽絕緣體)基板。又，基板SUB之俯視形狀為矩形。類比區域ANR及數位區域DGR於上述矩形之長向彼此對向。此外，半導體裝置之俯視配置並不限本圖所示之例。
類比區域ANR包含類比電路ANC(第1電路)。數位區域DGR包含數位電路DGC(第2電路)。類比電路ANC之電源電位為第1電壓。數位電路DGC之電源電位為第2電壓。第2電壓低於第1電壓。舉例而言，第1電壓約10V，第2電壓則約1V。類比電路ANC係例如生成用以驅動LCD之電壓的電路。數位電路DGC為例如邏輯電路。
圖27係顯示電晶體TR1之結構及電晶體TR2的結構之剖面圖。圖28係顯示電晶體TR2之結構的俯視圖。圖27所示之類比區域ANR對應圖2。圖27所示之數位區域DGR對應圖28之B-B'剖面。
在本實施形態中，電晶體TR1構成圖26所示之類比電路ANC。電晶體TR2構成圖26所示之數位電路DGC。如圖27所示，電晶體TR1及電晶體TR2係使用同一基板SUB形成。此外，本實施形態之電晶體TR1係與第1實施形態之電晶體TR1相同的結構。
如圖27所示，基板SUB於數位區域DGR具有阱WL2。電晶體TR2係使用阱WL2形成。電晶體TR2具有閘極電極GE2、閘極絕緣膜GI2、汲極區域DR2、源極區域SR2、LDD區域LD2、LDS區域LS2、及側壁SW2。
參照圖28，就電晶體TR2之俯視配置作說明。在電晶體TR2，汲極(汲極區域DR2)、閘極電極GE2、及源極(源極區域SR2)於第3方向(X2方向)依序排列。又，汲極區域DR2、閘極電極GE2、及源極區域SR2分別在垂直於第3方向之第4方向 (Y2方向)延伸。此外，第3方向(X2方向)及第4方向(Y2)可分別與第1方向(X1方向)及第2方向(Y1方向)(圖1)相同，或者，亦可分別與第1方向(X1方向)及第2方向(Y1方向)(圖1)不同。
如上述，於基板SUB形成有分離區域IR。如本圖所示，汲極區域DR2及源極區域SR2由分離區域IR規定。此外，在本圖所示之例中，未於汲極區域DR2與源極區域SR2之間形成分離區域IR。LDD區域LD2、閘極電極GE2及LDS區域LS2位於汲極區域DR2與源極區域SR2之間。
於汲極區域DR2設有複數接點CT2。該等接點CT2沿著第4方向(Y2方向)配置。於源極區域SR2設有複數接點CT2。該等接點CT2沿著第4方向(Y2方向)配置。
接著，參照圖27，就電晶體TR2之剖面構造作說明。如本圖所示，電晶體TR2於基板SUB上具有閘極電極GE2，基板SUB(阱WL2)具有汲極區域DR2及源極區域SR2。
如本圖所示，LDD區域LD2位於閘極電極GE2與汲極區域DR2之間。LDD區域LD2係具有與阱WL2相反導電型態的區域，且雜質濃度低於汲極區域DR2。同樣地，LDS區域LS2位於閘極電極GE2與源極區域SR2之間。LDS區域LS2為具有與阱WL2相反導電型態的區域，且雜質濃度低於源極區域SR2。
閘極絕緣膜GI2位於基板SUB與閘極電極GE2之間。在本實施形態中，閘極絕緣膜GI2為例如與閘極絕緣膜GI1相同種類之絕緣膜(例如氧化矽膜)。又，閘極絕緣膜GI2之膜厚T2薄於閘極絕緣膜GI1之膜厚T1。此係因數位電路DGC之電源電位(第2電壓)如上述低於類比電路ANC的電源電壓(第1電壓)之故。換言之，電晶體TR2(構成數位電路DGC之電晶體)的耐電壓亦可低於電晶體TR1(構成類比電路ANC之電晶體)的耐電壓。藉此，可使閘極絕緣膜GI2之膜厚T2薄於閘極絕緣膜GI1之膜厚T1。
再者，在本圖所示之例中，第3方向(X2方向)之閘極電極GE2的長度L2短於第1方向(X1)方向之閘極電極GE1的長度L1。此與上述同樣地係因電晶體TR2之耐電壓低於電晶體TR1之耐電壓之故。藉此，可使閘極電極GE2之長度L2低於閘極電極GE1之長度L1。
與電晶體TR1同樣地，電晶體TR2以絕緣層IL覆蓋。於絕緣層IL埋置有接點CT2。汲極區域DR2側之接點CT2連接於汲極區域DR2。源極區域SR2側之接點CT2連接於源極區域SR2。
圖29至圖39係顯示圖27所示之半導體裝置之製造方法的剖面圖。首先，如圖29所示，於基板SUB形成阱WL1、WL2。接著，於阱WL1形成LDD區域LD1及LDS區域LS1。然後，於基板SUB上依序層積氧化膜OX1(例如氧化矽膜)、氮化膜NT1、防反射膜ARC、及遮罩膜MK1。之後，以微影方式於遮罩膜MK1形成開口OP1。
接著，如圖30所示，將遮罩膜MK1作為遮罩，來蝕刻氮化膜NT1、氧化膜OX1、及基板SUB。藉此，於氮化膜NT1及氧化膜OX1形成開口OP1。進一步，藉由開口OP2於基板SUB形成凹部REC。此時，凹部REC於類比區域ANR包含凹部RD、RS。然後，去除遮罩膜MK1及防反射膜ARC。
之後，如圖31所示，於基板SUB上及氮化膜NT1上形成絕緣膜DF。藉此，以絕緣膜DF埋置凹部REC及開口OP2。進一步，於氮化膜NT1上形成絕緣膜DF。此外，絕緣膜DF藉由例如CVD(Chemical Vapor Deposition：化學氣相沉積)形成。
接著，如圖32所示，去除絕緣膜DF之表層。藉此，可去除氮化膜NT1上之絕緣膜DF。絕緣膜DF之去除使用例如CMP(Chemical Mechanical Polishing：化學機械研磨)。
然後，如圖33所示，進一步去除絕緣膜DF之表層。藉此，可使絕緣膜DF之上面的高度低於氮化膜NT1之上面的高度。再者，在本圖所示之例中，絕緣膜DF之上面的高度高於基板SUB之表面。此外，絕緣膜DF之去除使用例如濕式蝕刻。
之後，如圖34所示，於絕緣膜DF上及氮化膜NT1上形成氮化膜NT2。此時，與第1實施形態(圖11)同樣地，如本圖所示，氮化膜NT2在與凹部REC重疊之區域具有凹部RE1。
接著，如圖35所示，於氮化膜NT2上形成遮罩膜MK2。遮罩膜MK2於第2區域RG2具有開口OP3。第2區域RG2係在之後的步驟形成閘極絕緣膜GI1(圖27)之區域。遮罩膜MK2在第2區域RG2以外之區域(第1區域RG1)覆蓋氮化膜NT2。
之後，如圖36所示，將遮罩膜MK2作為遮罩，來蝕刻氮化膜NT2、氮化膜NT1、氧化膜OX1、及絕緣膜DF。藉此，在第2區域RG2，去除氮化膜NT2、氮化膜NT1及氧化膜OX1。進一步，在第2區域RG2，使絕緣膜DF之上面位於凹部REC之上端的下方。此時，在第2區域RG2，去除基板SUB之一部份。此時，與第1實施形態(例如圖13)同樣地，在第2區域RG2，以凹部REC之內側面及基板SUB之表面形成的角(角CR1、CR2)呈圓形。接著，去除遮罩膜MK2。
在本圖所示之步驟中，數位區域DGR之基板SUB以氮化膜NT2覆蓋。因此，在本圖所示之步驟中，無法去除數位區域DGR之絕緣膜DF的上面。因此，如圖27所示，數位區域DGR之絕緣膜DF的上面得以位於凹部RD1之底面及凹部RS1的底面之上方。
然後，如圖37所示，在第1區域RG1仍殘留氮化膜NT2之狀態下，在第2區域RG2藉由例如熱氧化於基板SUB形成氧化膜OX2。氧化膜OX2係作為閘極絕緣膜GI1之絕緣膜。此時，於凹部RD、RS之絕緣膜DF分別形成「側面具有氧化膜OX2(閘極絕緣膜GI2)的凹部RD1、RS1」。
之後，如圖38所示，去除氮化膜NT2、氮化膜NT1及氧化膜OX1。接著，藉由例如熱氧化於基板SUB形成氧化膜OX3。氧化膜OX3係作為閘極絕緣膜GI2(圖27)之絕緣膜。然後，於基板SUB上形成導電膜GE。導電膜GE係作為閘極電極GE1、GE2(圖27)之導電膜(例如多晶矽膜)。
之後，如圖39所示，將導電膜GE及氧化膜OX3(圖39)圖案化。藉此，形成閘極電極GE1、GE2及閘極絕緣膜GI2。接著，於數位區域DGR形成LDD區域LD2及LDS區域LS2。然後，於基板SUB上形成作為側壁SW1、SW2之絕緣膜。之後，蝕刻此絕緣膜。藉此，可形成側壁SW1、SW2。然後，形成汲極區域DR1及源極區域SR1以及汲極區域DR2及源極區域SR2。接著，於基板SUB上形成絕緣層IL。之後，將接點CT1、CT2埋置於絕緣層IL。如此進行，可製造圖27所示之半導體裝置。
在本實施形態，亦可獲得與第1實施形態相同之效果。
以上，依據實施形態，具體地說明了由本案發明人所作之發明，本發明不限於前述實施形態，可在不脫離其要旨之範圍進行各種變更是無須贅言的。

Claims (8)

  1. 一種半導體裝置，其包含有: 基板; 第1電晶體，具有閘極絕緣膜及閘極電極，汲極及源極以俯視觀之隔著該閘極絕緣膜相互對向; 第1雜質區域，形成於該基板且作為該汲極及該源極其中一者; 第1凹部，形成於該基板且位於該閘極絕緣膜與該第1雜質區域之間; 第1絕緣膜，埋置於該第1凹部;及 第2凹部，在該閘極絕緣膜側形成於該第1絕緣膜; 又，在該第1凹部之該閘極絕緣膜側，以該第1凹部之內側面及該基板的表面形成之第1角呈圓形。
  2. 如申請專利範圍第1項之半導體裝置，其包含有: 第2雜質區域，形成於該基板且作為該汲極及該源極另一者; 第3凹部，形成於該基板且位於該閘極絕緣膜與該第2雜質區域之間; 第2絕緣膜，埋置於該第3凹部;及 第4凹部，在該閘極絕緣膜側形成於該第2絕緣膜; 又，在該第3凹部之該閘極絕緣膜側，以該第3凹部之內側面及該基板的表面形成之第2角呈圓形。
  3. 如申請專利範圍第1項之半導體裝置，其包含有 : 第2電晶體，其具有閘極絕緣膜及閘極電極，汲極及源極以俯視觀之隔著該閘極絕緣膜彼此對向， 該第1電晶體構成電源電位為第1電壓之第1電路，該第2電晶體構成電源電位為低於該第1電壓之第2電壓的第2電路，該第1電晶體之該閘極絕緣膜比該第2電晶體之該閘極絕緣膜厚。
  4. 如申請專利範圍第3項之半導體裝置，其包含有: 第5凹部，其形成於該基板且以俯視觀之包圍該第2電晶體;及 第3絕緣膜，其埋置於該第5凹部; 又，該第3絕緣膜之上面位於該第2凹部的底面之上方。
  5. 一種半導裝置之製造方法，其包含下列步驟: (1)於基板上形成第1絕緣膜; (2)於該第1絕緣膜形成開口; (3)於形成該開口後，將該第1絕緣膜作為遮罩來蝕刻該基板，藉此，於該基板形成第1凹部; (4)將第2絕緣膜埋置於該第1凹部及該開口; (5)藉蝕刻該第2絕緣膜，而使該第2絕緣膜之上面位於該開口的上端之下方; (6)藉於蝕刻該第2絕緣膜後，將絕緣膜形成於該第1絕緣膜上及第2絕緣膜上，而形成與該開口重疊之區域具有第2凹部的第3絕緣膜; (7)以遮罩膜覆蓋「以俯視觀之，內側包含該第2凹部之一部份的第1區域」，且不以該遮罩膜覆蓋「以俯視觀之，內側包含該第2凹部之剩餘部份的第2區域」; (8)藉將該遮罩膜作為遮罩來蝕刻該第1絕緣膜、該第2絕緣膜及該第3絕緣膜，而在該第2區域中去除該第1絕緣膜及該第3絕緣膜，並且在該第2區域中，使該第2絕緣膜之上面位於該第1凹部的上端之下方; (9)去除該遮罩膜; (10)去除該遮罩膜後，在該第1區域仍殘留該第3絕緣膜之狀態下，在該第2區域於該基板形成氧化膜。
  6. 如申請專利範圍第5項之半導體裝置之製造方法，其中， 該第1絕緣膜為氮化矽膜，該第2絕緣膜為氧化矽膜，該第3絕緣膜為氮化矽膜。
  7. 一種半導體裝置之製造方法，其包含下列步驟: (1)於基板上形成第1絕緣膜; (2)於該第1絕緣膜形成開口; (3)於形成該開口後，將該第1絕緣膜作為遮罩來蝕刻該基板，藉此，於該基板形成第1凹部; (4)將第2絕緣膜埋置於該第1凹部及該開口; (5)藉蝕刻該第2絕緣膜，而使該第2絕緣膜之上面位於該第1凹部的上端之下方; (6)蝕刻該第2絕緣膜後，去除該第1絕緣膜 (7)藉於去除該第1絕緣膜後，將絕緣膜形成於該基板上及該第2絕緣膜上，而形成與該第1凹部重疊之區域具有第2凹部的第3絕緣膜; (8)以遮罩膜覆蓋「以俯視觀之，內側包含該第2凹部之一部份的第1區域」，且不以該遮罩膜覆蓋「以俯視觀之，內側包含該第2凹部之剩餘部份的第2區域」; (9)藉將該遮罩膜作為遮罩來蝕刻該第2絕緣膜及該第3絕緣膜，而在該第2區域中去除該第3絕緣膜，並且在該第2區域中，使該第2絕緣膜之上面位於該第1凹部的上端之下方; (10)去除該遮罩膜; (11)去除該遮罩膜後，在該第1區域仍殘留該第3絕緣膜之狀態下，在該第2區域於該基板形成氧化膜。
  8. 如申請專利範圍第7項之半導體裝置的製造方法，其中， 該第1絕緣膜為氮化矽膜，該第2絕緣膜為氧化矽膜，該第3絕緣膜為氮化矽膜。
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090166736A1 (en) * 2007-12-28 2009-07-02 Il-Yong Park Lateral double difused metal oxide semiconductor transistor and method for manufacturing the same
US20090273029A1 (en) * 2008-05-02 2009-11-05 William Wei-Yuan Tien High Voltage LDMOS Transistor and Method

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000349164A (ja) * 1999-06-08 2000-12-15 Nec Corp 素子分離絶縁膜を有する半導体装置の製造方法
US6900101B2 (en) * 2003-06-13 2005-05-31 Texas Instruments Incorporated LDMOS transistors and methods for making the same
JP4158621B2 (ja) 2003-06-26 2008-10-01 沖電気工業株式会社 半導体装置の製造方法
JP4407794B2 (ja) * 2003-07-25 2010-02-03 セイコーエプソン株式会社 半導体装置の製造方法
JP2005116744A (ja) * 2003-10-07 2005-04-28 Seiko Epson Corp 半導体装置およびその製造方法
JP4707947B2 (ja) * 2003-11-14 2011-06-22 ルネサスエレクトロニクス株式会社 半導体装置
US7122876B2 (en) * 2004-08-11 2006-10-17 Taiwan Semiconductor Manufacturing Company, Ltd. Isolation-region configuration for integrated-circuit transistor
JP2006332404A (ja) * 2005-05-27 2006-12-07 Seiko Epson Corp 半導体装置の製造方法及び半導体装置
JP2008124172A (ja) * 2006-11-10 2008-05-29 Fujitsu Ltd 半導体装置及びその製造方法
JP5385679B2 (ja) * 2008-05-16 2014-01-08 旭化成エレクトロニクス株式会社 横方向半導体デバイスおよびその製造方法
JP5492610B2 (ja) * 2010-03-11 2014-05-14 パナソニック株式会社 半導体装置及びその製造方法
JP2013098444A (ja) * 2011-11-02 2013-05-20 Sharp Corp 半導体装置およびその製造方法
US9362272B2 (en) * 2012-11-01 2016-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Lateral MOSFET
JP6189771B2 (ja) * 2014-03-03 2017-08-30 ルネサスエレクトロニクス株式会社 半導体装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090166736A1 (en) * 2007-12-28 2009-07-02 Il-Yong Park Lateral double difused metal oxide semiconductor transistor and method for manufacturing the same
US20090273029A1 (en) * 2008-05-02 2009-11-05 William Wei-Yuan Tien High Voltage LDMOS Transistor and Method

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