TWI612593B - 半導體裝置之製造方法及半導體製造裝置 - Google Patents

半導體裝置之製造方法及半導體製造裝置 Download PDF

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TWI612593B
TWI612593B TW104107090A TW104107090A TWI612593B TW I612593 B TWI612593 B TW I612593B TW 104107090 A TW104107090 A TW 104107090A TW 104107090 A TW104107090 A TW 104107090A TW I612593 B TWI612593 B TW I612593B
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semiconductor wafer
semiconductor
manufacturing
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TW201612995A (en
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深山真哉
尾山幸史
村上和博
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東芝股份有限公司
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Description

半導體裝置之製造方法及半導體製造裝置
[關聯申請案]
本申請案享有以日本專利申請案2014-187676號(申請日：2014年9月16日)為基礎申請案之優先權。本申請案藉由參照該基礎申請案而包含基礎申請案之全部內容。
本發明之實施形態係關於一種半導體裝置之製造方法及半導體製造裝置。
為實現半導體裝置之小型化或高功能化等，而將複數個半導體晶片積層於1個封裝內並加以密封之半導體裝置正在實用化。
於此種半導體裝置中，要求於半導體晶片間高速地發送及接收電氣信號。此種情形時，於半導體晶片間之電性連接使用微凸塊。於將形成有微凸塊之半導體晶片積層多段之情形時，於利用相機識別形成於半導體晶片上之對準標記之後，將凸塊彼此位置對準，並且一面施加熱及超音波等一面將上下之半導體晶片壓接而連接。
此時，存在如下情形，即，對準標記座標之設計值與相機識別並獲取之對準標記座標之值產生偏差，從而位置偏移量變大。
本發明之實施形態減少積層晶片間之位置偏移量。
實施形態之半導體裝置之製造方法包括：獲取第1半導體晶片之位置之步驟；及將第2半導體晶片安裝於上述第1半導體晶片上之步 驟。該半導體裝置之製造方法更包括：獲取上述第2半導體晶片之位置之步驟；計算上述第1半導體晶片之位置、與上述第2半導體晶片之位置之偏移量即第1偏移量之步驟；及進行上述第1偏移量是否為第1範圍內之第1判定之步驟。
10‧‧‧載台
12‧‧‧第1半導體晶片
14‧‧‧凸塊
140‧‧‧凸塊
16‧‧‧相機
16a‧‧‧透鏡
16b‧‧‧透鏡
18‧‧‧頭部
20‧‧‧第2半導體晶片
22‧‧‧凸塊
24‧‧‧凸塊
26‧‧‧第3半導體晶片
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50‧‧‧對準標記
52‧‧‧對準標記
54‧‧‧對準標記
56‧‧‧對準標記
50a‧‧‧對準座標
50b‧‧‧對準座標
52a‧‧‧對準座標
52b‧‧‧對準座標
54a‧‧‧對準座標
54b‧‧‧對準座標
50c‧‧‧中心座標
52c‧‧‧中心座標
54c‧‧‧中心座標
100‧‧‧半導體製造裝置
110‧‧‧半導體裝置
120‧‧‧導體晶片
121‧‧‧半導體晶片
122‧‧‧半導體晶片
123‧‧‧半導體晶片
124‧‧‧半導體晶片
L1、L2‧‧‧線段
S101~S221‧‧‧步驟
圖1係自橫方向觀察第1實施形態之半導體裝置之製造方法之中途步驟的半導體製造裝置之狀態之圖之一例。
圖2係自橫方向觀察第1實施形態之半導體裝置之製造方法之中途步驟的半導體製造裝置之狀態之圖之一例。
圖3係自橫方向觀察第1實施形態之半導體裝置之製造方法之中途步驟的半導體製造裝置之狀態之圖之一例。
圖4係自橫方向觀察第1實施形態之半導體裝置之製造方法之中途步驟的半導體製造裝置之狀態之圖之一例。
圖5係自上方觀察第1半導體晶片及安裝於其上之第2半導體晶片之狀態的俯視圖之一例。
圖6係表示第1實施形態之半導體裝置之製造方法之順序的流程圖之一例。
圖7係表示半導體裝置之構成之立體圖之一例。
圖8係表示第2實施形態之半導體裝置之製造方法之順序的流程圖之一例。
以下，一面參照圖式一面對實施形態進行說明。再者，圖式係模式性圖式，厚度與平面尺寸之關係、各層之厚度之比率等未必一定與實際情形一致。即便於表示相同部分之情形時，亦有相互之尺寸或比率根據圖式而不同地表示之情形。又，關於上下左右之方向，亦表示將半導體基板之電路形成面側、或半導體製造裝置中載台之半導體 基板載置側作為上之情形之相對性的方向，未必一定限於與以重力加速度方向為基準之情形一致。本案說明書與各圖中，對與於已說明之圖中敍述之要素相同之要素標相同之符號，並適當省略詳細之說明。
(第1實施形態)
以下，參照圖1~圖7對第1實施形態進行說明。圖1~圖4係自橫方向觀察第1實施形態之半導體裝置之製造方法之中途步驟的半導體製造裝置100之狀態的之一例。圖5係自上方觀察第1半導體晶片12及安裝於其上之第2半導體晶片20之狀態的俯視圖之一例，其係模式性地表示第1半導體晶片12與第2半導體晶片20之安裝後之位置偏移狀況的圖之一例。圖6係表示第1實施形態之半導體裝置之製造方法之順序的流程圖之一例。圖7係表示半導體裝置110之構成之立體圖之一例。
首先，於本實施形態之半導體裝置之製造方法中，於安裝開始時，如圖1所示，將第1半導體晶片12以吸附保持於半導體製造裝置100之載台10上之狀態載置。於第1半導體晶片12之上表面形成有對準標記50及凸塊14。
其次，半導體製造裝置100進行接收第2半導體晶片20(步驟101)。第2半導體晶片20以凸塊22形成面為下側而藉由頭部18吸附保持。於第2半導體晶片20之下表面預先形成有對準標記52及凸塊22。
第1半導體晶片12與第2半導體晶片20以凸塊14及凸塊22相互相向之方式被保持，且於其等間配置有相機16。相機16包含透鏡16a、16b，且配置為可經由透鏡16a、16b而拍攝對準標記50及52。半導體製造裝置100可利用相機16拍攝對準標記，並特定出晶片之對準座標。載台10、頭部18及相機16為本實施形態之半導體製造裝置100之一部分。又，半導體製造裝置100包含記憶座標資料等之記憶體部、及進行使用座標資料之計算及載台10、頭部18、相機16等之控制等之CPU(central processing unit，中央處理單元)部(運算部、控制部)等。
此處，半導體製造裝置100利用相機16而識別、獲取第1半導體晶片12之對準標記50之對準座標50a、50b，且記憶座標資料(步驟102)。對準標記50於第1半導體晶片12上例如設置有兩個。將對準座標50a設為(X1a，Y1a)，且將對準座標50b設為(X1b，Y1b)。對準座標50a、50b係作為「基準對準座標」而加以記憶。此處，所謂基準對準座標係指例如於安裝第2半導體晶片20時成為用於位置對準之基準的第1半導體晶片12上之座標。於安裝時，將下述之搭載晶片之對準座標位置對準於「基準對準座標」。此處，如圖5所示，使用配置於半導體晶片之右上、左下之角部之例，但並不限定於該位置，可配置於任意之位置
其次，使用該座標而計算對準座標之中心座標(步驟103)。將中心座標50c設為(X1，Y1)。該第1半導體晶片12之中心座標50c作為「基準座標」而加以記憶。基準座標成為用於計算下述之偏移量等之基準點。此處，X1=(X1a+X1b)/2，Y1=(Y1a+Y1b)/2。即，中心座標50c係連結對準座標50a與50b之線段L1之中點。再者，此處，表示使用對準座標之中心座標作為基準座標之例，但並不限定於此。亦可於任意之位置設置基準點(基準座標)，並以該座標為基準而計算偏移量。又，基準座標亦可為複數個點。
其次，半導體製造裝置100利用相機16而識別、獲取第2半導體晶片20之對準標記52之對準座標52a、52b(步驟104)。對準標記52於第2半導體晶片20之下側之表面上例如設置有兩個，將其中一者設為對準座標52a，且將另一者設為對準座標52b。將對準座標52a設為(X2a，Y2a)，且將對準座標52b設為(X2b，Y2b)。
其次，半導體製造裝置100使用該等對準座標而控制裝置，將設置於第1半導體晶片12之上表面之凸塊14、與設置於第2半導體晶片20之下表面之凸塊22進行位置對準之後，對第2半導體晶片20施加熱或 超音波而進行壓接。藉此，如圖2所示，將凸塊14與凸塊22連接而進行安裝(步驟105)。
繼而，半導體製造裝置100確認積層段數(步驟106)。於積層段數未達預定之積層段數之情形時，半導體製造裝置100如圖3所示，頭部18接收下一要安裝之第3半導體晶片26(步驟107)。
其次，半導體製造裝置100利用相機16而識別、獲取設置於第2半導體晶片20之上表面之對準標記54之對準座標54a、54b，且記憶座標資料(步驟108)。對準標記54於第2半導體晶片20之上表面(圖之Z方向之上表面)例如設置有兩個，將其中一者設為對準座標54a，且將另一者設為對準座標54b。將對準座標54a設為(X2a，Y2a)，且將對準座標54b設為(X2b，Y2b)。半導體製造裝置100將對準座標54a、54b作為「搭載對準座標」而加以記憶。搭載對準座標係安裝晶片上之對準座標。
其次，半導體製造裝置100使用該座標而計算晶片之中心座標(步驟109)。將中心座標54c設為(X2，Y2)。該第2半導體晶片20之中心座標54c係作為「搭載座標」而加以記憶。搭載座標用於計算下述之偏移量等。此處，搭載座標X2=(X2a+X2b)/2，Y2=(Y2a+Y2b)/2。中心座標54c係連結對準座標54a與54b之線段L2之中點。該等座標係安裝且固定於第1半導體晶片12上之後的第2半導體晶片20之座標。因此，於施加熱或超音波時有可能產生偏移。即，有可能與之前獲取之對準座標產生偏差。
其次，如圖3所示，半導體製造裝置100利用相機16而識別、獲取第3半導體晶片26之對準標記56之對準座標56a、56b(步驟110)。對準標記56於第3半導體晶片26之下側表面上例如設置有兩個，將其中一者設為對準座標56a，且將另一者設為對準座標56b。此處，將對準座標56a設為(X3a，Y3a)，且將對準座標56b設為(X3b，Y3b)。對準座 標56a、56b可配置於任意之位置。
繼而，半導體製造裝置100計算第1半導體晶片12之基準座標(X1，Y1)、與第2半導體晶片20之搭載座標(X2，Y2))之位置偏移量(X=X1-X2，Y=Y1-Y2)、及角度偏移量θ(步驟111)。藉此，可獲得偏移量(X，Y，θ)。
其次，半導體製造裝置100進行偏移量是否為規格範圍內之判定(步驟112)。於偏移量為規格範圍外之情形時，半導體製造裝置100發出警報(步驟113)。此處，規格範圍可設為例如有可能於凸塊14與凸塊22之間產生連接不良之範圍。於偏移量為規格範圍外之情形時，有可能於第1半導體晶片12與第2半導體晶片20之間成為連接不良。如此，針對安裝之每一段而計算由安裝所致之偏移量，藉此可於偏移量為規格範圍外之情形時發出警報。藉此，不會浪費其後之安裝晶片，從而可降低成本。
又，亦可於以發出警報為契機而暫時確認凸塊之連接狀態後，進行是否繼續半導體晶片之安裝之判斷。於發出警報中，可採用例如於適當之顯示器顯示已產生誤差等之方法、或利用鳴響警報音等通知已產生誤差等之方法。藉此，於在安裝之中途階段之半導體晶片之安裝中產生不良之可能性較高的情形時，不會繼續其後之安裝，因而可削減成本。此處，由於不會浪費第3半導體晶片26以後之半導體晶片，因而可削減成本。
另一方面，於偏移量為規格範圍內之情形時，半導體製造裝置100將第2半導體晶片20之搭載對準座標覆寫(代入)為新的基準對準座標之座標資料(步驟114)。即，將對準座標54a(X2a，Y2a)、54b(X2b，Y2b)覆寫於對準座標50a(X1a，Y1a)、50b(X1b，Y1b)，而將對準座標54a(X2a，Y2a)、54b(X2b，Y2b)設為新的基準對準座標。
或者，亦可將第2半導體晶片20之對準標記54之中心座標54c(搭 載座標)覆寫(代入)為基準座標。即，亦可將中心座標54c(X2，Y2)覆寫於中心座標50c(X1，Y1)。
其次，半導體製造裝置100以使於步驟110中識別、獲取之第3半導體晶片26之對準座標56a、56b與基準對準座標54a、54b位置對準的方式控制裝置，將設置於第2半導體晶片20之上表面之凸塊24、與設置於第3半導體晶片26之下側之凸塊28進行位置對準。其後，對第2半導體晶片20施加熱或超音波而將凸塊24與凸塊28壓接。藉此，如圖4所示，將凸塊24與凸塊28連接而進行第3半導體晶片26之安裝(步驟115)。藉此，將第3半導體晶片26安裝於第2半導體晶片20上。再者，此時，存在藉由施加之熱或超音波而使第3半導體晶片26之位置產生偏移之情形。
其次，確認積層段數(步驟106)。於積層段數未達預定之積層段數之情形時，如圖3所示，頭部18接收下一要安裝之半導體晶片(步驟107)。其後，反覆執行自步驟107經過步驟115而至步驟106之流程直至安裝之半導體晶片成為預定之積層段數為止。
繼而，於步驟106中，於安裝之半導體晶片成為預定之積層段數，從而指定積層段之安裝結束之情形時，獲取設置於最上半導體晶片(以下稱為最上段晶片)之上表面之對準標記的對準座標(步驟116)。
其次，計算最上段晶片與下一段半導體晶片(以下稱為下段晶片)之對準座標之偏移量(步驟117)。再者，於步驟108中獲取、記憶下段晶片之對準座標(即基準對準座標)，且於步驟109計算其基準座標。
其次，進行偏移量是否為規格範圍內之判定(步驟118)。於偏移量為規格範圍外之情形時，發出警報(步驟119)。發出警報之實施可採用例如於適當之顯示器顯示已產生誤差等之方法、或利用警報音等通知已產生誤差等之方法。藉由發出警報而可顯示最上段晶片與下段晶片之偏移量較大，從而有可能成為連接不良。另一方面，於偏移量 為規格範圍內之情形時結束安裝。
經過以上步驟而可製造第1實施形態之半導體裝置110。本實施形態之半導體製造裝置100藉由對載台10、頭部18、及相機16實施上述之控制而可製造本實施形態之半導體裝置。
圖7係表示藉由本實施形態而製造之半導體裝置110之構成的立體圖之一例。如圖7所示，將半導體晶片121、122、123、124於Z方向積層而安裝。於最上段之半導體晶片124上形成有凸塊140。於凸塊140之下方，未圖示之金屬電極於Z方向延伸，且貫通半導體晶片121、122、123、124而形成。該金屬電極將半導體晶片間相互電性連接。再者，圖7中圖示安裝有4片半導體晶片之例，但並不限定於此，安裝片數可任意設定。再者，下述之第2實施形態之半導體裝置110亦具有相同之構成。
第1實施形態中，於步驟109之後執行識別、獲取第3半導體晶片26之對準標記56之對準座標56a、56b的步驟110，但其亦可於其他位置實施該步驟110。步驟110只要於進行第3半導體晶片26之安裝之步驟115之前實施即可，例如，亦可於步驟114之後實施。步驟110亦可與步驟108之第2半導體晶片20之對準座標之獲取同時執行。於相機16例如於上下包含透鏡16a、16b之情形時，如此可縮短製程時間。又，第3半導體晶片26之接收(步驟107)未必一定緊隨步驟106之後執行，只要為第3半導體晶片26之對準座標獲取(步驟110)之前，則亦可於自步驟107至115為止之任一位置執行。
以上，如所說明般，根據本實施形態，於安裝半導體晶片之每一安裝步驟，自兩個下半導體晶片之中心座標(基準座標)、與一個下半導體晶片之中心座標(搭載座標)而計算安裝晶片之位置偏移量(X，Y，θ)。其次，判定偏移量是否為規格範圍內，於偏移量為規格範圍外之情形時，則於此停止安裝步驟，不執行下一半導體晶片之安裝而 發出警報。藉此，於在安裝之中途階段有可能產生不良之情形時檢測出此，使其後之安裝停止，從而不會繼續安裝。因此，不會浪費地安裝半導體晶片，從而可削減成本。即，可預防製作位置偏移為規格以上之半導體裝置。
(第2實施形態)
其次，一面參照圖1~5、圖7、及圖8一面對第2實施形態進行說明。本實施形態之半導體裝置之製造方法之中途步驟的狀態、及第2實施形態之半導體裝置110之構成與第1實施形態相同，且顯示於圖1~圖4、及圖5中。安裝後之半導體裝置110之構成(立體圖)與如上所述之圖7所示之構成相同。
圖8係表示第2實施形態之半導體裝置之製造方法之順序的流程圖之一例。首先，於本實施形態之半導體裝置之製造方法中，自步驟201至步驟211與第1實施形態之自步驟101至步驟111相同。
第2實施形態中，於執行自步驟201至步驟211之後，判定偏移量是否為誤差規格範圍內(步驟212)。於偏移量為誤差規格範圍外之情形時發出警報(步驟213)。誤差規格範圍可設為例如於凸塊14與凸塊22之間有可能產生連接不良之範圍。於此種情形時，有可能於第1半導體晶片12與第2半導體晶片20之間成為連接不良。
於發出警報中，可採用例如於適當之顯示器顯示已產生誤差等之方法、或利用鳴響警報音等通知已產生誤差等之方法。於安裝之每一段計算由安裝所致之偏移量，藉此可於產生偏移量為規格範圍外之安裝段之情形時發出警報。藉此，不會繼續其後之安裝，因而不會浪費其後之安裝晶片，從而可削減成本。此處，由於不會浪費第3半導體晶片26之後之半導體晶片，因此可削減其後安裝預定之半導體晶片、或安裝完成後之密封步驟等之成本。
另一方面，於偏移量為誤差規格範圍內之情形時，判定偏移量 是否為修正規格範圍內(步驟214)。
於偏移量為修正規格範圍外之情形時，藉由於步驟210中計算之位置偏移量(X，Y)而修正於步驟208中獲取之搭載對準座標(第2半導體晶片20之對準座標)之座標資料(步驟215)。即，將修正量(-X，-Y)加上搭載對準座標之座標資料(即減去偏移量)。其次，將修正後之搭載對準座標之座標資料覆寫於基準對準座標之座標資料，且將此作為新的基準對準座標之座標資料(步驟216)。
另一方面，於步驟214中，於偏移量為修正規格範圍內之情形時，將第2半導體晶片20之對準座標(搭載對準座標)之座標資料覆寫於基準對準座標之座標資料，且將此作為新的基準對準座標之座標資料(步驟216)。即，將第2半導體晶片20之搭載對準座標54a(X2a，Y2a)、54b(X2b，Y2b)覆寫(代入)於第1半導體晶片12之基準對準座標50a(X1a，Y1a)、50b(X1b，Y1b)，且將此作為新的基準對準座標之座標資料。
或者，亦可代替上述方法而將第2半導體晶片20之搭載座標作為基準座標而覆寫。即，將第2半導體晶片20之搭載座標54c(X2，Y2)覆寫(代入)於基準座標50c(X1，Y1)，且將此作為新的基準座標。
其次，以使於步驟210中識別、獲取之第3半導體晶片26之對準座標56a、56b與基準對準座標54a、54b位置對準的方式控制裝置，使設置於第2半導體晶片20之上表面之凸塊24、與設置於第3半導體晶片26之下側之凸塊28位置對準。其後，對第2半導體晶片20施加熱或超音波而將凸塊24與凸塊28壓接。藉此，如圖4所示，將凸塊24與凸塊28連接而執行第3半導體晶片26之安裝(步驟217)。藉此，將第3半導體晶片26安裝於第2半導體晶片20上。再者，此時，有藉由施加之熱或超音波而使第3半導體晶片26位置產生偏移之情形。
其次，確認積層段數(步驟206)。於積層段數未達預定之積層段 數之情形時，如圖3所示，頭部18接收下一要安裝之半導體晶片(步驟207)。其後，反覆執行自步驟207經過步驟217而至步驟206為止之流程直至安裝之半導體晶片成為預定之積層段數為止。
繼而，於步驟206中，於安裝之半導體晶片成為預定之積層段數，從而完成指定積層段數之安裝之情形時，獲取設置於最上半導體晶片(以下稱為最上段晶片)之上表面之對準標記的對準座標(步驟218)。其後，自步驟218至步驟221與第1實施形態之自步驟116至步驟119相同，因而省略說明。
經過以上步驟而可製造第2實施形態之半導體裝置110。本實施形態之半導體製造裝置100藉由對載台10、頭部18、相機16實施上述控制而可製造本實施形態之半導體裝置。
如以上所說明般，根據第2實施形態之半導體裝置之製造方法，具有與第1實施形態相同之效果。又，於為誤差規格範圍內且修正規格範圍外之偏移量之情形時，可藉由於步驟210中計算之偏移量(X，Y，θ)而修正搭載對準座標。藉此，可減少位置偏移量，進而可減少連接不良。
(其他實施形態)
上述說明之實施形態可應用於各種半導體裝置。例如，亦可應用於NAND(Not AND，與非)型或NOR(Not OR，或非)型之快閃記憶體、EPROM(Erasable Programmable Read Only Memory，可抹除可程式化唯讀記憶體)、或DRAM(Dynamic Random Access Memory，動態隨機存取記憶體)、SRAM(Static Random Access Memory，靜態隨機存取記憶體)及其他半導體記憶裝置、或各種邏輯裝置、及其他半導體裝置。
如上所述，對本發明之若干個實施形態進行了說明，但該等實施形態係作為示例而提出者，並未意圖限定發明之範圍。該等新穎之 實施形態能以其他各種形態而實施，且可於不脫離發明之要旨之範圍進行各種省略、置換、變更。該等實施形態或其之變化包含於發明之範圍或要旨，並且包含於申請專利範圍中記載之發明及其均等之範圍。
S101~S119‧‧‧步驟

Claims (15)

  1. 一種半導體裝置之製造方法，其包括：使用形成於第1半導體晶片之一個以上之第1對準標記，判定包含複數個第1電極之上述第1半導體晶片之位置；使用形成於第2半導體晶片之一個以上之第2對準標記，判定包含複數個第2電極之上述第2半導體晶片之位置；根據上述第1及第2半導體晶片之經上述判定之位置，以使上述第2電極對準上述第1電極之方式，相對於上述第1半導體晶片而移動上述第2半導體晶片；在上述移動後，以使上述第1電極電性連接於上述第2電極之方式，將上述第2半導體晶片堆疊(stacking)於上述第1半導體晶片上；在上述堆疊後，使用一個以上之第3對準標記，判定上述第2半導體晶片之上述堆疊後之位置，上述第3對準標記係形成於上述第2半導體晶片之與形成有上述一個以上之第2對準標記之面相反之面；及由控制部根據上述第1半導體晶片之上述堆疊前之位置及上述堆疊後之上述第2半導體晶片之上述堆疊後之位置，計算上述第1半導體晶片與堆疊於其上之上述第2半導體晶片之間之偏移量(misalignment amount)。
  2. 如請求項1之半導體裝置之製造方法，其中上述第1半導體晶片之位置係：於上述第1半導體晶片經以使上述第1電極面向上述第2半導體晶片之方式而配置於載台上時，進行判定；及上述第2半導體晶片之位置係：於上述第2半導體晶片被保持 在保持具(holder)且相對於上述第1半導體晶片而經移動時，進行判定。
  3. 如請求項1之半導體裝置之製造方法，其中上述第1半導體晶片之位置係：根據包括上述一個以上之第1對準標記之上述第1半導體晶片之圖像，而進行判定；且上述第2半導體晶片之位置係：根據包括上述一個以上之第2對準標記之上述第2半導體晶片之圖像，而進行判定。
  4. 如請求項1之半導體裝置之製造方法，其更包括：判定上述偏移量是否為預定範圍內。
  5. 如請求項4之半導體裝置之製造方法，其更包括：上述偏移量被判定為上述預定範圍內時，將第3半導體晶片堆疊於上述第2半導體晶片上。
  6. 如請求項5之半導體裝置之製造方法，其更包括：計算上述第2半導體晶片與堆疊於其上之上述第3半導體晶片之間之偏移量。
  7. 如請求項5之半導體裝置之製造方法，其更包括：上述偏移量被判定為上述預定範圍內時，使用形成於上述第3半導體晶片之一個以上之第4對準標記，判定上述第3半導體晶片之位置；根據上述第2及第3半導體晶片之經上述判定之位置，以使形成於第3半導體晶片之第3電極與形成於上述第2半導體晶片之第4電極對準之方式，相對於上述第2半導體晶片而移動上述第3半導體晶片；其中上述第3半導體晶片之上述堆疊係於移動上述第3半導體晶片後進行，而使得上述第3電極電性連接於上述第4電極。
  8. 如請求項7之半導體裝置之製造方法，其中 上述第3半導體晶片移動至如下位置：上述第2及第3半導體晶片之間之上述偏移量可補償(offset)上述第1及第2半導體晶片之間之上述偏移量。
  9. 如請求項7之半導體裝置之製造方法，其中上述第3半導體晶片係移動至上述第1與第3半導體晶片之間的無偏移量之位置。
  10. 如請求項1之半導體裝置之製造方法，其中上述第1及第2電極係導電凸塊。
  11. 一種半導體製造裝置，其包含：載台，其可載置第1半導體晶片；保持具，其構成為可保持要堆疊於被載置於上述載台上之上述第1半導體晶片上的第2半導體晶片；攝像部，其拍攝：上述第2半導體晶片堆疊於上述第1半導體晶片前的上述載台上之上述第1半導體晶片之第1圖像、及堆疊於上述第1半導體晶片前之位於保持具的上述第2半導體晶片之第2圖像，上述第1圖像包含形成於上述第1半導體晶片之一個以上之第1對準標記，上述第2圖像包含形成於上述第2半導體晶片之一個以上之第2對準標記；及控制部，其構成為：相對於上述載台而使上述保持具移動，以根據上述第1及第2圖像而將上述第2半導體晶片堆疊於上述第1半導體晶片上；使上述攝像部拍攝已堆疊於上述第1半導體晶片上之上述第2半導體晶片之第3圖像，其包含一個以上之第3對準標記，且上述第3對準標記形成於上述第2半導體晶片之與形成有上述一個以上之第2對準標記之面相反之面；及根據上述第1及第3圖像，計算上述第1半導體晶片與上述第 2半導體晶片之間之偏移量。
  12. 如請求項11之半導體製造裝置，其中上述控制部更構成為於上述偏移量被判定為大於預定範圍時，使產生警報。
  13. 如請求項11之半導體製造裝置，其中上述控制部更構成為於上述偏移量被判定為預定範圍內時，根據上述偏移量來計算用於第3半導體晶片之堆疊之修正值。
  14. 如請求項13之半導體製造裝置，其中上述控制部更構成為依據上述修正值，將用於堆疊在上述第2半導體晶片上之上述第3半導體晶片進行定位。
  15. 如請求項11之半導體製造裝置，其中上述控制部更構成為依據基於上述偏移量所計算之修正值，將用於堆疊在上述第2半導體晶片上之第3半導體晶片進行定位。
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US9448065B2 (en) 2016-09-20
CN105990205A (zh) 2016-10-05
CN105990205B (zh) 2019-05-21

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