WO2009022401A1 - 半導体素子の選別取得方法、半導体装置の製造方法及び半導体装置 - Google Patents

半導体素子の選別取得方法、半導体装置の製造方法及び半導体装置 Download PDF

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Publication number
WO2009022401A1
WO2009022401A1 PCT/JP2007/065784 JP2007065784W WO2009022401A1 WO 2009022401 A1 WO2009022401 A1 WO 2009022401A1 JP 2007065784 W JP2007065784 W JP 2007065784W WO 2009022401 A1 WO2009022401 A1 WO 2009022401A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor
semiconductor device
semiconductor element
sorting
acquiring
Prior art date
Application number
PCT/JP2007/065784
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English (en)
French (fr)
Inventor
Yoshito Konno
Yutaka Yamada
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Fujitsu Microelectronics Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Microelectronics Limited filed Critical Fujitsu Microelectronics Limited
Priority to JP2009527990A priority Critical patent/JP5126231B2/ja
Priority to PCT/JP2007/065784 priority patent/WO2009022401A1/ja
Priority to CN2007801000825A priority patent/CN101765910B/zh
Publication of WO2009022401A1 publication Critical patent/WO2009022401A1/ja
Priority to US12/690,198 priority patent/US8445906B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Dicing (AREA)

Abstract

　半導体基板（半導体ウエハ）に形成された複数個の半導体素子（半導体チップ）から、無欠陥（良品）の半導体素子を効率的にかつ確実にピックアップ可能な半導体素子の選別取得方法、半導体装置の製造方法及び半導体装置を提供することを目的とする。 　本発明の半導体素子の選別取得方法は、半導体基板の有効領域内に複数個の半導体素子を配設する工程と、前記半導体基板上で前記有効領域外に基準半導体素子を配設する工程と、前記複数個の半導体素子及び前記基準半導体素子にバンプを形成する工程と、前記有効領域内の前記複数個の半導体素子に対し試験を行う工程と、前記基準半導体素子を基点として、配置マップを作成する工程と、前記配置マップに基づき、前記複数の半導体素子の中から前記試験において良品と判定された半導体素子を摘出する工程とを含む。
PCT/JP2007/065784 2007-08-10 2007-08-10 半導体素子の選別取得方法、半導体装置の製造方法及び半導体装置 WO2009022401A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2009527990A JP5126231B2 (ja) 2007-08-10 2007-08-10 半導体素子の選別取得方法、半導体装置の製造方法及び半導体装置
PCT/JP2007/065784 WO2009022401A1 (ja) 2007-08-10 2007-08-10 半導体素子の選別取得方法、半導体装置の製造方法及び半導体装置
CN2007801000825A CN101765910B (zh) 2007-08-10 2007-08-10 半导体元件的选取方法、半导体器件及其制造方法
US12/690,198 US8445906B2 (en) 2007-08-10 2010-01-20 Method for sorting and acquiring semiconductor element, method for producing semiconductor device, and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/065784 WO2009022401A1 (ja) 2007-08-10 2007-08-10 半導体素子の選別取得方法、半導体装置の製造方法及び半導体装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/690,198 Continuation US8445906B2 (en) 2007-08-10 2010-01-20 Method for sorting and acquiring semiconductor element, method for producing semiconductor device, and semiconductor device

Publications (1)

Publication Number Publication Date
WO2009022401A1 true WO2009022401A1 (ja) 2009-02-19

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PCT/JP2007/065784 WO2009022401A1 (ja) 2007-08-10 2007-08-10 半導体素子の選別取得方法、半導体装置の製造方法及び半導体装置

Country Status (4)

Country Link
US (1) US8445906B2 (ja)
JP (1) JP5126231B2 (ja)
CN (1) CN101765910B (ja)
WO (1) WO2009022401A1 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011091286A (ja) * 2009-10-26 2011-05-06 Fujitsu Semiconductor Ltd 半導体装置の製造方法

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US8956954B2 (en) * 2012-02-21 2015-02-17 Chih-hao Chen Method of processing wafers for saving material and protecting environment
MY192745A (en) * 2014-05-23 2022-09-06 Cirrus Logic Inc Systems and methods for placement of singulated semiconductor devices for multi-site testing
JP6305887B2 (ja) * 2014-09-16 2018-04-04 東芝メモリ株式会社 半導体装置の製造方法及び半導体製造装置

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JP2001176892A (ja) * 1999-12-15 2001-06-29 Shinkawa Ltd ダイボンディング方法及びその装置
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JPS60246645A (ja) * 1984-05-22 1985-12-06 Tokyo Erekutoron Kk 半導体ウエハチツプの位置合わせ方法
JPH03196633A (ja) * 1989-12-26 1991-08-28 Fuji Electric Co Ltd 半導体集積回路装置及び半導体ウエハ
JPH05121496A (ja) * 1991-10-25 1993-05-18 Nec Corp 不良チツプ除去方法
JP2000077487A (ja) * 1998-08-28 2000-03-14 Seiko Epson Corp ウエハプローバ
JP2001144197A (ja) * 1999-11-11 2001-05-25 Fujitsu Ltd 半導体装置、半導体装置の製造方法及び試験方法
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011091286A (ja) * 2009-10-26 2011-05-06 Fujitsu Semiconductor Ltd 半導体装置の製造方法
US8349624B2 (en) * 2009-10-26 2013-01-08 Fujitsu Semiconductor Limited Method for fabricating semiconductor device

Also Published As

Publication number Publication date
JP5126231B2 (ja) 2013-01-23
CN101765910A (zh) 2010-06-30
US8445906B2 (en) 2013-05-21
US20100117084A1 (en) 2010-05-13
CN101765910B (zh) 2013-01-02
JPWO2009022401A1 (ja) 2010-11-11

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