TWI598457B - 使用自組裝單層形成ald抑制層之方法 - Google Patents
使用自組裝單層形成ald抑制層之方法 Download PDFInfo
- Publication number
- TWI598457B TWI598457B TW105133783A TW105133783A TWI598457B TW I598457 B TWI598457 B TW I598457B TW 105133783 A TW105133783 A TW 105133783A TW 105133783 A TW105133783 A TW 105133783A TW I598457 B TWI598457 B TW I598457B
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- metal
- ald
- sam
- molecule
- Prior art date
Links
- 239000010410 layer Substances 0.000 title claims description 214
- 238000000034 method Methods 0.000 title claims description 108
- 239000002094 self assembled monolayer Substances 0.000 title claims description 92
- 239000013545 self-assembled monolayer Substances 0.000 title claims description 92
- 230000002401 inhibitory effect Effects 0.000 title 1
- 238000000231 atomic layer deposition Methods 0.000 claims description 122
- 229910052751 metal Inorganic materials 0.000 claims description 95
- 239000002184 metal Substances 0.000 claims description 95
- 229910044991 metal oxide Inorganic materials 0.000 claims description 57
- 150000004706 metal oxides Chemical class 0.000 claims description 57
- 239000000758 substrate Substances 0.000 claims description 48
- 239000010949 copper Substances 0.000 claims description 44
- 229910052802 copper Inorganic materials 0.000 claims description 37
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 33
- 230000008569 process Effects 0.000 claims description 29
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 claims description 27
- 230000001629 suppression Effects 0.000 claims description 21
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 claims description 15
- 239000005751 Copper oxide Substances 0.000 claims description 14
- 229910000431 copper oxide Inorganic materials 0.000 claims description 14
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 13
- 239000004065 semiconductor Substances 0.000 claims description 12
- 230000015572 biosynthetic process Effects 0.000 claims description 10
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- 229910052719 titanium Inorganic materials 0.000 claims description 6
- 229910052735 hafnium Inorganic materials 0.000 claims description 5
- 229910052742 iron Inorganic materials 0.000 claims description 5
- 229910052759 nickel Inorganic materials 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000012808 vapor phase Substances 0.000 claims description 5
- 229910052726 zirconium Inorganic materials 0.000 claims description 5
- 229910052725 zinc Inorganic materials 0.000 claims description 4
- 125000003396 thiol group Chemical class [H]S* 0.000 claims 4
- 239000007789 gas Substances 0.000 description 45
- 230000009467 reduction Effects 0.000 description 18
- 150000003573 thiols Chemical class 0.000 description 15
- 238000011065 in-situ storage Methods 0.000 description 10
- 238000006243 chemical reaction Methods 0.000 description 6
- 238000000151 deposition Methods 0.000 description 6
- QJAOYSPHSNGHNC-UHFFFAOYSA-N octadecane-1-thiol Chemical group CCCCCCCCCCCCCCCCCCS QJAOYSPHSNGHNC-UHFFFAOYSA-N 0.000 description 5
- 230000008021 deposition Effects 0.000 description 4
- 238000002474 experimental method Methods 0.000 description 4
- 230000005764 inhibitory process Effects 0.000 description 4
- XEEYBQQBJWHFJM-UHFFFAOYSA-N iron Substances [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 230000003111 delayed effect Effects 0.000 description 3
- 238000010926 purge Methods 0.000 description 3
- 229920006395 saturated elastomer Polymers 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- -1 alkyl decylamine Chemical compound 0.000 description 2
- 125000000217 alkyl group Chemical group 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical group [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- HQWPLXHWEZZGKY-UHFFFAOYSA-N diethylzinc Chemical compound CC[Zn]CC HQWPLXHWEZZGKY-UHFFFAOYSA-N 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 230000006911 nucleation Effects 0.000 description 2
- 238000010899 nucleation Methods 0.000 description 2
- 230000033116 oxidation-reduction process Effects 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 239000002243 precursor Substances 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000003595 spectral effect Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000011701 zinc Substances 0.000 description 2
- VRPSXSYEJSDFCW-UHFFFAOYSA-N CNC(C)C.NN Chemical compound CNC(C)C.NN VRPSXSYEJSDFCW-UHFFFAOYSA-N 0.000 description 1
- MHZGKXUYDGKKIU-UHFFFAOYSA-N Decylamine Chemical compound CCCCCCCCCCN MHZGKXUYDGKKIU-UHFFFAOYSA-N 0.000 description 1
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 1
- LSDPWZHWYPCBBB-UHFFFAOYSA-N Methanethiol Chemical group SC LSDPWZHWYPCBBB-UHFFFAOYSA-N 0.000 description 1
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- PDNPMLJCSBEXND-UHFFFAOYSA-N [Zr].CNC.[Zr] Chemical compound [Zr].CNC.[Zr] PDNPMLJCSBEXND-UHFFFAOYSA-N 0.000 description 1
- 150000003973 alkyl amines Chemical class 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- CETPSERCERDGAM-UHFFFAOYSA-N ceric oxide Chemical compound O=[Ce]=O CETPSERCERDGAM-UHFFFAOYSA-N 0.000 description 1
- 229910000422 cerium(IV) oxide Inorganic materials 0.000 description 1
- 238000012512 characterization method Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010924 continuous production Methods 0.000 description 1
- LBJNMUFDOHXDFG-UHFFFAOYSA-N copper;hydrate Chemical compound O.[Cu].[Cu] LBJNMUFDOHXDFG-UHFFFAOYSA-N 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- GMTCPFCMAHMEMT-UHFFFAOYSA-N n-decyldecan-1-amine Chemical compound CCCCCCCCCCNCCCCCCCCCC GMTCPFCMAHMEMT-UHFFFAOYSA-N 0.000 description 1
- 150000002898 organic sulfur compounds Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 125000003544 oxime group Chemical group 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000011946 reduction process Methods 0.000 description 1
- 238000004611 spectroscopical analysis Methods 0.000 description 1
- 229910052717 sulfur Inorganic materials 0.000 description 1
- 239000011593 sulfur Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/02—Pretreatment of the material to be coated
- C23C16/0272—Deposition of sub-layers, e.g. to promote the adhesion of the main coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
-
- C—CHEMISTRY; METALLURGY
- C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
- C22B—PRODUCTION AND REFINING OF METALS; PRETREATMENT OF RAW MATERIALS
- C22B15/00—Obtaining copper
-
- C—CHEMISTRY; METALLURGY
- C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
- C22B—PRODUCTION AND REFINING OF METALS; PRETREATMENT OF RAW MATERIALS
- C22B5/00—General methods of reducing to metals
- C22B5/02—Dry methods smelting of sulfides or formation of mattes
- C22B5/12—Dry methods smelting of sulfides or formation of mattes by gases
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/04—Coating on selected surface areas, e.g. using masks
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
- C23C16/45523—Pulsed gas flow or change of composition over time
- C23C16/45525—Atomic layer deposition [ALD]
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
- C23C16/45523—Pulsed gas flow or change of composition over time
- C23C16/45525—Atomic layer deposition [ALD]
- C23C16/45527—Atomic layer deposition [ALD] characterized by the ALD cycle, e.g. different flows or temperatures during half-reactions, unusual pulsing sequence, use of precursor mixtures or auxiliary reactants or activations
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/56—After-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
- H01L21/02304—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
Landscapes
- Chemical & Material Sciences (AREA)
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Organic Chemistry (AREA)
- Materials Engineering (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- General Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical Vapour Deposition (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
- Electrodes Of Semiconductors (AREA)
Description
本揭露係關於原子層沉積(ALD),且特定而言係關於一種使用自組裝單層(SAM)形成ALD抑制層之方法。
任何本文提及之出版物或專利文件之全部揭露係以引用方式併入本文中。
ALD係一種在極受控制之方式下在一基板上沉積一薄膜之方法。使用二或多種呈蒸氣形式之化學品(即「製程氣體」)控制該沉積製程且連續地及以自限制方式在該基板表面(諸如矽晶圓)上使其等反應。重覆該連續製程以一層接一層地建構該薄膜層,其中該等層係原子等級。
使用ALD以形成各式各樣之膜,諸如用於先進閘極及電容介電質之二元、三元及四元氧化物,以及用於互連阻障及電容電極之金屬基化合物。
該典型ALD製程將第一製程氣體引入該單一製程室內。在此環境中置放該基板持續短時間週期以將該表面暴露至第一製程氣體。一旦該基板表面經該第一製程氣體飽和後,將該第一製程氣體泵出該室。接著一惰性或清洗氣體流經該室。然後將第二製程氣體引入該室。該第二製程氣體與經該第一製程氣體飽和之該基板表面反應。在第二製程氣體流入該室內之前使該惰性或清洗氣體流經該室之目的係確保移除所有初始未反應之第一製程氣體。第二製程氣體與經第一製程氣體飽和之該基板表面反應。
一旦完成此第二反應製程,移除該第二製程氣體且再次以惰性或清洗氣體清洗該室。接著,將該第一製程氣體引入該室內並重覆全部反應順序直至獲得所需厚度之ALD膜。
在一類型之ALD製程中,該ALD膜覆蓋該基板之全部表面。然而,當形成一半導體裝置時,其通常較佳在界定3D半導體裝置結構之製程中在該基板之選擇區域形成ALD膜。儘管此可使用物理遮罩方法進行,諸如一光阻型遮罩,該等遮罩方法係製程密集且耗時的。
本文揭示之方法可用於在包括天然金屬氧化物(MOx
)之一金屬M層上形成一ALD抑制層。該方法包括使用包含一金屬Q之還原氣體進行天然金屬氧化物MOX
之原位還原,以形成M+MQy
Ox
形式之「金屬+金屬氧化物」層。接著將M+MQy
Ox
層暴露至呈蒸氣相之SAM分子以在該M+MQy
Ox
層上形成SAM層。一實例SAM分子係硫醇,其係含有碳接合巰基團之有機硫化合物。
本揭露之一態樣係一種在覆蓋有該金屬M之氧化物層(下文稱為「金屬氧化物層」)的金屬M上形成ALD抑制層之方法。該方法包括:a) 藉由將該金屬氧化物層暴露至包括一金屬Q之一還原氣體以還原該金屬氧化物層,以在該金屬M上形成M+MQx
Oy
層;及b) 將該M+MQx
Oy
層暴露至呈蒸氣相之自組裝單層(下文稱為「SAM」)分子,其中該SAM分子在該M+MQx
Oy
層上形成為ALD抑制之一SAM層。
本揭露之另一態樣係上述之方法,其中該金屬M係Cu、Ni、Fe或Co,及該金屬Q係Al、Hf、Zr、Si、Ti或Zn。
本揭露之另一態樣係上述方法,其中該SAM分子係硫醇分子。
本揭露之另一態樣係上述之方法,其中該金屬M係銅,該金屬氧化物層係由氧化銅製成,該還原氣體包含三甲基鋁(TMA),該SAM分子係硫醇分子,及M+MQx
Oy
層係Cu+CuAlO2
層。
本揭露之另一態樣係上述之方法,其中步驟a)係在120°C與250°C間之溫度下進行。
本揭露之另一態樣係上述方法,其中步驟a)及b)係在少於1托之真空條件下進行。
本揭露之另一態樣係上述方法,其中該金屬氧化物層具有範圍在1 nm至5 nm之厚度。
本揭露之另一態樣係上述方法,其中該ALD抑制層實質上抑制其上之ALD膜之形成持續至少100次ALD循環。
本揭露之另一態樣係上述方法,其中該ALD抑制層實質上抑制其上之ALD膜之形成持續至少150次ALD循環。
本揭露之另一態樣係上述方法,該方法進一步包含在一半導體基板上形成金屬M作為圖案化金屬層。
本揭露之另一態樣係上述方法,該金屬M係在一半導體基板之介電層上形成為一圖案。及該方法進一步包括進行選區ALD,其係藉由在該介電層及覆蓋該金屬M之SAM層上進行一ALD製程,藉以在該介電層上但不在SAM層上形成一ALD膜。
本揭露之另一態樣係上述方法,其中該介電層係氧化物層。
本揭露之另一態樣係上述方法,該方法進一步包括移除該SAM層。
本揭露之另一態樣係上述方法,其中進行步驟a)少於720秒。
本文揭示之方法使得可藉由例如在一半導體裝置之金屬電極上選擇性形成該ALD抑制層以進行選區ALD(S-ALD)。該等方法減少在製造積體電路期間所需之加工步驟數,因其減少通常與習知S-ALD方法相關之微影、蝕刻及沉積步驟數的需要。
本揭露之一態樣係一種進行選區原子層沉積(以下稱為「S-ALD」)之方法。該方法包括a)在由半導體基板支撐之一介電層上界定一金屬M層(下文稱為「金屬層」),其中該金屬層界定一圖案,且其中該金屬層係由一層該金屬M之氧化物(下文稱為「金屬氧化物層」)覆蓋;b) 藉由將該金屬氧化物層暴露至包括金屬Q之一還原氣體還原該金屬氧化物層以在該金屬層上形成M+MQx
Oy
層;c) 將M+MQx
Oy
層與介電層暴露至呈蒸氣相之自組裝單層(SAM)分子,其中該SAM分子在該M+MQx
Oy
層上形成一SAM層以界定一ALD抑制層,及其中無SAM層在該介電層上形成;及d) 進行一ALD製程以沉積一ALD膜,其中該ALD膜在該介電層上但未在該SAM層上形成。
本揭露之另一態樣係上述之方法,其中該金屬M係Cu、Ni、Fe或Co,及該金屬Q係Al、Hf、Zr、Si、Ti或Zn。
本揭露之另一態樣係上述方法,該方法進一步包括移除該SAM層之步驟e)。
本揭露之另一態樣係上述方法,其中在720秒內進行步驟b)。
本揭露之另一態樣係上述方法,其中該SAM分子由硫醇分子組成。
本揭露之另一態樣係上述方法,其中該介電層包含SiO2
層。
本揭露之另一態樣係上述之方法,其中該金屬M係銅,該金屬氧化物層係由氧化銅製成,該還原氣體包含三甲基鋁(TMA),該SAM分子係硫醇分子,及M+MQx
Oy
層係Cu+CuAlO2
層。
本揭露之另一態樣係上述方法,其中該SAM層實質上抑制其上之ALD膜之形成持續至少100次ALD循環。
本揭露之另一態樣係上述方法,其中該SAM層實質上抑制其上之ALD膜之形成持續至少150次ALD循環。
本揭露之另一態樣係上述之方法,其中步驟b)係在120°C與250°C間之溫度下進行。
本揭露之另一態樣係上述方法,其中步驟b)及c)係在少於1托之真空條件下進行。
本揭露之另一態樣係上述方法,其中該金屬氧化物層具有範圍在1 nm至5 nm之厚度。
本揭露之另一態樣係上述方法,其中該還原氣體包含三甲基鋁(TMA)或烷基醯胺。
本揭露之另一態樣係上述方法,其中步驟b)、c)及d)係在單一ALD腔室中進行。
在以下實施方式中提出其它特徵及優點,且部份將由該實施方式為熟習本技術之人士所明顯得知,或藉由實行如在所寫描述及其申請專利範圍以及隨附圖式中所述之具體實施例識出。應了解先前之一般描述與之後之實施方式皆僅係說明性且意欲提供了解該等申請專利範圍之性質及特徵的綜述或架構。
現詳細參照本揭露之各種具體實施例,其實例在隨附圖式中說明。只要可能,相同或類似參照數字及符號在全部圖示中用來參照相同或類似部份。該等圖式不必按比例繪製,且熟習本技術者將認可其中該等圖式已經簡化以說明本揭露之主要態樣。
如以下提出之該等申請專利範圍併入且構成此實施方式之部份。
在某些圖式中顯示笛卡兒座標以供參照且未意欲限制方向或定向。
在以下討論中,「SAM層」意指一層自組裝分子,即一自組裝單層。
並且在以下討論中,術語「SAM分子」意指可形成具其它SAM分子之SAM層之分子。以下討論之SAM分子之實例係1-十八烷硫醇。
進行選區原子層沉積(S-ALD)之方法的實例現連同第1圖至4之截面圖描述。在第一步驟中,提供具上表面12之基板10。在一實例中,基板10係Si晶圓。基板10之上表面12係以金屬層20覆蓋,其係以天然金屬氧化物之層22(下文稱為「金屬氧化物層」)覆蓋。在一實例中,金屬層20之金屬係銅(Cu),而在金屬氧化物層22中之天然金屬氧化物係氧化銅(Cu2
O)。在此點,具金屬層20及金屬氧化物層22之基板10構成一金屬化基板10M。金屬層20之金屬在此稱為「M」。金屬氧化物層22之厚度可係極薄,例如在1 nm至5 nm範圍中之厚度。金屬M之實例係銅、鎳、鐵及鈷。
參照第2圖,在第二步驟中,第1圖之金屬化基板10M係置於ALD反應器系統之ALD腔室30之內部32。接著將ALD腔室30之內部32帶至真空條件(例如:壓力少於1托)且加熱金屬化基板10M至120˚C或高於120˚C(例如150˚C或170˚C或高至250˚C)之溫度。真空條件限制殘留氧量,其可導致更多量之金屬氧化物形成。增加之溫度有助於在如下述之後續步驟中之化學反應。
參照第3圖,在第三步驟中,金屬化晶圓10M且尤其其上之金屬氧化物層22暴露於含有金屬Q之還原氣體40。在一實例中,還原氣體40係三甲基鋁(TMA)或包括三甲基鋁,其中金屬Q係鋁。在另一實例中,還原氣體40係金屬烷基醯胺或包括金屬烷基醯胺,其中金屬Q係Hf、Zr、Si或Ti。並且在一實例中,諸如二乙基鋅之其它烷基金屬有機前驅物可用作還原氣體40。
還原氣體40還原金屬氧化物層22,藉以移除金屬氧化物層22。所需還原氣體40之暴露長度及量係待移除之天然金屬氧化物之特性、其厚度、金屬化基板10M之溫度及所用還原氣體40之類型的函數。此氧化-還原步驟之結果係在金屬層20上形成之M+MQy
Ox
形式之「金屬+金屬氧化物」層50。金屬+金屬氧化物層50具有表面52。在其中還原氣體40之金屬Q係鋁且其中金屬層20之金屬M係銅的一實例中,金屬+金屬氧化物層50可具有Cu + CuAlO2
之形式。
進行實驗,其中金屬化基板10M係使用M=銅之金屬層20,及具有1 nm至3 nm之厚度之氧化銅的金屬氧化物層22形成。將銅基金屬化基板10M在真空(0.1托)下加熱至150˚C至170˚C且以10至20個連續脈衝之TMA作為還原氣體40來移除天然氧化銅層22,其中TMA脈衝係0.015 s長及2 s至60 s分隔。原位觀察氧化銅層22之還原且在10次TMA暴露後其厚度逐漸減少至約1nm之厚度。亦注意亦觀察到在呈TDMAHf (其中金屬Q = Hf)及TDMAZr (其中Q = Zr)形式之還原氣體40之脈衝下之由該銅還原引起的視厚度減少,還原氣體40係常用於藉由ALD沉積HfO2
及ZrO2
之反應氣體。
由此銅基實例之金屬+金屬氧化物層50包括金屬Cu且金屬-氧化鋁具有前述之CuAlO2
形式。
第5圖係氧化銅層22之厚度(Å)對時間(s)之圖,如由原位光譜橢圓偏振計在20個連續脈衝之還原氣體40以60s之脈衝間間隔觀察到,還原氣體40係呈TMA(曲線A)、TDMAHf (曲線B)及TDMAZr (曲線C)之形式,說明所給還原氣體40如何減少Cu2
O層22之厚度。
參照第4圖,在第四步驟中將金屬+金屬氧化物層50立即暴露至包括SAM分子60之SAM蒸氣。一實例SAM蒸氣係硫醇,例如:1-十八烷基硫醇。該SAM分子60可有效地沉積在金屬+金屬氧化物層50之不含氧化物表面52以提供由SAM分子60(例如:硫醇分子)界定之高度堆積自組裝單層(「SAM層」)60L。在該製程中之此點,金屬化基板10M稱為SAM塗布基板(「SAMS」)10S。
在一實例中,氧化-還原步驟及SAMS沉積步驟可各在相同ALD腔室30中進行,但還原步驟可在不同ALD腔室30中進行,較佳地反應表面未暴露於空氣(例如:使用一密封轉移箱)。
SAM蒸氣暴露步驟可由數秒至數小時變化,但在實驗中提供600s之暴露時間以足以達到在銅基金屬化基板10M上硫醇分子60之良好SAM層60L。
堆積SAM分子60之SAM層60L(可由金屬化基板10M之還原預處理實現)構成一ALD抑制層,即對沉積ALD膜之一有效阻障層。SAM層60L延遲ALD膜之成核及生長持續相對大之ALD循環數(例如:N > 100)。
在方法之一實例中,原位還原步驟可使用含Q還原氣體40在兩個步驟中(例如:一金屬氧化物層22之ALD形成(例如:10-30 nm),接著金屬氧化物層22之原位還原)進行以獲得金屬+金屬氧化物層50。
實驗
亦在基板10上進行實驗,基板10係使用物理氣相沉積(PVD)以銅層20金屬化,天然氧化銅之頂部金屬氧化物層22具有在1 nm至3 nm間之厚度。金屬化基板10M係依現狀(即無預清洗)裝載在一ALD反應器中。所用之特定ALD反應器係Ultratech Cambridge Nanotech SavannahTM
反應器。快速地將金屬化基板10M帶至真空(0.1托)且在150˚C至170˚C間之溫度下加熱。
將連續脈衝之TMA引入ALD腔室30且藉由原位光譜橢圓偏振計即時觀察天然氧化銅之還原。發現10至20個0.015 s持續時間之TMA脈衝係足以完成天然氧化銅層22之還原。在第5圖之實例中脈衝係60s分隔,但該等脈衝可具有其它週期,例如5秒分隔或更短。脈衝亦可以TMA或其它還原氣體40之連續流置換。因此,在一實例中,金屬氧化物層22之還原係在600秒(s),即10分鐘內進行。在另一實例中,金屬氧化物層22之還原可在720 s,即12分鐘內進行。亦展示少於2分鐘之還原。
接著將所還原金屬表面在真空下暴露於1-十八烷硫醇蒸氣達600s以獲得在還原銅之頂部上之密集SAM層60L。藉由在經由ALD在銅/SAMS基板頂部上沉積HfNx
金屬氮化物期間監控該成核抑制而原位特性化SAM層60L之品質(即堆積密度)。金屬氮化物之生長經成功地延遲至針對硫醇塗布銅樣本之高達150次ALD循環相對於針對裸銅/氧化銅之0次ALD循環,以及針對含硫醇但無TMA預處理之銅/氧化銅之10次ALD循環。在暴露至硫醇處理之SiO2
表面上亦未觀察到顯著抑制。因此可實行此原位還原方法以促進在銅表面上之選區ALD。
藉由光譜橢圓偏振計原位監控暴露至ALD中常用之其它化學品之銅/氧化銅表面,該等化學品係諸如金屬烷基醯胺,即肆(二甲基胺)鉿(TDMAHf)或肆(二甲基胺)鋯(TDMAZr),指出亦可以該等前驅物還原氧化銅。可有效地使用之其它還原氣體40包括鈦烷基醯胺、矽烷基醯胺及二乙基鋅。
第6圖係ALD膜HfNx
之所測厚度(Å)對ALD循環數N之圖,其係針對在含天然氧化銅之一現有銅基板上(曲線A)、具硫醇SAM層60L但無還原預處理之銅上(曲線B)、及在具TMA預處理硫醇之銅上(曲線C)沉積之ALD膜,後者曲線顯示一ALD抑制性質,其中ALD膜之生長有效地延遲N > 150次ALD循環。第6圖之資料指示需要金屬氧化物層22之還原預處理以移除金屬氧化物層22而可形成ALD抑制SAM層60L。
在一實例中,使SAM塗布基板10S進行一ALD製程,以意圖使用在170˚C之溫度下沉積之TDMAHf及氨(NH3
)在SAM層60L上生長HfNx
之ALD膜。第7圖係ALD膜HfNx
之所測厚度(Å)對ALD循環數N之圖。圖式顯示在SiO2
+ SAM層上(曲線A)、在未還原銅 + SAM層上(曲線B)及還原銅 + SAM層上(曲線C)之ALD膜之生長。該等三個曲線說明ALD抑制SAM層60L如何相對於還原銅(生長僅發生在N >150次ALD循環)在SiO2
上幾乎不抑制(生長發生開始在N = 5次 ALD循環)。亦觀察到該TMA預處理及後續硫醇SAM沉積係選擇性的,當使用相同方法時有效硫醇SAM層60L係沉積在Cu+CuAlO2
層50上但不在SiO2
上。此指出在該預處理二氧化矽表面上之ALD製程期間不存在顯著成核抑制。
S-ALD
方法實例
本揭露之一態樣包括進行S-ALD作為在半導體裝置之製造中形成半導體結構之製程的部份。
第8A圖係一俯視圖且第8B圖係一實例金屬化基板10M之一截面圖(沿線A-A),其包括在基板10之上表面12上之一介電層100(例如:氧化物,諸如SiO2
膜)及在氧化物膜上之一金屬層20。金屬層20經圖案化且界定一電極。金屬圖案20包括金屬氧化物層22。氧化物膜可係用於半導體加工之任何氧化物,其中SiO2
係一實例氧化物。
第9A圖至第9D圖係當基板10進行提供ALD抑制SAM層60L之上述方法時沿線A-A之金屬化基板10M之截面圖。參照第9A圖,使圖案化金屬層20之金屬氧化物層22進行上述還原製程,其在圖案化金屬層20上形成金屬+金屬氧化物層50。如上述,金屬+金屬氧化物層50可容納SAM分子60。
參照第9B圖,接著將SAM分子60引入ALD腔室30之內部32以在由圖案化金屬層20界定之金屬+金屬氧化物層50之區段頂部上形成ALD抑制SAM層60L。SAM分子60不在介電層100上自組裝以使得此層100保持可用於ALD塗布。
參照第9C圖及第9D圖,進行ALD製程110,其在介電層100上但不在ALD抑制SAM層60L之區段上沉積ALD膜120。一旦完成ALD製程且在SiO2
層100上形成ALD膜120,使用溫和之蝕刻劑移除ALD抑制SAM層60L,留下具金屬+金屬氧化物層50及ALD塗布介電層100之金屬電極。
熟習本技術者顯而易見地可在不背離如隨附申請專利範圍中所定義之本揭露之精神或範疇下對如本文所述之本揭露之較佳具體實施例進行各種修正。因此,本揭露涵蓋該等修改及變化只要其在隨附申請專利範圍及其同等物之範疇內。
10‧‧‧基板 10M‧‧‧金屬化基板 10S‧‧‧SAM塗布基板 12‧‧‧上表面 20‧‧‧金屬層 22‧‧‧金屬氧化物層 30‧‧‧ALD腔室 32‧‧‧內部 40‧‧‧還原氣體 50‧‧‧金屬+金屬氧化物層 52‧‧‧表面 60‧‧‧SAM分子 60L‧‧‧SAM層 100‧‧‧介電層 110‧‧‧ALD製程 120‧‧‧ALD膜
所包括之隨附圖式提供進一步了解,及併入且構成本說明書之一部份。該等圖式說明一或多個具體實施例,並連同實施方式一起用於解釋各種具體實施例之原理及操作。同樣地,將由以下實施方式,連同隨附圖式變得更全面地了解本揭露,其中:
第1圖至第4圖係實例金屬化基板之截面圖,其顯示在該金屬化基板上形成一ALD抑制SAM層之方法的不同步驟;
第5圖係Cu2
O層之厚度TH(Å)對時間t(s)之關係圖,如由原位光譜橢圓偏振計在20個連續脈衝之還原氣體下以60 s之脈衝間間隔觀察到,其中該還原氣體係呈TMA(曲線A)、TDMAHf (曲線B)及TDMAZr (曲線C)之形式,其說明所給還原氣體如何減少Cu2
O層之厚度。
第6圖係該ALD膜HfNx
之所測厚度TH(Å)對ALD循環數N之圖,其係針對在具有天然氧化銅Cu2
O之一現有銅基板上(曲線A)、在具有硫醇但無還原預處理之銅上(曲線B)、及在具有TMA還原預處理並使用硫醇SAM分子之銅上(曲線C)沉積之ALD膜,後者顯示一ALD抑制性質,其中該ALD膜生長經有效地延遲超過150次ALD循環;
第7圖係一ALD膜HfNx
之所測厚度TH(Å)對ALD循環數N之圖,其顯示在SiO2
+ SAM層上(曲線A)、在未還原銅 + SAM層上(曲線B)及在還原銅 + SAM層上(曲線C) 該ALD膜之生長,說明該ALD抑制SAM層相對於還原銅(大於150次ALD循環)如何在SiO2
上幾乎無抑制(約5次ALD循環)。
第8A圖係一俯視圖且第8B圖係沿第8A圖之線A-A之一截面圖,其顯示具有SiO2
層之一實例金屬化基板,其中一圖案化金屬層在該SiO2
層上形成;及
第9A圖至第9D圖係類似第8B圖之橫截面,其說明用於在第8A圖及第8B圖之金屬化基板上進行S-ALD之實例方法步驟,其中ALD抑制層係在該等圖案化金屬層區段上形成,使得該ALD膜可在該SiO2
層上且不在該圖案化金屬層上形成。
10‧‧‧基板
10M‧‧‧金屬化基板
12‧‧‧上表面
20‧‧‧金屬層
22‧‧‧金屬氧化物層
Claims (28)
- 一種在覆蓋有金屬M之氧化物層(「金屬氧化物層」)的金屬M上形成ALD抑制層之方法,包含: a) 藉由將該金屬氧化物層暴露於包括一金屬Q之一還原氣體以還原該金屬氧化物層,以在該金屬M上形成M+MQx Oy 層;及 b) 將該M+MQx Oy 層暴露至呈蒸氣相之自組裝單層(「SAM」)分子,其中該SAM分子在該M+MQx Oy 層上形成具ALD抑制特性之一SAM層。
- 如申請專利範圍第1項所述之方法,其中: 該金屬M係Cu、Ni、Fe或Co;及 該金屬Q係Al、Hf、Zr、Si、Ti或Zn。
- 如申請專利範圍第1項所述之方法,其中該SAM分子係硫醇分子。
- 如申請專利範圍第1項所述之方法,其中: 該金屬M係銅; 該金屬氧化物層係由氧化銅製成; 該還原氣體包含三甲基鋁(TMA); 該SAM分子係硫醇分子;及 該M+MQx Oy 層係Cu+CuAlO2 層。
- 如申請專利範圍第1項所述之方法,其中步驟a)係在120°C與250°C間之溫度下進行。
- 如申請專利範圍第1項所述之方法,其中步驟a)及b)係在少於1托之真空條件下進行。
- 如申請專利範圍第1項所述之方法,其中該金屬氧化物層具有範圍在1 nm至5 nm之厚度。
- 如申請專利範圍第1項所述之方法,其中該ALD抑制層實質上抑制其上之ALD膜之形成持續至少100次ALD循環。
- 如申請專利範圍第8項所述之方法,其中該ALD抑制層實質上抑制其上之ALD膜之形成持續至少150次ALD循環。
- 如申請專利範圍第1項所述之方法,其更包含在一半導體基板上形成該金屬M作為一圖案化金屬層。
- 如申請專利範圍第1項所述之方法,其中該金屬M形成為在一半導體基板之介電層上之一圖案,且進一步地包含藉由以下進行選區ALD: 在該介電層及覆蓋該金屬M之該SAM層上進行一ALD製程,藉以在該介電層上但不在該SAM層上形成一ALD膜。
- 如申請專利範圍第11項所述之方法,其中該介電層係氧化物層。
- 如申請專利範圍第11項所述之方法,其更包含移除該SAM層。
- 如申請專利範圍第1項所述之方法,其中步驟a)係在少於720秒下進行。
- 一種進行選區原子層沉積(「S-ALD」)之方法,其包含: a) 在由一半導體基板支撐之一介電層上界定一層金屬M(「金屬層」),其中該金屬層界定一圖案,且其中該金屬層係以一層金屬M之氧化物(「金屬氧化物層」)覆蓋; b) 藉由將該金屬氧化物層暴露於一還原氣體以還原該金屬氧化物層,其包括一金屬Q以在該金屬層上形成M+MQx Oy 層; c) 將該M+MQx Oy 層及該介電層暴露至呈蒸氣相之自組裝單層(SAM)分子,其中該SAM分子在該M+MQx Oy 層上形成一SAM層以界定一ALD抑制層,及其中在該介電層上未形成SAM層;及 d) 進行一ALD製程以沉積一ALD膜,其中該ALD膜在該介電層上但不在該SAM層上形成。
- 如申請專利範圍第15項所述之方法,其中: 該金屬M係Cu、Ni、Fe或Co;及 該金屬Q係Al、Hf、Zr、Si、Ti或Zn。
- 如申請專利範圍第15項所述之方法,其更包含移除該SAM層之一步驟e)。
- 如申請專利範圍第15項所述之方法,其中步驟b)係在720秒內進行。
- 如申請專利範圍第15項所述之方法,其中該SAM分子係由硫醇分子組成。
- 如申請專利範圍第15項所述之方法,其中該介電層包含SiO2 層。
- 如申請專利範圍第15項所述之方法,其中: 該金屬M係銅; 該金屬氧化物層係由氧化銅製成; 該還原氣體包含三甲基鋁(TMA); 該SAM分子係硫醇分子;及 該M+MQx Oy 層係Cu+CuAlO2 層。
- 如申請專利範圍第15項所述之方法,其中該SAM層實質上抑制其上之ALD膜之形成持續至少100次ALD循環。
- 如申請專利範圍第22項所述之方法,其中該SAM層實質上抑制其上之ALD膜之形成持續至少150次ALD循環。
- 如申請專利範圍第15項所述之方法,其中步驟b)係在120°C與250°C間之溫度下進行。
- 如申請專利範圍第15項所述之方法,其中步驟b)及c)係在少於1托之真空條件下進行。
- 如申請專利範圍第15項所述之方法,其中該金屬氧化物層具有範圍在1 nm至5 nm之厚度。
- 如申請專利範圍第15項所述之方法,其中該還原氣體包含三甲基鋁(TMA)或烷基醯胺。
- 如申請專利範圍第15項所述之方法,其中步驟b)、c)及d)係在單一ALD腔室中進行。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201562244467P | 2015-10-21 | 2015-10-21 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201716617A TW201716617A (zh) | 2017-05-16 |
TWI598457B true TWI598457B (zh) | 2017-09-11 |
Family
ID=58558431
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW105133783A TWI598457B (zh) | 2015-10-21 | 2016-10-19 | 使用自組裝單層形成ald抑制層之方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US10316406B2 (zh) |
JP (1) | JP6306661B2 (zh) |
KR (1) | KR20170046591A (zh) |
CN (1) | CN106611702A (zh) |
SG (1) | SG10201608841VA (zh) |
TW (1) | TWI598457B (zh) |
Families Citing this family (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI627192B (zh) * | 2015-03-13 | 2018-06-21 | 村田製作所股份有限公司 | Atomic layer deposition inhibiting material |
US10695794B2 (en) | 2015-10-09 | 2020-06-30 | Asm Ip Holding B.V. | Vapor phase deposition of organic films |
US10814349B2 (en) | 2015-10-09 | 2020-10-27 | Asm Ip Holding B.V. | Vapor phase deposition of organic films |
US10373820B2 (en) | 2016-06-01 | 2019-08-06 | Asm Ip Holding B.V. | Deposition of organic films |
US10453701B2 (en) | 2016-06-01 | 2019-10-22 | Asm Ip Holding B.V. | Deposition of organic films |
JP7169072B2 (ja) * | 2017-02-14 | 2022-11-10 | エーエスエム アイピー ホールディング ビー.ブイ. | 選択的パッシベーションおよび選択的堆積 |
TWI850084B (zh) * | 2017-06-14 | 2024-07-21 | 美商應用材料股份有限公司 | 用於達成無缺陷自組裝單層的晶圓處理設備 |
US10586734B2 (en) * | 2017-11-20 | 2020-03-10 | Tokyo Electron Limited | Method of selective film deposition for forming fully self-aligned vias |
JP7226336B2 (ja) | 2018-01-10 | 2023-02-21 | Jsr株式会社 | パターン形成方法 |
JP7146690B2 (ja) | 2018-05-02 | 2022-10-04 | エーエスエム アイピー ホールディング ビー.ブイ. | 堆積および除去を使用した選択的層形成 |
WO2019229785A1 (ja) * | 2018-05-28 | 2019-12-05 | 株式会社Kokusai Electric | 半導体装置の製造方法、基板処理装置およびプログラム |
JP7110468B2 (ja) * | 2018-05-28 | 2022-08-01 | 株式会社Kokusai Electric | 半導体装置の製造方法、基板処理装置、プログラム及び基板処理方法。 |
JP7059810B2 (ja) * | 2018-05-30 | 2022-04-26 | 株式会社デンソー | 表面被覆部材及びその製造方法 |
US10643889B2 (en) * | 2018-08-06 | 2020-05-05 | Lam Rasearch Corporation | Pre-treatment method to improve selectivity in a selective deposition process |
CN109712868A (zh) * | 2018-12-20 | 2019-05-03 | 西安电子科技大学 | 基于氧化铝材料内嵌纳米晶结构的铁电薄膜制备方法 |
US10961624B2 (en) | 2019-04-02 | 2021-03-30 | Gelest Technologies, Inc. | Process for pulsed thin film deposition |
US11450562B2 (en) | 2019-09-16 | 2022-09-20 | Tokyo Electron Limited | Method of bottom-up metallization in a recessed feature |
JP7195239B2 (ja) * | 2019-09-24 | 2022-12-23 | 東京エレクトロン株式会社 | 成膜方法及び成膜装置 |
JP7262354B2 (ja) * | 2019-09-24 | 2023-04-21 | 東京エレクトロン株式会社 | 成膜方法 |
JP2021052070A (ja) * | 2019-09-24 | 2021-04-01 | 東京エレクトロン株式会社 | 成膜方法 |
KR20220113444A (ko) * | 2019-12-10 | 2022-08-12 | 도쿄엘렉트론가부시키가이샤 | 희생 캡핑 층으로서의 자가-조립된 모노층 |
EP4158078A1 (en) | 2020-05-27 | 2023-04-05 | Gelest, Inc. | Silicon-based thin films from n-alkyl substituted perhydridocyclotrisilazanes |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3998746B2 (ja) | 1996-11-28 | 2007-10-31 | 財団法人川村理化学研究所 | オキソチタニウムフタロシアニン配向膜及びその製造方法 |
JP5445886B2 (ja) | 2006-03-31 | 2014-03-19 | 静岡県 | 改質された固体表面を形成する方法および改質された固体表面 |
US20080032064A1 (en) | 2006-07-10 | 2008-02-07 | President And Fellows Of Harvard College | Selective sealing of porous dielectric materials |
WO2008136882A2 (en) * | 2007-02-14 | 2008-11-13 | The Board Of Trustees Of The Leland Stanford Junior University | Fabrication method of size-controlled, spatially distributed nanostructures by atomic layer deposition |
JP2009158691A (ja) | 2007-12-26 | 2009-07-16 | Sharp Corp | 有機デバイスおよびその製造方法 |
US8293658B2 (en) | 2010-02-17 | 2012-10-23 | Asm America, Inc. | Reactive site deactivation against vapor deposition |
JP5646914B2 (ja) | 2010-08-24 | 2014-12-24 | 独立行政法人科学技術振興機構 | トンネル接合素子の製造方法 |
JP2013143424A (ja) | 2012-01-10 | 2013-07-22 | Elpida Memory Inc | 半導体装置及びその製造方法 |
WO2013141149A1 (ja) | 2012-03-19 | 2013-09-26 | 三菱電機株式会社 | 半導体装置の製造方法 |
US9165821B2 (en) * | 2013-12-23 | 2015-10-20 | Infineon Technologies Ag | Method for providing a self-aligned pad protection in a semiconductor device |
TWI739285B (zh) * | 2014-02-04 | 2021-09-11 | 荷蘭商Asm Ip控股公司 | 金屬、金屬氧化物與介電質的選擇性沉積 |
US9515166B2 (en) * | 2014-04-10 | 2016-12-06 | Applied Materials, Inc. | Selective atomic layer deposition process utilizing patterned self assembled monolayers for 3D structure semiconductor applications |
-
2016
- 2016-10-17 US US15/295,813 patent/US10316406B2/en not_active Expired - Fee Related
- 2016-10-19 TW TW105133783A patent/TWI598457B/zh not_active IP Right Cessation
- 2016-10-20 KR KR1020160136553A patent/KR20170046591A/ko unknown
- 2016-10-20 JP JP2016206010A patent/JP6306661B2/ja not_active Expired - Fee Related
- 2016-10-21 CN CN201610919979.1A patent/CN106611702A/zh active Pending
- 2016-10-21 SG SG10201608841VA patent/SG10201608841VA/en unknown
Also Published As
Publication number | Publication date |
---|---|
CN106611702A (zh) | 2017-05-03 |
TW201716617A (zh) | 2017-05-16 |
JP6306661B2 (ja) | 2018-04-04 |
JP2017098539A (ja) | 2017-06-01 |
KR20170046591A (ko) | 2017-05-02 |
US10316406B2 (en) | 2019-06-11 |
SG10201608841VA (en) | 2017-05-30 |
US20170114451A1 (en) | 2017-04-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI598457B (zh) | 使用自組裝單層形成ald抑制層之方法 | |
JP7523936B2 (ja) | 金属表面上の金属酸化物の選択的堆積 | |
TWI722301B (zh) | 在金屬材料表面上沉積阻擋層的方法 | |
KR102662636B1 (ko) | 유전체 표면들에 대하여 금속 또는 금속성 표면들 상에서의 선택적 퇴적 | |
JP7290760B2 (ja) | 選択的原子層堆積方法 | |
TWI772460B (zh) | 氣相塗佈之方法及氣相沈積製程 | |
JP3798248B2 (ja) | ラジカルを利用した連続cvd | |
US20200234950A1 (en) | Methods For Selective Deposition On Silicon-Based Dielectrics | |
CN110709534B (zh) | TiAlN膜的铝含量控制 | |
TWI727660B (zh) | 氮化矽之選擇性沉積 | |
JP2024511271A (ja) | 原子層堆積のための還元剤 | |
US9460932B2 (en) | Surface poisoning using ALD for high selectivity deposition of high aspect ratio features | |
US20220139703A1 (en) | New precursors for selective atomic layer deposition of metal oxides with small molecule inhibitors | |
US20230197438A1 (en) | Selective tantalum nitride deposition for barrier applications | |
JP7577449B2 (ja) | 3d-nandデバイスでのワードライン分離のための方法 | |
JP2023143793A (ja) | 基板処理方法及びこれを用いた選択的蒸着方法 | |
KR20240135381A (ko) | 상호연결 구조물들을 형성하는 방법들 | |
WO2023205332A1 (en) | Area selective atomic layer deposition of metal oxide or dielectric layer on patterned substrate |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |