TWI594258B - 具有劃分邏輯的堆疊式半導體晶粒總成以及相關的系統及方法 - Google Patents

具有劃分邏輯的堆疊式半導體晶粒總成以及相關的系統及方法 Download PDF

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TWI594258B
TWI594258B TW104110126A TW104110126A TWI594258B TW I594258 B TWI594258 B TW I594258B TW 104110126 A TW104110126 A TW 104110126A TW 104110126 A TW104110126 A TW 104110126A TW I594258 B TWI594258 B TW I594258B
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Taiwan
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die
logic
stack
memory
logic die
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TW104110126A
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TW201601165A (zh
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李健
史蒂芬Ｋ 古斯厄斯
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美光科技公司
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Description

具有劃分邏輯的堆疊式半導體晶粒總成以及相關的系統及方法
所揭示實施例係關於半導體晶粒總成且係關於管理此等總成內之熱。特定而言，本發明技術係關於具有堆疊於劃分邏輯晶粒之間的記憶體晶粒之晶粒總成。
包含記憶體晶片、微處理器晶片及成像器晶片之封裝式半導體晶粒通常包含安裝於一基板上且包封於一塑膠保護覆蓋中之一半導體晶粒。晶粒包含功能特徵，諸如記憶體單元、處理器電路及成像器裝置以及電連接至該等功能特徵之接合墊。接合墊可電連接至保護覆蓋外部之端子以允許晶粒連接至較高階電路。
半導體製造商不斷減小晶粒封裝之大小以裝配在電子裝置之空間約束內，同時亦增加每一封裝之功能能力以滿足操作參數。用於在實質上不增加由封裝覆蓋之表面積(亦即，封裝之「佔用面積」)之情況下增加一半導體封裝之處理能力之一種方法係在一單個封裝中在彼此之頂部上垂直堆疊多個半導體晶粒。此等垂直堆疊之封裝中之晶粒可藉由使用穿矽導通體(TSV)將個別晶粒之接合墊與毗鄰晶粒之接合墊電耦合來互連。
由垂直堆疊之晶粒封裝中之個別晶粒產生之熱難以耗散，此增 加個別晶粒、其間之接面及作為一整體之封裝之操作溫度。在諸多類型之裝置中且尤其在封裝中之晶粒之密度增加時，此可導致堆疊晶粒達到超過其最大操作溫度(Tmax)之溫度。
100‧‧‧半導體晶粒總成/總成
102a‧‧‧第一邏輯晶粒
102b‧‧‧第二邏輯晶粒
103‧‧‧記憶體晶粒/個別記憶體晶粒
105‧‧‧堆疊/記憶體晶粒堆疊
106‧‧‧背側部分
107‧‧‧周邊部分
110‧‧‧導熱殼體/殼體
112‧‧‧蓋部分
113‧‧‧壁部分
114a‧‧‧第一界面材料
114b‧‧‧第二界面材料
116‧‧‧介電底膠填充材料/底膠填充材料
120‧‧‧封裝基板/殼體
122‧‧‧插置器
124‧‧‧封裝觸點
125‧‧‧電連接器
130‧‧‧貫穿堆疊互連件
200‧‧‧混合記憶體立方體總成
201‧‧‧單個下伏邏輯晶粒/邏輯晶粒
202a‧‧‧第一邏輯晶粒
202b‧‧‧第二邏輯晶粒
202c‧‧‧邏輯晶粒
202d‧‧‧邏輯晶粒
203‧‧‧記憶體晶粒堆疊/記憶體晶粒
204‧‧‧堆疊式記憶體晶粒/記憶體晶粒
207‧‧‧周邊部分
227‧‧‧經疊加佔用面積
240a‧‧‧第一積體電路組件
240b‧‧‧第二積體電路組件
260‧‧‧半導體晶粒總成
290‧‧‧混合記憶體立方體總成/總成
300‧‧‧半導體晶粒總成/總成
308‧‧‧接合墊
309‧‧‧接合墊
326‧‧‧最外表面
329‧‧‧塊狀部分
330‧‧‧貫穿堆疊互連件
331‧‧‧「虛設」接觸墊
332‧‧‧電連接器/互連件
334‧‧‧貫穿晶粒互連件
339‧‧‧部分
400‧‧‧總成
430a‧‧‧雙側箭頭/第一貫穿堆疊互連件
430b‧‧‧雙側箭頭/第二貫穿堆疊互連件
430c‧‧‧雙側箭頭
440‧‧‧通信組件
441‧‧‧額外電路組件
442‧‧‧記憶體控制器組件/記憶體控制器
444‧‧‧記憶體
600‧‧‧半導體晶粒總成/總成
620‧‧‧支撐基板
700‧‧‧半導體晶粒總成
790‧‧‧系統/所得系統/代表系統
792‧‧‧電源
794‧‧‧驅動器
796‧‧‧處理器
798‧‧‧其他子系統/組件
圖1係根據本發明技術之一實施例組態之一半導體晶粒總成之一剖面圖。
圖2A係圖解說明一HMC總成在操作期間之一溫度量變曲線之一等角視圖，且圖2B係圖解說明根據本發明技術之一實施例之一HMC總成之一溫度量變曲線之一等角視圖。
圖2C係圖解說明根據本發明技術之另一實施例組態之一半導體晶粒總成之一等角視圖。
圖3係根據本發明技術之另一實施例組態之一半導體晶粒總成之一剖面圖。
圖4係根據本發明技術之一實施例組態之具有積體電路組件之一半導體晶粒總成之一示意圖。
圖5係圖解說明根據本發明技術之一實施例之用於操作一半導體晶粒總成之一方法之一流程圖。
圖6係根據本發明技術之另一實施例組態之一半導體晶粒總成之一剖面圖。
圖7係根據本發明技術之實施例組態之包含一半導體晶粒總成之一系統之一示意圖。
下文闡述具有堆疊於劃分邏輯晶粒之間的記憶體晶粒之堆疊式半導體晶粒總成以及相關的系統及方法之數個實施例之特定細節。術語「半導體晶粒」通常係指具有積體電路或組件、資料儲存元件、處理組件及/或製造於半導體基板上之其他特徵之一晶粒。舉例而言， 半導體晶粒可包含積體電路記憶體及/或邏輯電路。半導體晶粒及/或半導體晶粒封裝中之其他特徵據稱可彼此「熱接觸」(若兩個結構可透過熱來交換能量的話)。熟習此項技術者亦將理解，本技術可具有額外實施例，且可在無下文參考圖1至圖7所闡述之實施例之數個細節之情形下實踐本技術。
如本文中所使用，術語「垂直」、「橫向」、「上部」及「下部」可係指鑒於圖中所展示之定向之半導體晶粒總成中之特徵之對置方向或位置。舉例而言，「上部」或「最上部」可係指經定位比另一特徵更接近於一頁之頂部之一特徵。然而，此等術語應廣泛地理解為包含具有其他定向之半導體裝置。
圖1係根據本發明技術之一實施例組態之一半導體晶粒總成100(「總成100」)之一剖面圖。如所展示，總成100包含一第一邏輯晶粒102a、一第二邏輯晶粒102b(統稱「邏輯晶粒102」)及配置於一堆疊105(「記憶體晶粒堆疊105」)中在邏輯晶粒102之間的複數個記憶體晶粒103。第一邏輯晶粒102a藉由一插置器122電耦合至一封裝基板120。插置器122可包含(舉例而言)一半導體晶粒、一介電間隔物及/或具有連接於插置器122與封裝基板120之間的電連接器(例如，導通體、金屬跡線等)之其他適合基板。封裝基板120可包含(舉例而言)一插置器、一印刷電路板或連接至將總成100電耦合至外部電路(未展示)之封裝觸點124(例如，接合墊)及電連接器125(例如，焊料凸塊)之其他適合基板。在某些實施例中，封裝基板120及/或插置器122可以不同方式組態。舉例而言，在某些實施例中，可省略插置器122且可將第一邏輯晶粒102a直接連接至封裝基板120。
第一邏輯晶粒102a及第二邏輯晶粒102b耦合至延伸穿過記憶體晶粒堆疊105之複數個貫穿堆疊互連件130。在圖1之所圖解說明實施例中，出於圖解說明目的而將貫穿堆疊互連件130展示為大體上垂直單 一結構。然而，貫穿堆疊互連件130中之每一者可由貫穿記憶體晶粒堆疊105之彼此互連之經垂直及/或橫向配置導電元件的一組合構成。舉例而言，貫穿堆疊互連件130中之每一者可包含經互連導電柱、導通體、貫穿晶粒導通體、焊料凸塊、金屬跡線等之一配置。
總成100進一步包含將第二邏輯晶粒102b及記憶體晶粒堆疊105至少部分地封圍於一外殼(例如，一腔)內之一導熱殼體110。在所圖解說明實施例中，殼體110包含一蓋部分112及附接至蓋部分112或與蓋部分112整體形成之一壁部分113。蓋部分112可藉由一第一界面材料114a(例如，一黏合劑)附接至第二邏輯晶粒102b之一背側部分106。壁部分113可遠離蓋部分112垂直延伸且藉由一第二界面材料114b(例如，一黏合劑)附接至第一邏輯晶粒102a之一周邊部分107(作為一「廊」或「架」為熟習此項技術者已知)。除提供一保護覆蓋之外，殼體110亦提供一散熱器以自邏輯晶粒102及記憶體晶粒103吸收並耗散熱能。因此，殼體110可由一導熱材料(諸如鎳、銅、鋁、具有高導熱率之陶瓷材料(例如，氮化鋁)及/或其他適合導熱材料)製成。
在某些實施例中，第一界面材料114a及/或第二界面材料114b可由經設計以增加表面接面(例如，一晶粒表面與一散熱器之間)處之熱接觸傳導性之此項技術中稱為「熱界面材料」或「TIM」之材料製成。TIM可包含摻雜有傳導材料(例如，碳奈米管、焊料材料、類鑽碳(DLC)等)之基於聚矽氧之油脂、凝膠或黏合劑以及相變材料。在某些實施例中，舉例而言，熱界面材料可由具有約3W/m°K至4W/m°K之一導熱率之亞利桑那州鳳凰城(Phoenix)之Shin-Etsu MicroSi公司所製造之X-23-7772-4 TIM製成。在其他實施例中，第一界面材料114a及/或第二界面材料114b可包含其他適合材料，諸如金屬(例如，銅)及/或其他適合導熱材料。
邏輯晶粒102及/或記憶體晶粒103可至少部分地囊封於一介電底 膠填充材料116中。底膠填充材料116可沈積或以其他方式形成於總成100之晶粒中之某些或所有晶粒周圍及/或之間以增強晶粒之間的機械連接及/或提供(例如)晶粒之間的互連件或其他導電結構之間的電隔離。底膠填充材料116可為一非導電環氧樹脂膏(例如，由日本新潟(Niigata)之Namics公司製造之XS8448-171)、一毛細管底膠填充、一非導電膜、一經模製底膠填充及/或包含其他適合電絕緣材料。在數個實施例中，可基於其導熱率來選擇底膠填充材料116以增強貫穿總成100之晶粒之熱耗散。在某些實施例中，底膠填充材料116可替代第一界面材料114a及/或第二界面材料114b而用於將殼體110附接至第一邏輯晶粒102a及/或第二邏輯晶粒102b。
邏輯晶粒102及記憶體晶粒103可各自由一半導體基板(諸如矽、絕緣體上矽、化合物半導體(例如，氮化鎵))或其他適合基板形成。半導體基板可切割或單粒化成具有各種積體電路組件或功能特徵(諸如動態隨機存取記憶體(DRAM)、靜態隨機存取記憶體(SRAM)、快閃記憶體、包含記憶體、處理電路、成像組件之其他形式之積體電路裝置及/或其他半導體裝置)中之任一者之半導體晶粒。在選定實施例中，總成100可組態為一混合記憶體立方體(HMC)，其中在HMC內，記憶體晶粒103提供資料儲存裝置(例如，DRAM晶粒)且邏輯晶粒102共同地提供記憶體控制件(例如，DRAM控制件)。在某些實施例中，除邏輯晶粒102及記憶體晶粒103中之一或多者之外及/或替代邏輯晶粒102及記憶體晶粒103中之一或多者，總成100亦可包含其他半導體晶粒。舉例而言，此等半導體晶粒可包含除資料儲存裝置及/或記憶體控制組件外之積體電路組件。此外，儘管總成100包含堆疊於插置器122上之十個晶粒，但在其他實施例中，總成100可包含少於十個晶粒(例如，六個晶粒)或十個以上晶粒(例如，十二個晶粒、十四個晶粒等)。舉例而言，在一項實施例中，總成100可包含堆疊於四個記憶體晶粒 之頂部上之兩個邏輯晶粒及堆疊於四個記憶體晶粒下方之一單個邏輯晶粒。此外，在各種實施例中，邏輯晶粒102及記憶體晶粒103可具有不同大小。舉例而言，在某些實施例中，第一邏輯晶粒102a可具有與記憶體晶粒堆疊105相同之佔用面積及/或第二邏輯晶粒102b可具有比記憶體晶粒堆疊105小或大的一佔用面積。
一般而言，由一邏輯晶粒產生之熱可顯著大於由記憶體晶粒共同地產生之熱。舉例而言，一習用HMC總成中之一邏輯晶粒可在操作期間消耗總功率之80%。一習用半導體晶粒總成通常包含朝向該總成之底部定位之一單個邏輯晶粒。此意指在操作期間，來自邏輯晶粒之熱在至總成之殼體途中必須轉移穿過記憶體晶粒。由於熱轉移穿過記憶體晶粒，因此此增加了總成之整體溫度。舉例而言，圖2A係圖解說明一HMC總成290在操作期間之一溫度量變曲線之一等角視圖。如所展示，HMC總成290包含堆疊式記憶體晶粒204及一單個下伏邏輯晶粒201。在操作期間，邏輯晶粒201之高溫將熱能朝向總成290之底部集中。舉例而言，邏輯晶粒201具有約111℃之一最大操作溫度，而記憶體晶粒204具有約105℃之一最大操作溫度。此熱集中可導致邏輯晶粒201以及毗鄰記憶體晶粒204超過其最大操作溫度(Tmax)。此可尤其係針對可具有(例如)約14W(對(例如)較早一代HMC總成之約4W)之一邏輯核心功率之較新一代HMC總成之情形。
預期根據本發明技術之實施例組態之半導體晶粒總成減少穿過記憶體晶粒之熱流。舉例而言，圖2B係圖解說明根據本發明技術之一HMC總成200在操作期間之一溫度量變曲線之一等角視圖。HMC總成200包含安置於一第一邏輯晶粒202a與一第二邏輯晶粒202b之間的一記憶體晶粒堆疊203。如所展示，第一邏輯晶粒202a朝向一周邊部分207耗散其熱之大部分。舉例而言，周邊部分207可將熱直接耗散至殼體110之壁部分113(圖1)。另一方面，第二邏輯晶粒202b朝向總成 之頂部耗散其熱之大部分。舉例而言，第二邏輯晶粒202b可將熱直接耗散至殼體110之蓋部分112(圖1)。因此，第一邏輯晶粒202a之最大溫度低於HMC總成290之邏輯晶粒201之最大溫度(例如，96℃對111℃)。此外，記憶體晶粒203之最大溫度低於記憶體晶粒204之最大操作溫度(例如，91℃對96℃)。因此，HMC總成200之邏輯晶粒202及記憶體晶粒203可在一更可接受溫度範圍內且在最大溫度規範以下操作。
一般而言，一半導體晶粒總成之邏輯晶粒可包含具有用於貫穿一半導體晶粒總成耗散熱之各種配置中之任一者之積體電路組件。舉例而言，圖2C展示具有在記憶體晶粒堆疊203下方之一邏輯晶粒202c及在記憶體晶粒堆疊203之頂部上之一邏輯晶粒202d之一半導體晶粒總成260。邏輯晶粒202c可包含朝向邏輯晶粒202c之周邊集中之第一積體電路組件240a(示意性地展示)，且邏輯晶粒202d可包含跨越實質上整個邏輯晶粒202d形成之第二積體電路組件240b(示意性地展示)。在另一實施例中，第二積體電路組件240b可自邏輯晶粒202d之周邊偏移且更居中地安置(如由經疊加佔用面積227所展示)。在各種實施例中，積體電路組件亦可經組態以產生不同量之熱。舉例而言，一最頂部邏輯晶粒之積體電路組件可產生多於邏輯相關之熱之50%(例如，熱之約75%或更多)，而最底部邏輯晶粒可產生少於邏輯相關之熱之50%(例如，熱之約25%或更少)。另一選擇係，最頂部邏輯晶粒之積體電路組件可產生比最底部邏輯晶粒之電路組件少的熱。
圖3係根據本發明技術之另一實施例組態之一半導體晶粒總成300(「總成300」)之一剖面圖。總成300可包含大體上類似於上文詳細闡述之總成100之彼等特徵之特徵。舉例而言，總成300可包含定位於邏輯晶粒102之間的記憶體晶粒堆疊105。在圖3之所圖解說明實施例中，第一邏輯晶粒102a、第二邏輯晶粒102b及記憶體晶粒103中之 每一者藉由複數個電連接器或互連件332(例如，銅柱、焊料凸塊、導電跡線、接觸墊等)彼此電耦合。第一邏輯晶粒102a及個別記憶體晶粒103可各自包含耦合於與互連件332對置之側上之複數個貫穿晶粒互連件334(例如，貫穿基板導通體、TSV等)。互連件332及貫穿晶粒互連件334可由各種類型之導電材料(例如，金屬材料)形成，諸如銅、鎳、鋁等。在某些實施例中，導電材料可包含焊料(例如，基於SnAg之焊料)、導體填充之環氧樹脂及/或其他導電材料。在選定實施例中，舉例而言，互連件332可為銅柱，而在其他實施例中，互連件332可包含更複雜結構(諸如氮化物上凸塊結構)。在其他實施例中，可用其他類型之材料或結構(諸如一導電膏)來替換互連件332。
在此實施例之一項態樣中，第二邏輯晶粒102b可在無貫穿晶粒互連件之情況下形成，此乃因第二邏輯晶粒102b朝向總成100之頂部而非總成之底部安置。舉例而言，習用半導體晶粒封裝具有安置於封裝基板與記憶體晶粒堆疊之間的一單個邏輯晶粒。此配置可需要邏輯晶粒具有貫穿晶粒互連件以電連接封裝基板與記憶體晶粒堆疊。此配置亦可需要邏輯晶粒係薄的以減小貫穿晶粒互連件之垂直長度及縱橫比。舉例而言，可藉由背面研磨、蝕刻及/或化學機械拋光(CMP)來使邏輯晶粒(或用以形成邏輯晶粒之基板)變薄至一定大小。因此，在總成100之頂部處具有第二邏輯晶粒102b之一個優點係可用比形成第一邏輯晶粒102a少的製造步驟形成第二邏輯晶粒102b。舉例而言，可在無用於形成貫穿晶粒互連件之基板變薄、通孔蝕刻及金屬沈積程序之情況下形成第二邏輯晶粒102b。在數個實施例中，第二邏輯晶粒102b可具有在約300μm至約1000μm之範圍中(例如，350μm)之一厚度且總成100中之其他晶粒可具有在約50μm至約200μm之範圍中(例如，100μm)之一厚度。
在此實施例之另一態樣中，第二邏輯晶粒102b包含半導體基板 之一塊狀部分329，塊狀部分329在形成貫穿晶粒互連件時通常將自第二邏輯晶粒102b移除。在數個實施例中，塊狀部分329可促進遠離總成300且穿過殼體110之蓋部分112之熱傳導。在另一實施例中，可自總成300省略殼體110以使得總成300之一最外表面326曝露。在一替代實施例中，可用底膠填充材料116及/或另一材料(例如，一封裝殼體之一囊封劑)覆蓋最外表面326。
除電通信之外，互連件332及貫穿晶粒互連件334亦可用作透過其可將熱自記憶體晶粒堆疊105轉移走且轉移朝向殼體110的導管。在某些實施例中，總成100亦可包含以填隙方式定位於互連件332之間的複數個導熱元件或「虛設元件」(未展示)以進一步促進熱遠離邏輯晶粒102及記憶體晶粒103轉移。此等虛設元件可在結構及組合物上至少大體上與互連件332類似，惟該等虛設元件不電耦合至邏輯晶粒102及記憶體晶粒103除外。
在所圖解說明實施例中，複數個貫穿堆疊互連件330將第一邏輯晶粒102a之接合墊308與第二邏輯晶粒102b之對應接合墊309耦合。如上文所論述，貫穿堆疊互連件330可各自由互連件332及貫穿晶粒互連件334之一集體部分構成。在某些實施例中，貫穿堆疊互連件330之一部分339可在功能上與第一邏輯晶粒102a隔離。舉例而言，貫穿堆疊互連件330之部分339可在第一邏輯晶粒102a處連接至在功能上與第一邏輯晶粒102a之積體電路組件(未展示)隔離之「虛設」接觸墊331。
圖4係根據本發明技術之一實施例組態之具有積體電路組件之一半導體晶粒總成(「總成400」)之一示意圖。總成400可包含大體上類似於上文詳細闡述之晶粒總成之彼等特徵之特徵。舉例而言，總成400可包含定位於第一邏輯晶粒102a與一第二邏輯晶粒102b之間的記憶體晶粒堆疊105。在所圖解說明實施例中，第一邏輯晶粒102a包含耦合至封裝基板120之封裝觸點124(圖1)之通信組件440。第二邏輯晶 粒102b可包含藉由一或多個第一貫穿堆疊互連件(由雙側箭頭430a示意性地表示)耦合至通信組件440之記憶體控制器組件442(「記憶體控制器442」)。記憶體晶粒103中之每一者可包含配置於記憶體(「記憶體444」)之一或多個陣列及/或記憶體區塊中之複數個記憶體單元(未展示)。個別記憶體晶粒103之記憶體444藉由一或多個第二貫穿堆疊互連件(由雙側箭頭430b示意性地表示)耦合至記憶體控制器442。
在此實施例之一項態樣中，通信組件440朝向第一邏輯晶粒102a之外周邊配置以將熱耗散至殼體110之壁部分113(圖1)。另一方面，記憶體控制器442定位於總成100之頂部處以將熱耗散至殼體110之蓋部分112(圖1)。然而，在某些實施例中，通信組件440及/或記憶體控制器442可在總成400內不同地定位。舉例而言，在數個實施例中，通信組件440可位於記憶體晶粒堆疊105之兩個以上側處。在其他實施例中，通信組件440可位於記憶體晶粒堆疊105之一單個側處。此外，在特定實施例中，通信組件440可在記憶體晶粒堆疊105下方延伸。
在數個實施例中，第一邏輯晶粒102a及/或第二邏輯晶粒102b可包含額外及/或替代積體電路組件。舉例而言，在所圖解說明實施例中，第一邏輯晶粒102a包含在記憶體晶粒堆疊105下方之額外電路組件441(例如，功率分佈組件、時脈電路等)。在數個實施例中，額外電路組件441可具有比通信組件440低的操作溫度。在一項實施例中，額外電路組件441可藉由第三貫穿堆疊互連件(由雙側箭頭430c示意性地表示)耦合至第二邏輯晶粒102b。在另一實施例中，額外電路組件441亦可藉由第一貫穿堆疊互連件430a及/或第二貫穿堆疊互連件430b耦合至第二邏輯晶粒102b。另一選擇係，第一貫穿堆疊互連件430a及/或第二貫穿堆疊互連件430b可為不連接至額外電路組件441之專用電路路徑。此外，儘管出於清晰目的未在圖中圖解說明，但通信組件440、記憶體控制器442及/或記憶體444中之每一者可包含各種電路元 件。舉例而言，此等電路組件可包含多工器、移位暫存器、編碼器、解碼器、驅動器電路、放大器、緩衝器、暫存器、濾波器(例如，低通濾波器、高通濾波器及/或帶通濾波器)等。
圖5係圖解說明根據本發明技術之一實施例之用於操作一半導體晶粒總成之一方法570之一流程圖。在數個實施例中，可採用方法570用於操作上文詳細闡述之晶粒總成。在方塊572處，通信組件440(圖3)自封裝觸點124(圖1)接收串列資料SI之一輸入串流(「串列輸入SI」)。串列輸入SI可含有(舉例而言)資料及用以儲存資料之指令。另外或另一選擇係，串列輸入SI可含有用以讀取資料及/或抹除資料之指令。在方塊574處，通信組件440將串列輸入SI解串列化成複數個輸入串流PI1至PIX。在數個實施例中，通信組件440可包含經組態以將一串列資料串流轉換成一並列資料串流(且反之亦然)之一或多個串列化器/解串列化器電路(作為「SerDes」電路為熟習此項技術者已知)。舉例而言，串列化器/解串列化器電路兩者皆可產生且轉換具有多個信號分量(例如，四個分量信號、八個分量信號、十六個分量信號等)之並列資料串流。
在方塊576處，記憶體控制器442(圖3)經由第一貫穿堆疊互連件接收輸入串流PI1至PIX。舉例而言，記憶體控制器可經由貫穿堆疊互連件130(圖1)之一部分接收第一輸入串流PI1而同時或幾乎同時經由貫穿堆疊互連件130之另一部分接收其他輸入串流PI2至PIX。在方塊578處，記憶體控制器442處理輸入串流PI1至PIX且然後經由第二貫穿堆疊互連件選擇並存取特定記憶體。舉例而言，記憶體控制器442可藉由編碼用以擷取、儲存及/或抹除資料之指令以及一記憶體位址來選擇並存取記憶體晶粒103中之一或多者之記憶體444(圖3)。
在方塊580處，記憶體控制器442將自選定記憶體接收之一回應處理成複數個輸出串流PO1至POX。回應可包含(舉例而言)來自選定記 憶體之所請求資料、一確認回應及/或其他資訊(例如，在資料無法讀取或寫入之情況下之一錯誤回應)。在方塊582處，通信組件440經由第一貫穿堆疊互連件之至少一部分接收該複數個輸出串流PO1至POX。在方塊584處，通信組件440然後將輸出串流PO1至POX串列化成可輸出至封裝觸點124之一輸出串列資料串流SO(「串列輸出SO」)。
圖6係根據本發明技術之另一實施例組態之一半導體晶粒總成600(「總成600」)之一剖面圖。總成600可包含大體上類似於上文詳細闡述之晶粒總成之彼等特徵之特徵。舉例而言，總成600包含封圍於殼體110內之記憶體晶粒堆疊105及第二邏輯晶粒102b。然而，在圖6之所圖解說明實施例中，第一邏輯晶粒102a未附接至記憶體晶粒堆疊105。而是，第一邏輯晶粒102a安裝至一支撐基板620(例如，一印刷電路板)上之一不同位置。因此，第一邏輯晶粒102a透過延伸穿過支撐基板620、插置器122及貫穿堆疊互連件130之通信路徑電耦合至第二邏輯晶粒102b。在此實施例中，由第一邏輯晶粒102a產生之熱不透過記憶體晶粒堆疊105或第二邏輯晶粒102b耗散且因此記憶體晶粒103及第二邏輯晶粒102b可具有較低操作溫度。
可將上文參考圖1至圖6闡述之堆疊式半導體晶粒總成中之任一者併入至無數較大及/或較複雜系統中之任一者中，該等系統之一代表實例係圖7中示意性地展示之系統790。系統790可包含一半導體晶粒總成700、一電源792、一驅動器794、一處理器796及/或其他子系統或組件798。半導體晶粒總成700可包含大體上類似於上文詳細闡述之堆疊式半導體晶粒總成之彼等特徵之特徵。所得系統790可執行各種各樣之功能(諸如記憶體儲存、資料處理及/或其他適合功能)中之任一者。因此，代表系統790可無限制地包含手持式裝置(例如，行動電話、平板電腦、數位讀取器及數位音訊播放器)、電腦及電器。系統790之組件可裝納於一單個單元中或(例如，透過一通信網路)分佈於 多個經互連單元上。系統790之組件亦可包含遠端裝置及各種各樣之電腦可讀媒體中之任一者。
根據前述內容，應瞭解，本文中已出於圖解說明目的闡述了本技術之特定實施例，但可在不背離本發明之情況下做出各種修改。舉例而言，儘管關於HMC闡述了半導體晶粒總成之實施例中之諸多實施例，但在其他實施例中，半導體晶粒總成可如其他記憶體裝置或其他類型之堆疊式晶粒總成一般組態。亦可在其他實施例中組合或消除在特定實施例之內容脈絡中所闡述之本新技術之特定態樣。此外，儘管已在本新技術之特定實施例之內容脈絡中闡述與彼等實施例相關聯之優點，但其他實施例亦可展現此等優點且並非所有實施例皆必須展現此等優點以歸屬於本技術之範疇內。因此，本發明及相關聯技術可囊括本文中未明確展示或闡述之其他實施例。
100‧‧‧半導體晶粒總成/總成
102a‧‧‧第一邏輯晶粒
102b‧‧‧第二邏輯晶粒
103‧‧‧記憶體晶粒/個別記憶體晶粒
105‧‧‧堆疊/記憶體晶粒堆疊
106‧‧‧背側部分
107‧‧‧周邊部分
110‧‧‧導熱殼體/殼體
112‧‧‧蓋部分
113‧‧‧壁部分
114a‧‧‧第一界面材料
114b‧‧‧第二界面材料
116‧‧‧介電底膠填充材料/底膠填充材料
120‧‧‧封裝基板/殼體
122‧‧‧插置器
124‧‧‧封裝觸點
125‧‧‧電連接器
130‧‧‧貫穿堆疊互連件

Claims (35)

  1. 一種半導體晶粒總成，其包括：一第一邏輯晶粒，其包含複數個第一接合墊及可操作地耦合至該等第一接合墊之一記憶體控制器；一第二邏輯晶粒，其包含複數個第二接合墊、可操作地耦合至該等第二接合墊之一通信組件以及延伸超過該第一邏輯晶粒之一佔用面積(footprint)的一周邊部分；一記憶體晶粒堆疊，其位於該第二邏輯晶粒上並安置於該第一邏輯晶粒與該第二邏輯晶粒之間，其中該第一邏輯晶粒係位於該記憶體晶粒堆疊上；複數個貫穿堆疊互連件，其共同形成位於該記憶體控制器及該通信組件之間的一並列資料連結，其中該等貫穿堆疊互連件之每一者延伸穿過該記憶體晶粒堆疊之整體以將該第一邏輯晶粒之該等第一接合墊之一者連接至該第二邏輯晶粒之該等第二接合墊之相應一者；一導熱殼體，其具有在該第一邏輯晶粒之上的一蓋部分以及自該蓋部分延伸之一壁部分，其中該壁部分位於該第二邏輯晶粒之該周邊部分上，並經組態耗散在操作期間於該周邊部分產生之熱；及一熱界面材料，其將該第二邏輯晶粒之該周邊部分附接至該導熱殼體之該壁部分。
  2. 如請求項1之半導體晶粒總成，其中該通信組件包含一串列化器/解串列化器電路。
  3. 如請求項1之半導體晶粒總成，其中該導熱殼體之該蓋部分及該壁部分界定一外殼，且其中該記憶體晶粒堆疊安置於該外殼 內。
  4. 如請求項1之半導體晶粒總成，其中該第二邏輯晶粒包含一半導體基板，且其中該半導體基板不包含延伸穿過該半導體基板之任何貫穿晶粒互連件。
  5. 如請求項1之半導體晶粒總成，其中：該第一邏輯晶粒具有一第一厚度；且該第二邏輯晶粒具有小於該第一厚度之一第二厚度。
  6. 如請求項5之半導體晶粒總成，其中：該第一厚度在約300μm至約1000μm之範圍中；且該第二厚度在約50μm至約200μm之範圍中。
  7. 如請求項1之半導體晶粒總成，其中該第二邏輯晶粒經組態以將操作期間產生之該熱之一大部分經由該周邊部分耗散至該導熱殼體之該壁部分。
  8. 如請求項1之半導體晶粒總成，其中該導熱殼體之該壁部分附接至該第二邏輯晶粒之該周邊部分之一表面，其中該周邊部分之該表面朝向該第一邏輯晶粒。
  9. 如請求項1之半導體晶粒總成，其中該導熱殼體之該壁部分由該第二邏輯晶粒之該周邊部分處所攜載。
  10. 如請求項1之半導體晶粒總成，其中該導熱殼體之該壁部分包括銅。
  11. 如請求項1之半導體晶粒總成，其中該導熱殼體之該蓋部分與該壁部分為一體。
  12. 如請求項1之半導體晶粒總成，其中該第一邏輯晶粒經組態以將操作期間產生之該熱之一大部分耗散至該導熱殼體之該蓋部分。
  13. 如請求項1之半導體晶粒總成，其中該熱界面材料係一第一熱界 面材料，且半導體晶粒總成進一步包括：一第二熱界面材料，其該第一邏輯晶粒附接至該導熱殼體之該蓋部分。
  14. 如請求項1之半導體晶粒總成，其中：該記憶體晶粒堆疊中之記憶體晶粒之每一者包括一記憶體電路；該複數個貫穿堆疊互連件係複數個第一貫穿堆疊互連件；及該總成進一步包括複數個第二貫穿堆疊互連件，其中該等第二貫穿堆疊互連件之每一者形成位於該記憶體控制器及該等記憶體晶粒之一者之該記憶體電路之間的一專用電路路徑。
  15. 如請求項14之半導體晶粒總成，其中該第二邏輯晶粒包含複數個虛設觸接墊，且其中該等第二貫穿堆疊互連件之每一者耦合至該等虛設觸接墊之相應一者。
  16. 一種半導體晶粒總成，其包括：一導熱殼體，其具有一蓋部分及自該蓋部分延伸之一壁部分；一第一半導體晶粒，其具有經由一熱界面材料附接至該導熱殼體之該壁部分的一周邊部分，其中該第一半導體晶粒包含複數個第一接合墊以及可操作耦合至該等第一接合墊之一通信(communication)組件，且其中該壁部分經組態以耗散在操作期間由該第一半導體晶粒之該周邊部分產生之熱；一第二半導體晶粒，其附接至該導熱殼體之該蓋部分，其中該第二半導體晶粒包含複數個第二接合墊以及可操作耦合至該等第二接合墊之一控制器；一第三半導體晶粒堆疊，其至少部分地封圍於該導熱殼體內；及 複數個貫穿堆疊互連件，其延伸穿過該第三半導體晶粒堆疊，其中：該第三半導體晶粒堆疊安置於該第一半導體晶粒與該第二半導體晶粒之間；且該等貫穿堆疊互連件之至少一部分將該第一半導體晶粒與該第二半導體晶粒電耦合，其中該等貫穿堆疊互連件之該部分共同(collectively)形成位於該通信組件及該控制器之間的一並列資料連結。
  17. 如請求項16之半導體晶粒總成，其中該等貫穿堆疊互連件之另一部分在功能上與該第一半導體晶粒隔離。
  18. 如請求項16之半導體晶粒總成，其中該等貫穿堆疊互連件之該部分提供介於該第一半導體晶粒與該第二半導體晶粒之間之專用電路路徑。
  19. 如請求項16之半導體晶粒總成，其中：該第二半導體晶粒包含一控制器組件；且該第一半導體晶粒包含一通信組件，該通信組件經由該等貫穿堆疊互連件之該部分以可操作方式耦合至該控制器組件。
  20. 如請求項16之半導體晶粒總成，其進一步包括攜載該第一半導體晶粒之一封裝基板，其中：該封裝基板包含複數個封裝觸點；且該通信組件包含耦合於該等封裝觸點與該等貫穿堆疊互連件之該部分之間的一串列化器/解串列化器電路。
  21. 一種半導體晶粒總成，其包括：一第一邏輯晶粒，其包含一第一部分及在該第一部分周邊之一第二部分，其中該第一邏輯晶粒經組態以接收一串列資料串 流且將該串列資料串流解串列化成並列資料串流；一記憶體晶粒堆疊，其位於該第一邏輯晶粒之該第一部分上並自該第二部分偏移；一第二邏輯晶粒，其位於該記憶體晶粒堆疊上，其中該第二邏輯晶粒經組態以經由該記憶體晶粒堆疊接收該等並列資料串流；複數個貫穿堆疊互連件，其共同形成位於該第一邏輯晶粒及該第二邏輯晶粒之間的一並列資料連結，其中該等貫穿堆疊互連件之每一者延伸穿過該記憶體晶粒堆疊之整體以將該第一邏輯晶粒之一接合墊連結至該第二邏輯晶粒之一相應接合墊，且其中該第二邏輯晶粒經組態以在該並列資料連結上同時接收該等並列資料串流；及。 一導熱殼體，其具有附接至該第二邏輯晶粒之一蓋部分以及自該蓋部分延伸之一壁部分，其中該壁部分經由一熱界面材料附接至該第一邏輯晶粒之該第二部分之一表面，以耗散在操作期間由該第一邏輯晶粒產生之熱之一大部分。
  22. 如請求項21之半導體晶粒總成，其中該第一邏輯晶粒包含一記憶體控制器，該記憶體控制器經組態以經由該記憶體晶粒堆疊接收該等並列資料串流。
  23. 如請求項21之半導體晶粒總成，其進一步包括一封裝基板，其中該第一邏輯晶粒經組態以經由該封裝基板接收該串列資料串流。
  24. 一種操作一半導體晶粒總成之方法，其包括：在一第一邏輯晶粒之一第一積體電路組件處處理一信號；經由大體上垂直延伸穿過一記憶體晶粒堆疊之複數個第一通信路徑在一第二邏輯晶粒之一第二積體電路組件處接收該經處 理信號，其中該記憶體晶粒堆疊安置於該第一邏輯晶粒與該第二邏輯晶粒之間；基於該經處理信號，經由大體上垂直延伸穿過該記憶體晶粒堆疊之複數個第二通信路徑用該第二積體電路組件存取該記憶體晶粒堆疊之記憶體；及經由一導熱殼體耗散由該第一邏輯晶粒之該第一積體電路組件產生之熱，其中該導熱殼體係經由一熱界面材料附接至該第一邏輯晶粒之一周邊部分，該周邊部分延伸超過該第二邏輯晶粒之一佔用面積，其中處理該信號包含在該第一邏輯晶粒處將一串列資料串流解串列化成並列資料串流，以及在該等第一通信路徑之相應者上同時將該等並列資料串流通信至該第二積體電路組件。
  25. 如請求項24之方法，其中存取該記憶體晶粒堆疊之記憶體包含：處理該等並列資料串流以讀取、寫入及/或抹除記憶體。
  26. 如請求項24之方法，其中耗散由該第一積體電路組件產生之熱包含將熱耗散至該導熱殼體之一第一部分，該方法進一步包括：將由該第二積體電路組件產生之熱耗散至接近於該第二積體電路組件之該導熱殼體之一第二部分。
  27. 一種形成一半導體晶粒總成之方法，其包括：將一第一邏輯晶粒附接至一記憶體晶粒堆疊之一第一側；將一第二邏輯晶粒附接至該記憶體晶粒堆疊之一第二側，該第二側與該第一側相置；及將該第二邏輯晶粒及該記憶體晶粒堆疊至少部分地封圍於一導熱殼體內，其中至少部分地封圍該第二邏輯晶粒及該記憶體晶粒堆疊包含： 經由一熱界面材料將該導熱殼體之一第一部分附接至該第一邏輯晶粒之一周邊部分；及將該導熱殼體之一第二部分附接至該第二邏輯晶粒之一背側部分。
  28. 如請求項27之方法，其中至少部分地封圍該第二邏輯晶粒及該記憶體晶粒堆疊包含：將該導熱殼體之該第一部分附接接近於該第一邏輯晶粒之一通信組件；及將該導熱殼體之該第二部分附接接近於該第二邏輯晶粒之一記憶體控制器。
  29. 如請求項28之方法，其中該通信組件包含一串列化器/解串列化器電路。
  30. 一種形成一半導體晶粒總成之方法，其包括：將一記憶體晶粒堆疊安置於一第一邏輯晶粒與一導熱殼體之間；將一第二邏輯晶粒安置於該記憶體晶粒堆疊與該導熱殼體之間；穿過該記憶體晶粒堆疊形成複數個貫穿堆疊互連件以將該第一邏輯晶粒與該第二邏輯晶粒電耦合；及經由一熱界面材料將該導熱殼體之一壁部分附接至該第一邏輯晶粒之一周邊部分，該第一邏輯晶粒之該周邊部分延伸超過該第二邏輯晶粒之一佔用面積；將該導熱殼體之一蓋部分附接至該第二邏輯晶粒。
  31. 如請求項30之方法，其中形成該複數個貫穿堆疊互連件包含：將該複數個貫穿堆疊互連件電耦合至該第一邏輯晶粒之一串列化器/解串列化器電路。
  32. 如請求項31之方法，其中形成該複數個貫穿堆疊互連件進一步包含：形成該等貫穿堆疊互連件，使得該等貫穿堆疊互連件之至少一部分提供介於該串列化器/解串列化器電路與該第二邏輯晶粒之一記憶體控制器之間之一或多個專用電路路徑。
  33. 如請求項30之方法，其中該複數個貫穿堆疊互連件係第一複數個貫穿堆疊互連件，且其中該方法進一步包括：形成將該第二邏輯晶粒與該記憶體晶粒堆疊之個別記憶體晶粒電耦合之第二複數個貫穿堆疊互連件。
  34. 如請求項33之方法，其中形成該第二複數個貫穿堆疊互連件包含：形成該第二複數個貫穿堆疊互連件，使得第二複數個貫穿堆疊互連件在功能上與該第一邏輯晶粒隔離。
  35. 一種半導體系統，其包括：一混合記憶體立方體(HMC)，其包含：一第一邏輯晶粒，其包含複數個第一接合墊以及可操作耦合至該等第一接合墊之一記憶體控制器，一第二邏輯晶粒，其包含複數個第二接合墊以及可操作耦合至該等第二接合墊之一通信組件，一記憶體晶粒堆疊，其位於該第二邏輯晶粒上並安置於該第一邏輯晶粒與該第二邏輯晶粒之間，其中該第一邏輯晶粒位於該記憶體晶粒堆疊上，複數個貫穿堆疊互連件，其共同形成位於該記憶體控制器及該通信組件之間的一並列資料連結，其中該等貫穿堆疊互連件之每一者延伸穿過該記憶體晶粒堆疊之整體以將該第一邏輯晶粒之該等第一接合墊之一者連接至該第二邏輯晶粒之該等第二接合墊之相應一者，及一導熱殼體，其附接至該第一邏輯晶粒及該第二邏輯晶粒且將該記憶體晶粒堆疊封圍於一外殼內，其中該導熱殼體包 含在該第一邏輯晶粒上的一第一部分以及該第二邏輯晶粒之一周邊部分上的一第二部分；一熱界面材料，其將該第二邏輯晶粒之該周邊部分附接至該導熱殼體之該第二部分；及一驅動器，其電耦合至該第一邏輯晶粒，其中該第一邏輯晶粒將操作期間產生之熱之一大部分耗散至該導熱殼體之該第一部分，且第二邏輯晶粒將操作期間產生之該熱之一大部分經由該周邊部分及該熱界面材料耗散至該導熱殼體之該第二部分。
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