JP2017510077A - 区分された論理素子を有する積層半導体ダイアセンブリおよび関連システムと方法 - Google Patents
区分された論理素子を有する積層半導体ダイアセンブリおよび関連システムと方法 Download PDFInfo
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- JP2017510077A JP2017510077A JP2016559523A JP2016559523A JP2017510077A JP 2017510077 A JP2017510077 A JP 2017510077A JP 2016559523 A JP2016559523 A JP 2016559523A JP 2016559523 A JP2016559523 A JP 2016559523A JP 2017510077 A JP2017510077 A JP 2017510077A
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- die
- stack
- logic die
- logic
- memory
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 75
- 238000000034 method Methods 0.000 title claims abstract description 29
- 230000015654 memory Effects 0.000 claims abstract description 121
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- 238000005516 engineering process Methods 0.000 description 22
- 239000000463 material Substances 0.000 description 22
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- 229910000679 solder Inorganic materials 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
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- 239000010949 copper Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 230000008901 benefit Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
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- 238000012546 transfer Methods 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
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- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
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- 241000233805 Phoenix Species 0.000 description 1
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- 229910021393 carbon nanotube Inorganic materials 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000012777 electrically insulating material Substances 0.000 description 1
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- BIXHRBFZLLFBFL-UHFFFAOYSA-N germanium nitride Chemical compound N#[Ge]N([Ge]#N)[Ge]#N BIXHRBFZLLFBFL-UHFFFAOYSA-N 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
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Classifications
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Abstract
Description
Claims (35)
- 第一の論理ダイと、
第二の論理ダイと、
前記第一および第二の論理ダイの間に配置されたメモリダイの積層と、
を含む、
半導体ダイアセンブリ。 - 前記第一の論理ダイは、メモリコントローラを含み、
前記第二の論理ダイは、通信コンポーネントを含む、
請求項1に記載のダイアセンブリ。 - 前記通信コンポーネントは、シリアル/デシリアライザ回路を含む、
請求項2に記載のダイアセンブリ。 - 筐体を画定する熱伝導性ケーシングをさらに含み、前記メモリダイの積層は、前記筐体内に配置される、
請求項1に記載のダイアセンブリ。 - 前記第二の論理ダイは、前記熱伝導性ケーシングと前記メモリダイの積層との間に配置され、前記第二の論理ダイは、前記メモリダイの積層を介して、前記第一の論理ダイに電気的に結合される、
請求項4に記載のダイアセンブリ。 - 前記第二の論理ダイは、半導体基板を含み、前記半導体基板は、前記半導体基板を通って延びる如何なるダイ貫通相互接続も含まない、
請求項5に記載のダイアセンブリ。 - 前記第一の論理ダイは第一の厚さを有し、
前記第二の論理ダイは、前記第一の厚さよりも小さい第二の厚さを有する、
請求項1に記載のダイアセンブリ。 - 前記第一の厚さは、約50μmから約200μmの範囲内にあり、
前記第二の厚さは、約300μmから約1000μmの範囲内にある、
請求項7に記載のダイアセンブリ。 - 前記メモリダイの積層を通って延び、前記第一の論理ダイを前記第二の論理ダイと電気的に結合する複数の積層貫通相互接続をさらに含む、
請求項1に記載のダイアセンブリ。 - 前記メモリダイの積層を通って延び、前記メモリダイの積層の個々のメモリダイと前記第二の論理ダイを電気的に結合する、複数の積層貫通相互接続をさらに含む、
請求項1に記載のダイアセンブリ。 - 熱伝導性ケーシングと、
前記熱伝導性ケーシングの第一部分に取り付けられた第一の半導体ダイと、
前記第一部分から分離された前記熱伝導性ケーシングの第二部分に取り付けられた第二の半導体ダイと、
前記熱伝導性ケーシング内に少なくとも部分的に包囲された第三の半導体ダイの積層と、
前記第三の半導体ダイの積層を通って延びる複数の積層貫通相互接続と、
を含み、
前記第三の半導体ダイの積層は、前記第一および第二の半導体ダイの間に配置され、
前記積層貫通相互接続の少なくとも一部分は、前記第二の半導体ダイと前記第一の半導体ダイを電気的に結合する、
半導体ダイアセンブリ。 - 前記積層貫通相互接続の別の部分は、前記第一の半導体ダイから機能的に分離される、
請求項11に記載のダイアセンブリ。 - 前記積層貫通相互接続の前記部分は、前記第一および第二の半導体ダイの間に専用回線経路を提供する、
請求項11に記載のダイアセンブリ。 - 前記第一の半導体ダイは、コントローラコンポーネントを含み、
前記第二の半導体ダイは、前記積層貫通相互接続の前記部分を介して、前記コントローラコンポーネントに動作可能なように結合された通信コンポーネントを含む、
請求項11に記載のダイアセンブリ。 - 前記第一の半導体ダイを支持するパッケージ基板をさらに含み、
前記パッケージ基板は、複数のパッケージ接点を含み、
前記第一の半導体ダイは、前記パッケージ接点と、前記積層貫通相互接続の前記部分との間に結合されたシリアライザ/デシリアライザ回路を含む、
請求項11に記載のダイアセンブリ。 - シリアルデータストリームを受信し、前記シリアルデータストリームをパラレルデータストリームにデシリアライズするように構成された第一の論理ダイと、
メモリダイの積層と、
前記メモリダイの積層によって支持された第二の論理ダイと、
を含み、
前記第二の論理ダイは、前記メモリダイの積層を介して前記パラレルデータストリームを受信するように構成される、
半導体ダイアセンブリ。 - 前記第一の論理ダイは、前記メモリダイの積層を介して、前記パラレルデータストリームを受信するように構成されたメモリコントローラを含む、
請求項16に記載のダイアセンブリ。 - パッケージ基板をさらに含み、前記第一の論理ダイは、前記パッケージ基板を介して前記シリアルデータストリームを受信するように構成される、
請求項16に記載のダイアセンブリ。 - 前記第一の論理ダイおよび前記メモリダイの積層は、異なる位置で前記パッケージ基板に取り付けられる、
請求項18に記載のダイアセンブリ。 - 前記第一の論理ダイは、前記パッケージ基板と、前記メモリダイの積層との間に配置される、
請求項18に記載のダイアセンブリ。 - 半導体ダイアセンブリを動作させるための方法であって、
第一の論理ダイの第一の集積回路コンポーネントで信号を処理することと、
メモリダイの積層を通ってほぼ縦方向に延びる複数の第一の通信経路を介して、第二の論理ダイの第二の集積回路コンポーネントで、前記処理された信号を受信することであって、前記メモリダイの積層は、前記第一の論理ダイと前記第二の論理ダイとの間に配置される、ことと、
前記処理された信号に基づいて、前記第二の集積回路コンポーネントを用いて、前記メモリダイの積層を通ってほぼ縦方向に延びる複数の第二の通信経路を介して前記メモリダイの積層のメモリにアクセスすることと、
を含む、
方法。 - 前記信号を処理することは、シリアルデータストリームをパラレルデータストリームにデシリアライズすることを含む、
請求項21に記載の方法。 - 前記メモリダイの積層のメモリにアクセスすることは、メモリを読み出す、書き込む、および/または消去するために前記パラレルデータを処理することを含む、
請求項22に記載の方法。 - 前記第一の集積回路コンポーネントに隣接する熱伝導性ケーシングの第一部分に対して、前記第一の集積回路コンポーネントによって生成される熱を放散することと、
前記第二の集積回路コンポーネントに隣接する熱伝導性ケーシングの第二部分に対して、前記第二の集積回路コンポーネントによって生成される熱を放散することと、
をさらに含む、
請求項22に記載の方法。 - 半導体ダイアセンブリを形成するための方法であって、
メモリダイの積層の第一面に第一の論理ダイを取り付けることと、
前記第一面に対向するメモリダイの積層の第二面に、第二の論理ダイを取り付けることと、
熱伝導性ケーシング内に前記第二の論理ダイおよび前記メモリダイの積層を少なくとも部分的に包囲することと、
を含む、
方法。 - 前記第二の論理ダイおよび前記メモリダイの積層を少なくとも部分的に包囲することは、
前記第一の論理ダイの周辺部分に、前記熱伝導性ケーシングの第一部分を取り付けることと、
前記第二の論理ダイの裏面部分に、前記熱伝導性ケーシングの第二部分を取り付けることと、
を含む、
請求項25に記載の方法。 - 前記第二の論理ダイおよび前記メモリダイの積層を少なくとも部分的に包囲することは、
前記第一の論理ダイの通信コンポーネントに隣接して、前記熱伝導性ケーシングの第一部分を取り付けることと、
前記第二の論理ダイのメモリコントローラに隣接して、前記熱伝導性ケーシングの第二部分を取り付けることと、
を含む、
請求項26に記載の方法。 - 前記通信コンポーネントは、シリアライザ/デシリアライザ回路を含む、
請求項27に記載の方法。 - 半導体ダイアセンブリを形成する方法であって、
第一の論理ダイと熱伝導性ケーシングとの間にメモリダイの積層を配置することと、
前記メモリダイの積層と、前記熱伝導性ケーシングとの間に第二の論理ダイを配置することと、
前記第一の論理ダイを第二の論理ダイに電気的に結合するために、前記積層またはメモリダイを通って複数の積層貫通相互接続を形成することと、
を含む、
方法。 - 前記熱伝導性ケーシングの壁部分を前記第一の論理ダイに取り付けることと、
熱伝導性ケーシングのキャップ部分を前記第二の論理ダイに取り付けることと、
をさらに含む、
請求項29に記載の方法。 - 前記複数の積層貫通相互接続を形成することは、前記第一の論理ダイのシリアライザ/デシリアライザ回路に対して、前記複数の積層貫通相互接続を電気的に結合することを含む、
請求項29に記載の方法。 - 前記複数の積層貫通相互接続を形成することは、前記積層貫通相互接続の少なくとも一部分が前記シリアル/デシリアライザ回路と前記第二の論理ダイのメモリコントローラとの間に一つ以上の専用回線経路を提供するように、前記積層貫通相互接続を形成することをさらに含む、
請求項31に記載の方法。 - 前記複数の積層貫通相互接続は、第一の複数の積層貫通相互接続であり、前記方法は、前記第二の論理ダイを前記メモリダイの積層の個々のメモリダイと電気的に結合する第二の複数の積層貫通相互接続を形成することをさらに含む、
請求項29に記載の方法。 - 前記第二の複数の積層貫通相互接続を形成することは、第二の複数の積層貫通相互接続が前記第一の論理ダイから機能的に分離されるように、前記第二の複数の積層貫通相互接続を形成することを含む、
請求項33に記載の方法。 - 第一の論理ダイと、
第二の論理ダイと、
前記第一の論理ダイと前記第二の論理ダイとの間に配置されたメモリダイの積層と、
前記第二の論理ダイに取り付けられ、筐体内に前記メモリダイの積層を包囲する熱伝導性ケーシングと、
を含むハイブリッドメモリキューブ(HMC)と、
前記第一の論理ダイに電気的に結合されたドライバと、
を含む、
半導体システム。
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2018160490A (ja) * | 2017-03-22 | 2018-10-11 | 富士通株式会社 | 電子装置及びその製造方法、電子部品 |
Families Citing this family (52)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20150279431A1 (en) * | 2014-04-01 | 2015-10-01 | Micron Technology, Inc. | Stacked semiconductor die assemblies with partitioned logic and associated systems and methods |
US9768149B2 (en) * | 2015-05-19 | 2017-09-19 | Micron Technology, Inc. | Semiconductor device assembly with heat transfer structure formed from semiconductor material |
US11120884B2 (en) | 2015-09-30 | 2021-09-14 | Sunrise Memory Corporation | Implementing logic function and generating analog signals using NOR memory strings |
US10068875B2 (en) * | 2015-10-22 | 2018-09-04 | Micron Technology, Inc. | Apparatuses and methods for heat transfer from packaged semiconductor die |
US10090881B2 (en) * | 2015-11-13 | 2018-10-02 | Renesas Electronics Corporation | Semiconductor device |
US9881908B2 (en) * | 2016-01-15 | 2018-01-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated fan-out package on package structure and methods of forming same |
US10032695B2 (en) | 2016-02-19 | 2018-07-24 | Google Llc | Powermap optimized thermally aware 3D chip package |
WO2017171889A1 (en) * | 2016-04-02 | 2017-10-05 | Intel Corporation | Systems, methods, and apparatuses for implementing a thermal solution for 3d packaging |
CN107305861B (zh) * | 2016-04-25 | 2019-09-03 | 晟碟信息科技(上海)有限公司 | 半导体装置及其制造方法 |
US10249596B1 (en) * | 2016-06-30 | 2019-04-02 | Juniper Networks, Inc. | Fan-out in ball grid array (BGA) package |
US9918407B2 (en) * | 2016-08-02 | 2018-03-13 | Qualcomm Incorporated | Multi-layer heat dissipating device comprising heat storage capabilities, for an electronic device |
US10008395B2 (en) | 2016-10-19 | 2018-06-26 | Micron Technology, Inc. | Stacked semiconductor die assemblies with high efficiency thermal paths and molded underfill |
US10153222B2 (en) * | 2016-11-14 | 2018-12-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structures and methods of forming the same |
US11527454B2 (en) | 2016-11-14 | 2022-12-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structures and methods of forming the same |
US11397687B2 (en) * | 2017-01-25 | 2022-07-26 | Samsung Electronics Co., Ltd. | Flash-integrated high bandwidth memory appliance |
US9865570B1 (en) * | 2017-02-14 | 2018-01-09 | Globalfoundries Inc. | Integrated circuit package with thermally conductive pillar |
US10199356B2 (en) | 2017-02-24 | 2019-02-05 | Micron Technology, Inc. | Semiconductor device assembles with electrically functional heat transfer structures |
US10090282B1 (en) * | 2017-06-13 | 2018-10-02 | Micron Technology, Inc. | Semiconductor device assemblies with lids including circuit elements |
US10096576B1 (en) | 2017-06-13 | 2018-10-09 | Micron Technology, Inc. | Semiconductor device assemblies with annular interposers |
US11133261B2 (en) * | 2017-09-29 | 2021-09-28 | Intel Corporation | Electronic device packaging |
CN107993988A (zh) * | 2017-11-13 | 2018-05-04 | 芯原微电子(上海)有限公司 | 一种叠层封装结构及其制备方法 |
US10797020B2 (en) * | 2017-12-29 | 2020-10-06 | Micron Technology, Inc. | Semiconductor device assemblies including multiple stacks of different semiconductor dies |
US10424528B2 (en) * | 2018-02-07 | 2019-09-24 | Toyota Motor Engineering & Manufacturing North America, Inc. | Layered cooling structure including insulative layer and multiple metallization layers |
US10573630B2 (en) * | 2018-04-20 | 2020-02-25 | Advanced Micro Devices, Inc. | Offset-aligned three-dimensional integrated circuit |
US10510629B2 (en) * | 2018-05-18 | 2019-12-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit package and method of forming same |
US10685937B2 (en) * | 2018-06-15 | 2020-06-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit package having dummy structures and method of forming same |
FR3082656B1 (fr) | 2018-06-18 | 2022-02-04 | Commissariat Energie Atomique | Circuit integre comprenant des macros et son procede de fabrication |
GB2575038B (en) * | 2018-06-25 | 2023-04-19 | Lumentum Tech Uk Limited | A Semiconductor Separation Device |
US10672674B2 (en) | 2018-06-29 | 2020-06-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming semiconductor device package having testing pads on a topmost die |
US10840173B2 (en) | 2018-09-28 | 2020-11-17 | Juniper Networks, Inc. | Multi-pitch ball grid array |
US11594463B2 (en) * | 2018-10-11 | 2023-02-28 | Intel Corporation | Substrate thermal layer for heat spreader connection |
US11152333B2 (en) * | 2018-10-19 | 2021-10-19 | Micron Technology, Inc. | Semiconductor device packages with enhanced heat management and related systems |
US11171115B2 (en) * | 2019-03-18 | 2021-11-09 | Kepler Computing Inc. | Artificial intelligence processor with three-dimensional stacked memory |
US11836102B1 (en) | 2019-03-20 | 2023-12-05 | Kepler Computing Inc. | Low latency and high bandwidth artificial intelligence processor |
WO2020210390A1 (en) | 2019-04-09 | 2020-10-15 | Sunrise Memory Corporation | Quasi-volatile memory device with a back-channel usage |
US11043472B1 (en) | 2019-05-31 | 2021-06-22 | Kepler Compute Inc. | 3D integrated ultra high-bandwidth memory |
US11844223B1 (en) | 2019-05-31 | 2023-12-12 | Kepler Computing Inc. | Ferroelectric memory chiplet as unified memory in a multi-dimensional packaging |
US10872835B1 (en) | 2019-07-03 | 2020-12-22 | Micron Technology, Inc. | Semiconductor assemblies including vertically integrated circuits and methods of manufacturing the same |
US11139260B2 (en) * | 2019-09-17 | 2021-10-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Plurality of stacked pillar portions on a semiconductor structure |
US11004829B2 (en) | 2019-10-07 | 2021-05-11 | Sandisk Technologies Llc | Memory scaling semiconductor device |
WO2021127218A1 (en) | 2019-12-19 | 2021-06-24 | Sunrise Memory Corporation | Process for preparing a channel region of a thin-film transistor |
WO2021158994A1 (en) * | 2020-02-07 | 2021-08-12 | Sunrise Memory Corporation | Quasi-volatile system-level memory |
CN115413367A (zh) | 2020-02-07 | 2022-11-29 | 日升存储公司 | 具有低有效延迟的高容量存储器电路 |
US11507301B2 (en) | 2020-02-24 | 2022-11-22 | Sunrise Memory Corporation | Memory module implementing memory centric architecture |
US11561911B2 (en) | 2020-02-24 | 2023-01-24 | Sunrise Memory Corporation | Channel controller for shared memory access |
CN111834315A (zh) * | 2020-07-28 | 2020-10-27 | 华进半导体封装先导技术研发中心有限公司 | 一种存储器结构及其制造方法 |
US11347652B2 (en) * | 2020-08-31 | 2022-05-31 | Microsoft Technology Licensing, Llc | Banked memory architecture for multiple parallel datapath channels in an accelerator |
WO2022173700A1 (en) | 2021-02-10 | 2022-08-18 | Sunrise Memory Corporation | Memory interface with configurable high-speed serial data lanes for high bandwidth memory |
KR20220118006A (ko) | 2021-02-18 | 2022-08-25 | 에스케이하이닉스 주식회사 | 3차원 적층 구조를 갖는 반도체 패키지 |
CN113421864B (zh) * | 2021-06-11 | 2023-11-10 | 西安电子科技大学 | 三维封装相变散热装置 |
US11855006B2 (en) * | 2021-07-29 | 2023-12-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory device, package structure and fabricating method thereof |
US11791233B1 (en) | 2021-08-06 | 2023-10-17 | Kepler Computing Inc. | Ferroelectric or paraelectric memory and logic chiplet with thermal management in a multi-dimensional packaging |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011081885A (ja) * | 2009-10-09 | 2011-04-21 | Elpida Memory Inc | 半導体装置及びその制御方法並びにデータ処理システム |
US20110193229A1 (en) * | 2010-02-05 | 2011-08-11 | Samsung Electronics Co., Ltd. | Multi-Chip Package Having Semiconductor Chips Of Different Thicknesses From Each Other And Related Device |
US20120146207A1 (en) * | 2010-12-08 | 2012-06-14 | Industrial Technology Research Institute | Stacked structure and stacked method for three-dimensional chip |
WO2013074484A2 (en) * | 2011-11-14 | 2013-05-23 | Micron Technology, Inc. | Semiconductor die assemblies with enhanced thermal management, semiconductor devices including same and related methods |
WO2013119309A1 (en) * | 2012-02-08 | 2013-08-15 | Xilinx, Inc. | Stacked die assembly with multiple interposers |
Family Cites Families (34)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US435042A (en) | 1890-08-26 | Wire-fence machine | ||
TW479337B (en) * | 2001-06-04 | 2002-03-11 | Siliconware Precision Industries Co Ltd | High heat dissipation efficiency stacked-die BGA chip package structure and manufacturing process |
US7550097B2 (en) * | 2003-09-03 | 2009-06-23 | Momentive Performance Materials, Inc. | Thermal conductive material utilizing electrically conductive nanoparticles |
JP2006206721A (ja) | 2005-01-27 | 2006-08-10 | Kansai Electric Power Co Inc:The | 高耐熱合成高分子化合物及びこれで被覆した高耐電圧半導体装置 |
US20060275952A1 (en) * | 2005-06-07 | 2006-12-07 | General Electric Company | Method for making electronic devices |
US20070290333A1 (en) * | 2006-06-16 | 2007-12-20 | Intel Corporation | Chip stack with a higher power chip on the outside of the stack |
KR100874910B1 (ko) * | 2006-10-30 | 2008-12-19 | 삼성전자주식회사 | 수직형 열방출 통로를 갖는 적층형 반도체 패키지 및 그제조방법 |
US7941613B2 (en) * | 2007-05-31 | 2011-05-10 | Broadcom Corporation | Shared memory architecture |
US8064739B2 (en) * | 2007-10-23 | 2011-11-22 | Hewlett-Packard Development Company, L.P. | Three-dimensional die stacks with inter-device and intra-device optical interconnect |
US7818523B2 (en) * | 2008-01-10 | 2010-10-19 | Unity Semiconductor Corporation | Securing data in memory device |
US8787060B2 (en) | 2010-11-03 | 2014-07-22 | Netlist, Inc. | Method and apparatus for optimizing driver load in a memory package |
KR101660430B1 (ko) * | 2009-08-14 | 2016-09-27 | 삼성전자 주식회사 | 반도체 패키지 |
JP2010056139A (ja) * | 2008-08-26 | 2010-03-11 | Toshiba Corp | 積層型半導体装置 |
JP2012525627A (ja) | 2009-04-29 | 2012-10-22 | ヒューレット−パッカード デベロップメント カンパニー エル.ピー. | 光学メモリ拡張 |
JP2011142186A (ja) * | 2010-01-06 | 2011-07-21 | Toshiba Corp | 抵抗変化メモリ |
US8299608B2 (en) * | 2010-07-08 | 2012-10-30 | International Business Machines Corporation | Enhanced thermal management of 3-D stacked die packaging |
US8445918B2 (en) * | 2010-08-13 | 2013-05-21 | International Business Machines Corporation | Thermal enhancement for multi-layer semiconductor stacks |
US8796842B2 (en) * | 2010-08-20 | 2014-08-05 | Ati Technologies Ulc | Stacked semiconductor chip device with thermal management circuit board |
TWI445152B (zh) | 2010-08-30 | 2014-07-11 | Advanced Semiconductor Eng | 半導體結構及其製作方法 |
US20120074559A1 (en) * | 2010-09-24 | 2012-03-29 | International Business Machines Corporation | Integrated circuit package using through substrate vias to ground lid |
US9177609B2 (en) * | 2011-06-30 | 2015-11-03 | Sandisk Technologies Inc. | Smart bridge for memory core |
JP2013069782A (ja) | 2011-09-21 | 2013-04-18 | Toshiba Corp | 半導体装置 |
US8599595B1 (en) * | 2011-12-13 | 2013-12-03 | Michael C. Stephens, Jr. | Memory devices with serially connected signals for stacked arrangements |
TWM435042U (en) | 2012-02-23 | 2012-08-01 | Selling Ware Co Ltd | Device for dice suction and placement device and holder and nozzle therein |
TWI469312B (zh) * | 2012-03-09 | 2015-01-11 | Ind Tech Res Inst | 晶片堆疊結構及其製作方法 |
US9697147B2 (en) | 2012-08-06 | 2017-07-04 | Advanced Micro Devices, Inc. | Stacked memory device with metadata management |
US8546955B1 (en) * | 2012-08-16 | 2013-10-01 | Xilinx, Inc. | Multi-die stack package |
US9337120B2 (en) * | 2012-08-17 | 2016-05-10 | Cisco Technology, Inc. | Multi-chip module with multiple interposers |
US9583415B2 (en) * | 2013-08-02 | 2017-02-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packages with thermal interface material on the sidewalls of stacked dies |
US9076754B2 (en) * | 2013-08-02 | 2015-07-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3DIC packages with heat sinks attached to heat dissipating rings |
US9082743B2 (en) * | 2013-08-02 | 2015-07-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3DIC packages with heat dissipation structures |
KR20150058940A (ko) * | 2013-11-21 | 2015-05-29 | 삼성전자주식회사 | 히트 스프레더를 갖는 반도체 패키지 |
US20150279431A1 (en) * | 2014-04-01 | 2015-10-01 | Micron Technology, Inc. | Stacked semiconductor die assemblies with partitioned logic and associated systems and methods |
KR102287754B1 (ko) | 2014-08-22 | 2021-08-09 | 삼성전자주식회사 | 칩 적층 반도체 패키지 |
-
2014
- 2014-04-01 US US14/242,485 patent/US20150279431A1/en not_active Abandoned
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2015
- 2015-03-27 TW TW104110126A patent/TWI594258B/zh active
- 2015-03-31 KR KR1020197008435A patent/KR102076948B1/ko active IP Right Grant
- 2015-03-31 WO PCT/US2015/023677 patent/WO2015153664A1/en active Application Filing
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Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011081885A (ja) * | 2009-10-09 | 2011-04-21 | Elpida Memory Inc | 半導体装置及びその制御方法並びにデータ処理システム |
US20110193229A1 (en) * | 2010-02-05 | 2011-08-11 | Samsung Electronics Co., Ltd. | Multi-Chip Package Having Semiconductor Chips Of Different Thicknesses From Each Other And Related Device |
US20120146207A1 (en) * | 2010-12-08 | 2012-06-14 | Industrial Technology Research Institute | Stacked structure and stacked method for three-dimensional chip |
WO2013074484A2 (en) * | 2011-11-14 | 2013-05-23 | Micron Technology, Inc. | Semiconductor die assemblies with enhanced thermal management, semiconductor devices including same and related methods |
WO2013074454A2 (en) * | 2011-11-14 | 2013-05-23 | Micron Technology, Inc. | Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods |
WO2013119309A1 (en) * | 2012-02-08 | 2013-08-15 | Xilinx, Inc. | Stacked die assembly with multiple interposers |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2018160490A (ja) * | 2017-03-22 | 2018-10-11 | 富士通株式会社 | 電子装置及びその製造方法、電子部品 |
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US11562986B2 (en) | 2023-01-24 |
KR102076948B1 (ko) | 2020-02-12 |
JP2019071158A (ja) | 2019-05-09 |
KR101964507B1 (ko) | 2019-04-01 |
CN106463469B (zh) | 2020-04-28 |
EP3127149A1 (en) | 2017-02-08 |
EP3127149A4 (en) | 2017-09-20 |
JP6445586B2 (ja) | 2018-12-26 |
TWI594258B (zh) | 2017-08-01 |
SG10201912903UA (en) | 2020-02-27 |
SG11201608016YA (en) | 2016-10-28 |
KR20190034358A (ko) | 2019-04-01 |
US20200075555A1 (en) | 2020-03-05 |
KR20160138255A (ko) | 2016-12-02 |
CN106463469A (zh) | 2017-02-22 |
SG10201808497WA (en) | 2018-10-30 |
WO2015153664A1 (en) | 2015-10-08 |
JP6746667B2 (ja) | 2020-08-26 |
TW201601165A (zh) | 2016-01-01 |
US20150279431A1 (en) | 2015-10-01 |
US10978427B2 (en) | 2021-04-13 |
US20210217734A1 (en) | 2021-07-15 |
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