TWI578479B - 引線架 - Google Patents
引線架 Download PDFInfo
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- TWI578479B TWI578479B TW103100159A TW103100159A TWI578479B TW I578479 B TWI578479 B TW I578479B TW 103100159 A TW103100159 A TW 103100159A TW 103100159 A TW103100159 A TW 103100159A TW I578479 B TWI578479 B TW I578479B
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- Prior art keywords
- connecting rod
- lead frame
- lead
- retaining portion
- strength
- Prior art date
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- 238000005520 cutting process Methods 0.000 claims description 35
- 230000014759 maintenance of location Effects 0.000 claims description 14
- 238000009751 slip forming Methods 0.000 claims description 4
- 239000011159 matrix material Substances 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 description 18
- 238000000034 method Methods 0.000 description 12
- 238000005530 etching Methods 0.000 description 11
- 239000011347 resin Substances 0.000 description 6
- 229920005989 resin Polymers 0.000 description 6
- 239000002184 metal Substances 0.000 description 3
- 239000012141 concentrate Substances 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000000748 compression moulding Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
- H05K3/0052—Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
本發明係有關於用於半導體設備的引線架,特別是用於使用MAP(Molded Arrary Process,模壓陣列處理)模壓形成技術製造的QFN(Quad Flat Non-Leaded,四方形扁平無引腳封裝)半導體裝置,其中多個半導體設備統一被樹脂密封。
一種使用MAP模壓成型技術將多個半導體設備統一由樹脂密封而生產的QFN半導體設備,首先,引線架準備作為MAP引線架,該引線架中鄰近單位引線架的多個引線部份透過連接桿而彼此互連,半導體裝置係黏著於引線架的安裝部份上,且該半導體裝置以及引線架的引線係透過導線連接,接著,該引線架、該半導體裝置及該導線係以樹脂密封,隨後,該連接桿(也被稱為壩條(dam bar))藉由切割移除,因此劈開成為獨立單位引線架。
若該連接桿的厚度大,當執行切割時,旋轉刀的負載會提高,從而加速該旋轉刀的磨損,因此,切割能力劣化且可能產生切割毛邊。
JP-A-2005-166695描述一種技術,其從除了裝置安裝部
份的背側與引線的背側終端部分之外的整個壩條的背側進行半蝕刻。在此方式中,可能抑制進行切割時的旋轉刀的磨損的加速,並防止產生切割毛邊。
近年來,因為針腳的增加使半導體設備尺寸成長且為了符合半導體設備的薄化而使引線架變薄;另一方面,引線架傾向在面積上變大以增加從各個引線架獲得的單位引線架的數量;據此,如JP-A-2005-166695所述的連接桿整體於結構上變薄,產生作為該等單位引線架的連結的該連接桿及其鄰近部份無法承受外力從而導致變形的問題;該連接桿係圍繞該單位引線架而配置且包含位於縱連接桿及橫連接桿交叉處的交叉點,該單位引線架包含分隔為四個引線組(lead-group)的多個引線,該連接桿受到變形,特別是在交叉點及該引線組之間。
JP-A-2005-166695描述藉由半蝕刻讓引線架的壩條變薄的技術以及厚於經變薄部分的一部分係沿著切割方向形成於該阻礙桿上,於此種技術中,可能避免當執行切割的固定該壩條強度時切割毛邊產生;然而,於此方法中,雖然該壩條的強度已經固定,由於該較厚部份隨著該壩條連續形成,因為該旋轉刀的負載在執行切割時無法充分下降,從而造成可能產生切割毛邊的問題;此外,因為蝕刻液幾乎無法滲透入該引線及該厚於薄化部分的部分之間的部分中,使得蝕刻製程變得困難。
本發明係考量前述狀況而產生的,且本發
明的目標係提供具有連接桿的引線架,其外形可以用簡單蝕刻製程完成,藉以抑制在切割時的切割毛邊的產生,且避免該等連接桿的交叉點周圍變形。
本發明的第一態樣提供引線架,包含:配置成矩陣的多個單位引線架;沿著各該多個單位引線架的側面對齊的多個引線,該等引線的後表面係被露出;透過該鄰近該多個單位引線架的其中多個引線連接的連接桿,該連接桿包括縱連接桿、橫連接桿以及位於該縱連接桿及該橫連接桿交叉處的交叉部份;包含該連接桿及該引線的一部分的切割部分,其沿著切割線予以切除;沿著該等切割部分形成的半蝕刻部份,且其寬度小於該切割部份;以及形成於該半蝕刻部份內且僅在從該連接桿的該交叉部份延伸到鄰近該交叉部份的單位引線架之引線中最接近該交叉部份之端部引線的區域之強度保留部份。
根據本發明的第二態樣,該引線架可以被配置成使該強度保留部份包含第一強度保留部份與第二強度保留部份,該第一強度保留部份沿著該連接桿的切割方向形成,該第二強度保留部份沿著該等引線形成,且該第二強度保留部份係形成於透過該連接桿彼此連結的一對引線之間。
根據本發明的第三態樣,該引線架可以被配置成使該第一強度保留部份連續形成於該第二強度保留部份。
根據本發明的第四態樣,該引線架可以被
配置成使該第一強度保留部份具有該連接桿的四分之一至二分之一的寬度。
根據本發明的第五態樣,該引線架可以被配置成使該第二強度保留部份具有該連接桿的四分之一至二分之一的寬度。
根據本發明的第六態樣,該引線架可以被配置成使該第一強度保留部份一側的該半蝕刻部份的一端以及該引線一側的該半蝕刻部份的一端之間的距離為大於該連接桿的寬度0.5至0.75倍。
根據前述的該引線架,該切割部份以該旋轉刀所切割的金屬厚度係變薄,既然當執行的切割時施加於該旋轉刀的負載減少,切割毛邊的產生被抑制且旋轉刀的壽命延長;此外,既然該強度保留部份形成於該半蝕刻部份內且從該連接桿的該交叉部份延伸到鄰近該交叉部份的該單位引線架的該等引線中最接近該交叉部份的一端部引線,其可能增進應力最可能集中的部份的強度;因此,比起必要的是更不必要地去增加該切割部份內的金屬厚度,且避免該引線架變形;此外,隨著該引線架的強度增加,該半導體設備的尺寸成長及該引線架的薄化有所協調(harmonize);此外,既然該強度保留部分包含該第一強度保留部份以及該第二強度保留部份,該連接桿係可承受從多方向施加的應力,而且蝕刻製程在該第一強度保留部份與該引線的該被蝕刻部份的橫向端(widthwise end)之間的一部分便得簡化。
10‧‧‧引線架
11‧‧‧連接桿
11a‧‧‧交叉部份
12‧‧‧半蝕刻部份
13‧‧‧強度保留部份
13a‧‧‧第一強度保留部份
14‧‧‧引線
14a‧‧‧引線組
14b‧‧‧端部引線
15‧‧‧安裝部份
16‧‧‧半導體裝置
17‧‧‧導線
18‧‧‧樹脂
21‧‧‧連接桿
21a‧‧‧交叉部份
22‧‧‧半蝕刻部份
23‧‧‧強度保留部份
23a‧‧‧第一強度保留部份
23b‧‧‧第二強度保留部份
24a‧‧‧引線組
24b‧‧‧端部引線
E、A‧‧‧寬度
IVB-IVB、IVC-IVC‧‧‧線段
第1圖係根據本發明之第一實施例的引線架的平面圖;第2A圖係根據本發明之第一實施例顯示該引線架的連接桿的交叉部份的周圍內的背面平面圖;第2B圖係沿著第2A圖之線段IIB-IIB的剖面示意圖;第3圖係顯示根據本發明的該第一實施例的該引線架的切割處理;第4A圖係根據本發明的該第二實施例顯示引線架的連接桿的交叉點周圍背面的平面圖;第4B圖係沿著第4A圖之線段IVB-IVB的剖面示意圖;以及第4C圖係沿著第4A圖之線段IVC-IVC的剖面示意圖。
本申請案主張於2013年1月11日向日本智慧財產局申請之日本第2013-003110號專利申請案的優先權,其中所揭示之內容併入本文以供參照。
根據本發明的示範用實施例的引線架將以元件符號配合所附圖式詳細敘述。
第1圖係為根據本發明之第一實施例的引線架10之概要平面圖,該引線架10包含配置成矩陣的多個單位引線架。各單位引線架包含安裝部份15,其上安裝有半導體裝置16。該單位引線架包括多個引線14,其被分
隔成沿著該單位引線架的各邊對齊的四個引線組14a。鄰近單位引線架的該引線14係透過連接桿11連結。該連接桿11包含縱連接桿以及橫連接桿。該縱連接桿及該橫連接桿在交叉部份11a彼此交叉。如第3圖所示,虛線指示在以樹脂18密封該引線架10的一表面之後待以旋轉刀切割的切割線。在該等切割線之間的部份指示在切割處理中待切割的切割部份。
第2A圖係連接桿11的交叉部份11a的周圍的放大平面圖,該連接桿11位於該引線架10的背面處的該切割部份的寬度A內,如同在第1圖的元件符號IIA所指示。第2B圖係該連接桿11的周圍的放大剖面圖,其顯示沿著第2A圖的線段IIB-IIB的剖面。在第2A圖中,半蝕刻部份12係被劃剖面線(hatched)以方便識別。
第3圖係根據本發明的該第一實施例使用該引線架10的半導體設備的剖面圖。
於引線架10中,半蝕刻部份12係沿著該切割部份形成。此外,強度保留部份13係形成於該半蝕刻部份12內且從該連接桿11的該交叉部份11a延伸到一端部引線14b,其係鄰近該交叉部份11a的引線組14a之中最接近該交叉部份11a者。該半蝕刻部份12的寬度E小於該切割部份的寬度A。依據該半蝕刻部份12的存在,由於執行切割時之施加於該旋轉刀的負載減少,切割毛邊的產生被抑制且旋轉刀的壽命延長。若該半蝕刻部份12的寬度E大於該切割部份的寬度A,該半蝕刻部份12無法被充分切
割為小塊。因此,該引線的露出區域減少且可焊性係變差;依據本發明的第一實施例,由於形成的該半蝕刻部份12的寬度E係小於該切割部份的寬度A,該半蝕刻部份12係完全地被切成小塊,且該引線14係露出於該半導體裝置的安裝表面及其側表面,如第3圖所示。據此,當銲接處理執行時,該銲料係敷設於該引線14的該側表面,且可焊性係被提昇。
由於該強度保留部份13係形成於該半蝕刻部份12內且從該連接桿11的該交叉部份11a延伸到該端部引線14b,其係鄰近該交叉部份11a的引線組14a之中最接近該交叉部份11a者,其可能增進應力最可能集中的部份的強度。因此,比起必要的是更不必要地去增加該切割部份內的金屬厚度,且避免該引線架10變形。該強度保留部分13包含沿著該連接桿11的切割方向形成的該第一強度保留部份13a。
此處,該連接桿11的寬度係定義為a,該第一強度保留部份13a的寬度係定義為b,於該第一強度保留部份13a一側的該半蝕刻部份12的一端以及位於該引線14a一側的該半蝕刻部份12的一端之間的距離定義為d,此實施例示意一例子為a=0.1mm、b=0.05mm以及d=0.075mm。若b係0.25至0.5倍大於a,且d係0.50至0.75倍大於a,則是可應用的。
若參數b低於下限值或參數d超過上限值,亦即,若該強度保留部份13變薄或該半蝕刻部份12變寬,
其可能由於切割的變動使該強度維持部份13部份地脫離(drop out)而因此讓該引線架10的強度未受固定;此外,若該參數b超過上限值或參數d低於下限值,亦即,若該強度保留部份13變厚或該半蝕刻部份12變窄,其變得不可能去避免切割毛邊的產生。
如第3圖所示,該半導體裝置16係安裝於該引線架10的各單位引線架的該安裝部份15。該引線14及該半導體裝置16係透過導線17連結。然後,包含該半導體裝置16的該引線架10的一表面以及該導線17係利用樹脂18密封。該切割部份係以旋轉刀沿著切割線切割,因此劈開該引線架10成為個別的單位引線架。
其後,將描述依據本發明之第二實施例的引線架,特別是與根據第一實施例的引線架的不同點,第4A圖係具有位於該引線架10的背面的該切割部份的寬度A的連接桿21的交叉部份21a的周圍的放大平面圖。第4B圖係為該連接桿21周圍的放大剖面圖,其顯示沿著第4A圖的線段VIB-VIB的剖面。第4C圖係為該連接桿21的放大剖面圖,其顯示沿著第4A圖的線段VIC-VIC的剖面。
強度保留部份23係形成於半蝕刻部份22中以及從該連接桿21的該交叉部份21a延伸到端部引線24b,其係鄰近該交叉部份21a的引線組24a之中最接近該交叉部份21a者。該強度保留部份23包含第一強度保留部份23a與第二強度保留部份23b,第一強度保留部份23a沿著該連接桿21的切割方向形成,第二強度保留部份23b
沿著該引線24b形成。該第一強度保留位置23a係連續形成於該第二強度保留部份23b。如第4A圖所示,該第二強度保留部份23b係形成於透過該連接桿21相鄰地連結的引線組24之中最接近該交叉部份21a的一對最接近的引線24b之間。由於該第二強度保留部份23b之形成,該連接桿容許承受多方向施加的應力。此外,由於該單獨的第二強度保留部分23b係形成於該成對引線24b之間,其並無必要蝕刻位於該引線24b及該第一強度保留部份23a之間的一部分,該部分係蝕刻溶液幾乎無法滲透,且半蝕刻處理係只在蝕刻容易滲透的部分執行。因此蝕刻處理變得簡單。
此處,該連接桿21的寬度係定義為a,該第一強度保留部份23a的寬度係定義為b,該第二強度保留部份23b的寬度係定義為c,位於該第二強度保留部份23b一側的該半蝕刻部份22的一端以及位於該引線24a一側的該半蝕刻部份22的一端之間的距離定義為d,此實施例示意一例子為a=0.1mm、b=0.05mm、c=0.05mm及d=0.075mm。若b和c係0.25至0.5倍大於a,且d係0.50至0.75倍大於a,則是可應用的。
若參數b或c低於下限值或參數d超過上限值,亦即,若該強度保留部份23變薄或該半蝕刻部份22變寬,其可能由於切割變動使該強度維持部份23部份地脫離而因此讓該引線架10的強度未受固定。此外,若該參數b或c超過上限值或參數d低於下限值,亦即,若該強度
保留部份23變厚或該半蝕刻部份22變窄,其變得不可能去避免切割毛邊的產生。
本發明參照特定範例實施例詳盡解釋,然而,本發明並未限制於該等實施例所描述的配置,而是包含可被視為屬於本發明範疇內的其他實施例、各種變化以及修改。
10‧‧‧引線架
11‧‧‧連接桿
11a‧‧‧交叉部份
14‧‧‧引線
14a‧‧‧引線組
15‧‧‧安裝部份
A‧‧‧寬度
Claims (6)
- 一種引線架,係包括:多個單位引線架,係配置成矩陣;多個引線,沿著各該多個單位引線架的側面對齊,該等引線的後表面係被露出;連接桿,藉此將鄰近該多個單位引線架的其中多個引線連接,該連接桿包括縱連接桿、橫連接桿以及位於該縱連接桿及該橫連接桿交叉處的交叉部份;切割部分,包含該連接桿及該引線的一部分,沿著切割線予以切除;半蝕刻部份,沿著該切割部分形成,且寬度小於該切割部份;以及強度保留部份,形成於該半蝕刻部份內且僅在從該連接桿的該交叉部份延伸到鄰近該交叉部份的單位引線架之引線中最接近該交叉部份之端部引線的區域。
- 如申請專利範圍第1項所述之引線架,其中,該強度保留部份係包含第一強度保留部份與第二強度保留部份,該第一強度保留部份係沿著該連接桿的切割方向形成,該第二強度保留部份係沿著該等引線形成,且該第二強度保留部份係形成於透過該連接桿彼此連結的一對引線之間。
- 如申請專利範圍第2項所述之引線架,其中,該第一強度保留部份係連續形成於該第二強度保留部份。
- 如申請專利範圍第2項所述之引線架,其中,該第一強度保留部份具有該連接桿的四分之一至二分之一的寬度。
- 如申請專利範圍第2項所述之引線架,其中,該第二強度保留部份具有該連接桿的四分之一至二分之一的寬度。
- 如申請專利範圍第2項所述之引線架,其中,該第一強度保留部份一側的該半蝕刻部份的一端以及該引線一側的該半蝕刻部份的一端之間的距離為大於該連接桿的寬度0.5至0.75倍。
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