TWI559494B - 積體電路封裝結構 - Google Patents

積體電路封裝結構 Download PDF

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TWI559494B
TWI559494B TW101136631A TW101136631A TWI559494B TW I559494 B TWI559494 B TW I559494B TW 101136631 A TW101136631 A TW 101136631A TW 101136631 A TW101136631 A TW 101136631A TW I559494 B TWI559494 B TW I559494B
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integrated circuit
package
semiconductor wafer
circuit package
disposed
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TW201316487A (zh
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耿直 童
林子閎
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聯發科技股份有限公司
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    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
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Description

積體電路封裝結構
本發明係關於積體電路封裝結構(IC package structure)，且特別關於相鄰型疊合式封裝(side-by package-on-package)型態之一種封裝結構，其包括垂直與水平設置於一封裝基板上之數個半導體晶片。
電子裝置需要於具有較少實體空間之一積體電路封裝內封裝有更多之積體電路。其中部份技術係著重於於每一積體電路中整合有更多功能，而其他技術則著重於將此些積體電路堆疊於一單一封裝之內。當此些方法於一積體電路內提供更多之功能時，上述技術恐無法完全地解決如較低高度、較小尺寸以及成本降低等需求。
而當今行動電子裝置，例如為智慧型手機(smart phone)以及個人數位助理(PDA)等，期望於愈來愈低之成本下將愈來愈多之積體電路封裝於一愈來愈小之實體空間。目前已發展出如多晶片封裝(multi-chip package)與封裝內封裝(package-in-package，PIP)等眾多技術，以符合上述需求。
有鑑於此，本發明特提供一種新的積體電路封裝結構。
依據一實施例，本發明提供了一種積體電路封裝結構，包括：第一積體電路封裝物，其包括：第一封裝基板，具有相對之第一表面與第二表面；以及第一半導體晶片， 設置於該第一封裝基板之該第一表面之第一部分上。此外，一第二積體電路封裝，係設置於該第一封裝基板之該第一表面之不同於該第一部分之一第二部分上，包括：第二封裝基板，具有相對之第三表面與一第四表面；以及第二半導體晶片，設置於該第二封裝基板之該第三表面之一部分上，其中該第二半導體晶片具有不同於該第一半導體晶片之功能。
本發明之積體電路封裝結構具有較佳之操作效率與可靠度。
為讓本發明之上述目的、特徵及優點能更明顯易懂，下文特舉一較佳實施例，並配合所附的圖式，作詳細說明如下：
第1-4圖為一系列示意圖，顯示了可應用於行動電子裝置之積體電路封裝結構之多個實施例，其中第1、3圖顯示了分別沿第2、4圖內線段1-1與3-3之一示意剖面圖，而第2、4圖分別顯示了第1、3圖內積體電路封裝結構之一上視示意圖。如第1-4圖所示之積體電路封裝結構係做為比較例之用，藉以解說本發明之發明人所觀察到之問題，而非用於限制本發明。
請參照第1、2圖，顯示了具有相鄰封裝(side-by-side)形態之一種積體電路封裝結構(IC package substrate)100。積體電路封裝結構100包括具有相對表面A與B之一印刷電路板(PCB)101、以及設置於印刷電路板101之表面A上 之單獨的兩個積體電路封裝150與180。此外，於印刷電路板101之一部分上形成有複數個導線103。
如第1、2圖所示，積體電路封裝150與180係設置於印刷電路板101之表面A之不同部分之上，而積體電路封裝180係位於積體電路封裝150之一側。導線103係為平行導線，以做為匯流排線(bus line)之用，以電性連結積體電路封裝150與積體電路封裝180。
於一實施例中，積體電路封裝150包括具有相對表面C與D之一封裝基板151、設置於封裝基板151之表面C上之一半導體晶片153、覆蓋半導體晶片153與封裝基板151之表面C之一封裝層(encapsulate layer)155，以及設置於封裝基板153之表面D上用於電性連結對應地形成於印刷電路板101之表面A上之數個焊墊(landing pads，未顯示)之數個錫球(solder ball)157。同樣地，積體電路封裝180包括具有相對表面E與F之一封裝基板181、設置於封裝基板181之表面E上之一半導體晶片183、覆蓋半導體晶片183與封裝基板181之表面E之一封裝層185，以及設置於封裝基板181之表面F上用於電性連結對應地形成於印刷電路板101之表面A上之數個焊墊(landing pads，未顯示)之數個錫球(solder ball)187。半導體晶片183可具有不同於半導體晶片153之一功能。
於一實施例中，積體電路封裝結構100係用於一行動電子裝置之內，例如為一行動電話、一隨身數位助理(PDA)或相似物。於此實施例中，印刷電路板101可為行動電子裝置之一主機板(mother board)，而半導體晶片153可為如 微處理器(microprocessor)之一邏輯晶片(logic chip)，而半導體晶片183可為一整合型記憶晶片，其包括整合於單一半導體晶片之內之如嵌入式快閃(e-MMCTM)記憶裝置之一非揮發性記憶裝置(non-volatile memory device)以及如一低功率雙倍資料率(LPDDR)記憶裝置之一揮發性記憶裝置(volatile memory device)。然而，由於如導線103之匯流排線(bus line)係設置並形成於行動電子裝置之主機板(例如為印刷電路板101)內，因而使得半導體晶片183內之揮發性記裝置之匯排流速度(bus speed)受到限制，進而影響了積體電路封裝結構100之操作效率。
請參照第3、4圖，顯示了具有疊合型封裝(package-on-package package)形態之一種積體電路封裝結構200。積體電路封裝結構200包括具有相對表面G與H之一印刷電路板201、以及分別設置於印刷電路板201之表面G之獨立之兩個積體電路封裝250與280上。此外，於印刷電路板201之一部分上形成有數個導線203。
如第3、4圖所示，積體電路封裝250與280係設置於印刷電路板201之表面G之不同部分上，積體電路封裝250係具有疊合型封裝形態，其包括了依序堆疊印刷電路板201上之兩個子封裝250a與250b，而積體電路封裝280係位於積體電路封裝250之一側。此些導線203係為平行導線，以做為匯流排線(bus line)之用，以電性連結積體電路封裝250與積體電路封裝280。
如第3圖所示，積體電路封裝250之子封裝250a係堆疊於印刷電路板201之一部分之上，其包括了具有相對表 面I與J之一封裝基板251、設置於封裝基板251之表面I上之一半導體晶片253、覆蓋半導體晶片253以及封裝基板251之表面I之一封裝層255、以及設置於封裝基板251之表面J上用於電性連結對應地形成於印刷電路板201之表面G上之數個焊墊(landing pads，未顯示)之數個錫球(solder ball)257。此外，子封裝250b係堆疊於封裝基板251之表面I之上，其包括具有相對表面K與L之一封裝基板261、設置於封裝基板261之表面K上之一半導體晶片263、覆蓋了半導體晶片263與封裝基板261之表面K之一封裝層265、以及設置於封裝基板261之表面L上用於電性連結對應地形成於封裝基板251之表面I上之數個焊墊(landing pads，未顯示)之數個錫球(solder ball)267。在此，積體電路封裝250內之子封裝250b與子封裝250a係藉由封裝層255所相隔離，而錫球267係從環繞於半導體晶片253之至少兩側處而設置於封裝基板251之表面I之上。同樣地，積體電路封裝280包括具有相對表面M與N之一封裝基板281、設置於封裝基板281之表面M上之一半導體晶片283、覆蓋半導體晶片283與封裝基板281之表面M之一封裝層285，以及設置於封裝基板281之表面N上用於電性連結對應地形成於印刷電路板201之表面G上之數個焊墊(landing pads，未顯示)之數個(solder ball)287。在此，半導體晶片253、263與283具有不同之功能。
於一實施例中，積體電路封裝結構200係用於一行動電子裝置之內，例如為一行動電話、一隨身數位助理(PDA) 或相似物。於此實施例中，印刷電路板201可為行動電子裝置之一主機板(mother board)，而半導體晶片253可為如微處理器之一邏輯晶片，而半導體晶片263可為如一低功率雙倍資料率記憶裝置之一揮發性記憶裝置，而半導體晶片283可為如一嵌入式快閃記憶裝置之一非揮發性記憶裝置。雖然半導體晶片263之揮發性記憶裝置之匯流排速度之限制問題可藉由將半導體晶片263直接封裝於半導體晶片253之上所解決。然而，卻會引起積體電路封裝250之半導體晶片253之散熱與封裝基板251以及半導體晶片263的封裝翹曲問題，進而影響了積體電路封裝結構200之可靠度。
因此，於第5、6圖中便提供了一種較佳之積體電路封裝結構300，以克服前述之積體電路封裝結構100與200所遭遇之相關問題，其中第5圖顯示了沿第6圖內線段5-5之剖面示意圖，而第6圖顯示了如第5圖所示之積體電路封裝結構300之上視示意圖。
請參照第5、6圖，顯示了具有相鄰型疊合式封裝(side-by package-on-package)之封裝形態之一積體電路封裝結構300。此積體電路封裝結構300包括具有相對表面O與P之一印刷電路板301、設置於印刷電路板301之表面O上之一積體電路封裝350，以及設置於積體電路封裝350之一部分上之另一積體電路封裝380。
於一實施例中，積體電路封裝350包括了具有相對表面Q與R之一封裝基板351、設置於封裝基板351之表面Q之一部分上之一半導體晶片353、覆蓋半導體晶片353 以及封裝基板351之表面Q一部分之一封裝層355、以及設置於封裝基板351之表面R上用於電性連結對應地形成於印刷電路板301之表面O上之數個焊墊(landing pads，未顯示)之數個錫球(solder ball)357。此外，積體電路封裝380係自半導體晶片353之一側且設置於未為封裝層355所覆蓋之表面Q之一部分上，而於封裝基板351之一部分內形成有數個導線303。同樣地，積體電路封裝380包括具有相對表面S與T之一封裝基板381、設置於封裝基板381之表面S上之一半導體晶片383、覆蓋於半導體晶片383與封裝基板381之表面S上之一封裝層385、以及設置於封裝基板381之表面T上用於電性連結對應地形成於封裝基板351之表面Q上之數個焊墊(landing pads，未顯示)之數個錫球(solder ball)387。半導體晶片383與353具有不同功能。導線303係為平行導線，以做為匯流排線(bus line)之用，以電性連結積體電路封裝350內之半導體晶片353與積體電路封裝380。
於一實施例中，積體電路封裝結構300係用於一行動電子裝置內，例如為一行動電話、一隨身數位助理(PDA)、或相似物。於此實施例中，印刷電路板301可為行動電子裝置之一主機板(mother board)，而半導體晶片353可為如微處理器之一邏輯晶片，而半導體晶片383可為一整合型記憶晶片，其包括整合於單一半導體晶片之內之如嵌入式快閃(e-MMCTM)記憶裝置之一非揮發性記憶裝置(non-volatile memory device)以及如一低功率雙倍資料率(LPDDR)記憶裝置之一揮發性記憶裝置(volatile memory device)。
相較於第1、2圖，由於半導體晶片353係透過形成於積體電路封裝350之封裝基板351內之匯流排線而非透過如第1、2圖所示之形成於印刷電路板101內之匯流排線而電性連結位於積體電路封裝380內之半導體晶片383，因此可解決半導體晶片383內揮發性記憶裝置之匯流速度(bus speed)的限制。且相較於如第1、2圖所示之印刷電路板101內之匯流排線設計，於積體電路封裝350之封裝基板351內的匯流排線(如導線303)的設計與製造亦較為簡單。
再者，相較於如第3、4圖所示之積體電路封裝結構200，由於封裝層355此時係露出的，且沒有其他積體電路封裝形成於基底電路封裝350之上，因此對於積體電路封裝350而言，便不存在有半導體晶片353之散熱問題。
綜上所述，相較於如第1-4圖所示之積體電路封裝結構100、200言而，如第5、6圖所示之積體電路封裝結構300可具有較佳之操作效率與可靠度。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此項技藝者，在不脫離本發明之精神和範圍內，當可作更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100‧‧‧積體電路封裝結構
101‧‧‧印刷電路板
103‧‧‧導線
150‧‧‧積體電路封裝
151‧‧‧封裝基板
153‧‧‧半導體晶片
155‧‧‧封裝層
157‧‧‧錫球
180‧‧‧積體電路封裝
183‧‧‧半導體晶片
185‧‧‧封裝層
187‧‧‧錫球
200‧‧‧積體電路封裝結構
201‧‧‧印刷電路板
203‧‧‧導線
250‧‧‧積體電路封裝
250a、250b‧‧‧子封裝
251‧‧‧封裝基板
253‧‧‧半導體晶片
255‧‧‧封裝層
257‧‧‧錫球
261‧‧‧封裝基板
263‧‧‧半導體晶片
265‧‧‧封裝層
267‧‧‧錫球
280‧‧‧積體電路封裝
281‧‧‧封裝基板
283‧‧‧半導體晶片
285‧‧‧封裝層
287‧‧‧錫球
300‧‧‧積體電路封裝結構
301‧‧‧印刷電路板
303‧‧‧導線
350‧‧‧積體電路封裝
351‧‧‧封裝基板
353‧‧‧半導體晶片
355‧‧‧封裝層
357‧‧‧錫球
380‧‧‧積體電路封裝
381‧‧‧封裝基板
383‧‧‧半導體晶片
385‧‧‧封裝層
387‧‧‧錫球
A、B、C、D、E、F、G、H、I、J、K、L、M、N、O、P、Q、R、S、T‧‧‧表面
第1圖為一示意圖，顯示了依據本發明之一實施例之一種積體電路封裝結構； 第2圖為一上視示意圖，顯示了第1圖中所示之積體電路封裝結構；第3圖為一示意圖，顯示了依據本發明之另一實施例之一種積體電路封裝結構；第4圖為一上視示意圖，顯示了第3圖內所示之積體電路封裝結構；第5圖為一示意圖，顯示了依據本發明之又一實施例之一種積體電路封裝結構；第6圖為一上視示意圖，顯示了第5圖內所示之積體電路封裝結構。
300‧‧‧積體電路封裝結構
301‧‧‧印刷電路板
303‧‧‧導線
350‧‧‧積體電路封裝
351‧‧‧封裝基板
353‧‧‧半導體晶片
355‧‧‧封裝層
357‧‧‧錫球
380‧‧‧積體電路封裝
381‧‧‧封裝基板
383‧‧‧半導體晶片
385‧‧‧封裝層
387‧‧‧錫球
O、P、Q、R、S、T‧‧‧表面

Claims (7)

  1. 一種積體電路封裝結構，包括：一第一積體電路封裝，包括：一第一封裝基板，具有相對之一第一表面與一第二表面；一第一半導體晶片，設置於該第一封裝基板之該第一表面之一第一部分上；以及一封裝層，覆蓋該第一半導體晶片；一第二積體電路封裝，設置於該第一封裝基板之該第一表面之不同於該第一部分之一第二部分上，包括：一第二封裝基板，具有相對之一第三表面與一第四表面；複數個第一錫球，設置於該第二封裝基板之該第四表面上；以及一第二半導體晶片，設置於該第二封裝基板之該第三表面之一部分上，其中該第二半導體晶片具有不同於該第一半導體晶片之功能；以及數個匯流線，形成於該第一封裝基板之該第一表面之一第三部分內，該些匯流線的第一端電性連結該第一半導體晶片，而該些匯流線的第二端通過該些第一錫球電性連結該第二半導體晶片，其中該封裝層還覆蓋該些匯流線的部分。
  2. 如申請專利範圍第1項所述之積體電路封裝結構，更包括一印刷電路板，具有相對之一第五表面與一第六表面，其中該第一積體電路封裝係設置於該印刷電路板之該 第五表面之上。
  3. 如申請專利範圍第2項所述之積體電路封裝結構，更包括複數個第二錫球，設置於該第一封裝基板之該第二表面上，其中該第一積體電路封裝係透過該些第二錫球的連結而設置於該印刷電路板之該第五表面上。
  4. 如申請專利範圍第2項所述之積體電路封裝結構，其中該第二積體電路晶片係透過該些第一錫球的連結而設置於該第一封裝基板之該第一表面上。
  5. 如申請專利範圍第1項所述之積體電路封裝結構，其中該第一半導體晶片為一邏輯晶片，而該第二半導體晶片為包括有揮發性記憶裝置與非揮發性記憶裝置之一整合晶片。
  6. 如申請專利範圍第5項所述之積體電路封裝結構，其中該第一半導體晶片係為一微處理器晶片，而該第二半導體晶片包括低功率雙倍資料率記憶裝置與嵌入式快閃記憶體。
  7. 如申請專利範圍第1項所述之積體電路封裝結構，其中該第二積體電路封裝係從該第一半導體晶片之一側而堆疊於該第一積體電路封裝之上，進而形成了具有相鄰型疊合式封裝型態之一積體電路封裝結構。
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