TWI553857B - 半導體基板結構、半導體功率元件及改善半導體功率元件中之注入控制方法 - Google Patents

半導體基板結構、半導體功率元件及改善半導體功率元件中之注入控制方法 Download PDF

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TWI553857B
TWI553857B TW104117199A TW104117199A TWI553857B TW I553857 B TWI553857 B TW I553857B TW 104117199 A TW104117199 A TW 104117199A TW 104117199 A TW104117199 A TW 104117199A TW I553857 B TWI553857 B TW I553857B
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power device
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馬督兒 博德
胡軍
管靈鵬
哈姆紥 依瑪茲
張磊
金鐘五
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萬國半導體股份有限公司
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Description

半導體基板結構、半導體功率元件及改善半導體功率 元件中之注入控制方法
本發明主要是有關於一種半導體功率元件,更確切地說,是關於一種半導體功率元件的配置及其製備方法,以改善集電極-發射極飽和電壓並避免背部注入。
絕緣閘極雙極性電晶體(IGBT)是一種帶有複合結構的半導體功率元件,結合了金屬-氧化物-半導體場效應電晶體(MOSFET)和雙極接面電晶體(BJT)的特點。憑藉MOSFET的閘極電極易於控制、雙極電流機制、以及較短的切換時間和較低的功率損耗等優勢,使IGBT廣泛應用於高壓和高功率元件。
為了降低IGBT的導通電阻,已研發出場光闌(field stop)IGBT。場光闌IGBT通常在漂流區底部有一個(n-型)緩衝層,在緩衝層下方有一個很薄的注入(p-型)集電極區。集電極區的電荷數量比穿通IGBT的電荷數量要少,因此具有可控的少數載流子注入。緩衝層作為場光闌,使電場截止。對於場光闌IGBT來說,要小心地控制緩衝層 和集電極層中的電荷水平,是十分重要的。
配置和製備半導體功率元件、尤其是場光闌IGBT元件的傳統技術,在控制背層的厚度和摻雜濃度的各種取捨和不確定性方面,仍然面臨許多困難和侷限。在IGBT元件中,傳導損耗和切斷開關損耗Eoff之間存在取捨。傳導損耗依賴於額定電流下,集電極到發射極的飽和電壓Vce(SAT)。當元件接通時,載流子注入較大會提高元件的導電性,從而降低傳導損耗。然而,由於斷開時清除注入的載流子需要消耗能量,因此載流子注入升高會導致切斷開關損耗較高。對於開關損耗不占主導的應用來說,背部的載流子注入較高,可以降低傳導損耗,並且提高額定電流下集電極到發射極的飽和電壓Vce(SAT)。開關損耗不占主導的應用示例包括感測加熱、低頻電機驅動等。
用許多傳統方法可以製備帶有背部處理製程的IGBT。在一個實施例中,初始材料為一個單獨的半導體基板層(例如N型),其上方沒有額外的磊晶層。利用頂部處理製程,在基板上方製備IGBT結構。背部研磨後,利用背部N-型注入,形成一個N-型緩衝層,然後藉由P-型注入,形成底部P集電極層。背部金屬層用作汲極/集電極。該製程需要兩次背部注入操作和背部激化/退火操作。另外,由於習知的頂部IGBT結構和金屬層帶來的限制,背部層上的退火製程只能在低溫下進行。藉由在晶圓背部使用局部區域化高溫的短脈衝,雷射退火會減輕這種效果,基本不會增大晶圓頂部的溫度。然而,雷射退火通常很淺(通常為1μm量級),無法退火消除用於建立N緩衝區的較深的N注入物帶來的損害。
一個可選實施例包括N-型基板的初始材料,上方承載一個N-型磊晶層。用N-型緩衝層的體積摻雜濃度摻雜基板。藉由頂部處理製 程在基板頂部製備IGBT之後,利用背部研磨,將底部N-型基板層減至預設厚度。在理想情況下,底部N-型基板層的預設厚度與體積摻雜濃度一起,產生所需的緩衝區單位面積上的電荷水平。藉由背部P-型注入,形成底部P-型層。依次形成背部金屬層,作為汲極電極。由於N-型緩衝層已經作為初始底部基板層進行了摻雜,因此該實施例對N-型緩衝層背部研磨後,無需高溫退火。然而,這些製備製程利用嚴格控制的公差,無法精確控制背部研磨厚度,這是它們面臨的困難。N-型緩衝層厚度的變化,改變了N-型緩衝層中的電荷水平,從而對IGBT元件的性能產生不良影響。
本行業中常見的另一種IGBT稱為逆向傳導IGBT(RC-IGBT)。這種IGBT結合了元件結構中的續流二極體,從而無需將單獨的二極體芯片和IGBT封裝在一起。然而,製備RC-IGBT的傳統方法,依賴於在極薄的晶圓背部進行遮罩製程,然後進行頂部製程,使背部的厚度為2至4密耳。在這種厚度下,矽晶圓會彎曲變形,難以處理,使製備過程極其困難。
正是在這一前提下,提出了本發明的實施例。
本發明的目的在於提供一種具有高級別激化的半導體功率元件之結構及製備方法,該元件帶有深注入和改良的飽和電壓(Vcesat),適用於傳導損耗占主導的應用,確切地說,例如用於N-型元件,可以在輕摻雜P-型或N-型基板上製備一個額外的P-型層。藉由P-型層,可以控制P-型層的注入量、摻雜以及厚度。在高溫頂部製程中,可以實現100%的激化。只需要在製備背部金屬的歐姆接觸時,進行退火製程。
為了達到上述目的,本發明藉由以下技術方案實現:一種基板結構,其包括:一個第一導電類型或者與第一導電類型相反的第二導電類型之輕摻雜半導體基板;一個第一導電類型的半導體第一緩衝層,形成在輕摻雜半導體基板上方,其中第一緩衝層的摻雜濃度大於輕摻雜半導體基板的摻雜濃度;一個第二導電類型的半導體第二緩衝層,形成在第一緩衝層上方;以及一個第二導電類型的半導體磊晶層,形成在第二緩衝層上方,其中磊晶層的摻雜濃度大於第二緩衝層的摻雜濃度。
較佳地,其中第一導電類型為P-型,第二導電類型為N-型。
較佳地,更包括一個形成在磊晶層上方的第二導電類型的注入增強層,其中注入增強層的摻雜濃度大於第二導電類型的磊晶層的摻雜濃度。
較佳地,更包括一個或複數個第二導電類型的重摻雜區,穿過一部分第一緩衝層,從第二緩衝層延伸到相應的部分輕摻雜半導體基板中。
一種半導體功率元件,其包括:一個半導體基板,由第一導電類型或者與第一導電類型相反的第二導電類型的輕摻雜半導體基板構成; 一個第一導電類型的半導體第一緩衝層,形成在輕摻雜半導體基板上方,其中第一緩衝層的摻雜濃度大於輕摻雜半導體基板的摻雜濃度;一個第二導電類型的半導體第二緩衝層,形成在第一緩衝層上方;以及一個第二導電類型的半導體磊晶層,形成在第二緩衝層上方,其中磊晶層的摻雜濃度大於第二緩衝層的摻雜濃度;一個或複數個半導體功率元件結構,形成在基板結構頂部。
較佳地,其中一個或複數個半導體功率元件結構包括形成在基板結構中的一個或複數個溝槽,其中導電材料沉積在溝槽中,電介質材料沿著溝槽基材在導電材料和溝槽側壁之間。
較佳地,其中一個或複數個半導體功率元件結構更包括一個或複數個平面閘極,每個平面閘極都形成在相應的溝槽上方,絕緣層在每個平面閘極和相應的溝槽之間。
較佳地,其中一個或複數個半導體功率元件結構更包括一個或複數個第二導電類型的重摻雜接觸區,每個接觸區都被第一導電類型的本體區包圍,其中本體區形成在兩個相鄰溝槽之間的基板結構中;一個或複數個絕緣結構形成在接觸結構附近,並用絕緣材料填充。
較佳地,其中一個或複數個半導體功率元件結構包括一個或複數個絕緣閘極雙極電晶體(IGBT)元件可控矽整流器、MOS控制的可控矽整流器或反向傳導的IGBT元件。
較佳地,其中第一導電類型為P-型,第二導電類型為N-型。
較佳地,更包括一個第二導電類型的注入增強層,形成在磊晶層上方,其中注入增強層的摻雜濃度大於第二導電類型的磊晶層的摻雜濃度。
較佳地,更包括一個或複數個第二導電類型的重摻雜區,穿過一部分第一緩衝層,從第二緩衝層延伸到相應的部分輕摻雜半導體基板中。
一種改善半導體功率元件中之注入控制方法,其包括下列步驟:製備半導體基板,由一個第一導電類型或與第一導電類型相反的第二導電類型的輕摻雜半導體基板構成;在輕摻雜半導體基板上方,製備一個第一導電類型的半導體第一緩衝層,其中第一緩衝層的摻雜濃度大於輕摻雜半導體基板的摻雜濃度;在第一緩衝層上方,製備一個第二導電類型的半導體第二緩衝層;並且在第二緩衝層上方,製備一個第二導電類型的半導體磊晶層,其中磊晶層的摻雜濃度大於第二緩衝層的摻雜濃度。
較佳地,其中第一導電類型為P-型,第二導電類型為N-型。
較佳地,更包括在磊晶層上方製備一個第二導電類型的注入增強層,其中注入增強層的摻雜濃度大於磊晶層的摻雜濃度。
較佳地,其中製備第一導電類型的層,包括磊晶生長第一導電類型的層。
較佳地,其中製備第一緩衝層包括在輕摻雜的半導體基板中,全面注入第一導電類型的摻雜物。
較佳地,更包括製備一個或複數個第二導電類型的重摻雜區,穿過一部分之第一緩衝層,從第二緩衝層到對應的部分輕摻雜半導體基板中。
較佳地,其中製備一個或複數個第二導電類型的重摻雜基板區包括在一部分第一導電類型層和輕摻雜半導體基板中,帶遮罩的注入第二導電類型摻雜物。
較佳地,更包括在基板結構頂部,製備一個或複數個半導體功率元件結構。
較佳地,其中製備一個或複數個半導體功率元件結構包括在基板結構中製備一個或複數個溝槽,在溝槽中沉積導電材料,電介質材料沿著溝槽基材在導電材料和溝槽側壁之間。
較佳地,其中製備一個或複數個半導體功率元件結構更包括製備一個或複數個平面閘極極,每個平面閘極極都在相應的溝槽上方,在每個平面閘極極和相應的溝槽之間製備一個絕緣層。
較佳地,其中製備一個或複數個半導體功率元件結構更包括製備一個或複數個第二導電類型的重摻雜接觸區,其中每個接觸區都被相應的第一導電類型的本體區包圍,其中半導體形成在兩個相鄰溝槽之間的基板結構中。
較佳地,其中一個或複數個半導體功率元件結構包括一個或複數個絕緣閘極雙極電晶體(IGBT)元件可控矽整流器、MOS控制的可控矽整流器或反向傳導的IGBT元件。
本發明與習知技術相比具有以下優點:本發明揭露的一種改善半導體功率元件中之注入控制方法,半導體功率元件可以形成在基板結構上,具有第一導電類型的輕摻雜半導體基板,或與第一導電類型相反的第二導電類型。第一導電類型的半導體第一緩衝層形成在基板上方。第一緩衝層的摻雜濃度大於基板的摻雜濃度。第二導電類型的第二緩衝層形成在第一緩衝層上方,第二導電類型的磊晶層形成在第二緩衝層上方。磊晶層的摻雜濃度大於第二緩衝層的摻雜濃度。以改善集電極-發射極飽和電壓並避免背部注入。
100‧‧‧N-型IGBT元件
102‧‧‧基板
102-1‧‧‧基板
104‧‧‧P-型層
106‧‧‧N-型緩衝層
108‧‧‧N-型漂流層
109‧‧‧N-型注入增強層
112‧‧‧導電材料
113‧‧‧溝槽
114‧‧‧P-型本體區
115‧‧‧電介質材料
116‧‧‧N-型源極區
117‧‧‧絕緣層
118‧‧‧平面閘極
120‧‧‧頂部金屬層
132‧‧‧第二P-型層
134‧‧‧背部金屬層
300‧‧‧反向傳導IGBT元件
302‧‧‧基板
302-1‧‧‧基板
304‧‧‧P-型層
306‧‧‧N-型層
308‧‧‧N-型磊晶層
309‧‧‧N-型注入增強層
312‧‧‧溝槽閘極
314‧‧‧N-型源極區
316‧‧‧P-型本體區
318‧‧‧平面閘極
320‧‧‧頂部金屬層
332‧‧‧第二P-型層
334‧‧‧背部金屬層
350‧‧‧N-型區
閱讀詳細說明並參照以下圖式,本發明的特點及優勢將顯而易見:圖1表示依據本發明的一個實施例,一種半導體功率元件之剖面示意圖。
圖2A至圖2D所示之一系列剖面示意圖,表示圖1所示之元件之製備方法。
圖3表示依據本發明的一個實施例,一種半導體功率元件之剖面示意圖。
圖4A至4F所示之一系列剖面示意圖,表示圖3所示之元件之製備方法。
在以下詳細說明中,參照圖式,表示本發明可以實施的典 型實施例。就這一點而言,根據圖中所示方向,使用「頂部」、「底部」、「正面」、「背面」、「向前」、「向後」、「向上」、「向下」、「在……之上」、「在……之下」等方向術語。由於本發明之實施例的零部件,可以位於各種不同方向上,因此所用的方向術語僅用於解釋說明,不用於侷限。應明確,無需偏離本發明的範圍,就能實現其他實施例,做出結構或邏輯上的變化。因此,以下詳細說明不用於侷限,本發明的範圍應由所附的申請專利範圍限定。
共同擁有的美國專利8,283,213提出了一種半導體功率元件之結構和製備方法,其中緩衝區作為初始晶圓的一部分,在頂部製程之前就設置了其厚度和電荷水平,特此引用其全文,以作參考。確切地說,本製程從製備P-型或N-型半導體材料的輕摻雜層開始。利用磊晶生長過程,在基板上方至少形成一個緩衝層和漂流層。在基板頂部形成IGBT結構的頂部製程之後,利用背部研磨,將基板厚度減至100至120微米。藉由背部注入,形成底部集電極層。背部注入之後,接著進行低溫或快速熱退火。此後,製備背部金屬層,作為汲極/集電極。這種結構和製備製程藉由在450℃左右進行約60秒的快速熱退火,或在350℃左右進行約6小時的退火,限制了激化的量。由於頂部金屬層會在400℃融合,因此要小心地處理退火過程。不過,激化的量小於0.1%。雖然這種激化量對於開關損耗占主導的應用來說是足夠的,但是對於傳導損耗占主導的應用來說,則不夠。
提出了許複數其他方法包括從背部雷射退火,獲得侷部融化,以及矽的再結晶。雖然這些方法可以將激化量提高到100%,但是由於雷射在矽中只能貫穿1μm的數量級,因此無法應用於矽中較深處(在2.5μm及以上的範圍內)的退火損害。
本發明說明提出了一種具有高級別激化的半導體功率元件之結構及製備方法,該元件帶有深注入和改良的Vcesat,適用於傳導損耗占主導的應用,確切地說,例如用於N-型元件,可以在輕摻雜P-型或N-型基板上製備一個額外的P-型層。藉由P-型層,可以控制P-型層的注入量、摻雜以及厚度。在高溫頂部製程中,可以實現100%的激化。只需要在製備背部金屬的歐姆接觸時,進行退火製程。
本發明的其他方面提出了一種用於半導體元件之基板結構。基板結構包括一個第一導電類型的輕摻雜半導體基板,或與第一導電類型相反的第二導電類型。第一導電類型的半導體第一緩衝層形成在輕摻雜的半導體基板上方。第一緩衝層的摻雜濃度大於輕摻雜半導體基板的摻雜濃度。第二導電類型的半導體第二緩衝層形成在第一緩衝層上方。第二導電類型的半導體磊晶層形成在第二緩衝層上方,其中磊晶層的摻雜濃度大於第二緩衝層的摻雜濃度。
在某些方面,一個或複數個半導體功率元件結構形成在基板結構上方。
在一些實施例中,一個或複數個功率元件結構包括形成在磊晶層中的一個或複數個溝槽,其中導電材料沉積在溝槽中,電介質材料沿著溝槽基材在導電材料和溝槽側壁之間;一個或複數個平面閘極都形成在相應的溝槽上方,在平面閘極和相應的溝槽之間有一個絕緣層;並且一個或複數個第二導電類型的重摻雜接觸區都被第一導電類型相應的本體區包圍,其中第一導電類型的本體區形成在基板結構中,以及兩個相鄰的溝槽之間。
本發明的其他方面提出了一種製備基板和磊晶結構之方法。該方法包括製備一個基板結構,基板結構包括一個第一導電類型的 輕摻雜半導體基板,或與第一導電類型相反的第二導電類型;在輕摻雜半導體基板上方製備一個第一導電類型的第一緩衝層,其中第一緩衝層的摻雜濃度大於輕摻雜半導體基板的摻雜濃度;在第一緩衝層上方製備一個第二導電類型的半導體第二緩衝層;並且在第二緩衝層上方製備一個第二導電類型的半導體磊晶層,其中磊晶層的摻雜濃度大於第二緩衝層的摻雜濃度。
下面將結合實例詳細介紹本發明的各個方面,要理解的是本說明並不用於侷限。對於本發明所屬技術領域中具有通常知識者來說,閱讀本發明說明後,各種變化和修正無疑將顯而易見。
圖1表示依據本發明的一個方面,一種半導體功率元件。在以下說明中,以N-型元件為例,進行解釋說明。應注意的是,改變不同區域和層的導電類型極性,本發明也可適用於P-型元件。在圖1所示的示例中,元件為絕緣閘極雙極電晶體(IGBT)元件。然而,本發明所述之結構和方法並不侷限於IGBT元件,也適用於其他半導體功率元件,例如可控矽整流器、MOS控制的可控矽整流器或反向傳導的IGBT元件等。
如圖1所示,複數個N-型IGBT元件100包括形成在初始材料上方的IGBT結構,該IGBT結構包括一個基板102-1,基板102-1承載P-型層104、N-型緩衝層106、N-型漂流層108以及N-型注入增強層109。每個IGBT結構都包括填充在溝槽113中的導電材料112,由N-型注入增強層109的頂面構成,在N-型磊晶層108的頂部。溝槽113內襯電介質材料115,在導電材料112和溝槽113的側壁之間。IGBT結構更具有一個平面閘極118,位於閘極絕緣層117(例如閘極氧化物)上方。可以拉伸平面閘極,與溝槽的方向平行或正交。另外,N-型源極區 116被P-型本體區114包圍,P-型本體區114形成在鄰近溝槽113之間的N-型注入增強層109頂部。P-型本體區114在下面延伸,從N-型源極區116延伸到閘極絕緣層117下方的區域,並且遠離溝槽113的側壁,如圖1所示。在IGBT結構的頂面上沉積一個頂部金屬層120。另外,在基板102-1的背部,連接一個第二P-型層132和背部金屬層134。
圖2A至圖2D表示圖1所示半導體元件製備製程的一系列剖面圖。圖2A表示N-型、P-型或本質(intrinsic)半導體材料的輕摻雜基板102。作為示例,但不作為侷限,N-型/P-型基板102的摻雜濃度範圍為1e13至1e15cm-3(或小於1e15cm-3)。
圖2B表示P-型層104、N-型緩衝層106、N-型磊晶層108和N-型注入增強層109形成在基板102上方。在一個實施例中,進行的製程包括四步磊晶生長製程,以便在各自的上方製備這些層,如圖2B所示。確切地說,磊晶生長的第一層為P-型層104。作為示例,但不作為侷限,P-型層104的摻雜濃度約在1e15cm-3至1e18cm-3之間,高於基板102。P-型層104的厚度約為2-5μm。然後,在P-型層104上方磊晶生長一個N-型緩衝層106。作為示例,但不作為侷限,N-型緩衝層106的摻雜濃度約為1e15cm-3至1e17cm-3之間,也高於基板102。N-型層106的厚度範圍為3μm至15μm。另外,N-型磊晶層108生長在N-型緩衝層106上方。作為示例,但不作為侷限,可以用1e12cm-3至1e15cm-3之間的濃度,輕摻雜N-型磊晶層108。N-型磊晶層108的厚度範圍為30μm至150μm。最終,在N-型磊晶層108的上方,磊晶生長N-型注入增強層109。作為示例,但不作為侷限,N-型注入增強層109的摻雜濃度範圍為1e15cm-3至5e17cm-3之間,高於基板102。N-型注入增強層109的厚度範圍為2μm至5μm。作為示例,但不作為侷限,N-型摻雜物可以是磷、砷或銻,P-型摻雜物可以是硼或BF2
在另一個實施例中,該製程包括P-型摻雜物的全部注入,以製成P-型層104,然後藉由三步磊晶生長,製備N-型緩衝層106、N-型磊晶層108和N-型注入增強層109。在本實施例中,P-型層104的深度和摻雜濃度可以藉由注入能量和注入劑量控制。作為示例,但不作為侷限,藉由200KeV至1000KeV能量下,1e12至1e14cm-2劑量下的離子注入,製備P-型層104。用於製備P-型層104的摻雜物可以是硼或BF2。P-型層104的摻雜物可以藉由下文中的頂部製程的熱循環,被完全激化。
形成初始材料後,可以利用傳統的頂部製程,製備如圖2C所示的頂部IGBT結構。確切地說,藉由N-型注入增強層109和N-型磊晶層108中的刻蝕,製備溝槽113。溝槽113可以內襯電介質材料115(例如氧化物)。在一個實施例中,電介質材料115可以藉由氧化物沉積製程,形成在溝槽側壁上。此後,在溝槽113中填充導電材料(例如多晶矽),形成溝槽閘極112。在溝槽113上方製備平面閘極118,絕緣層117形成在兩者之間。在N-型注入增強層109中,製備(例如藉由注入)P-型本體區114和N-型源極區116。作為示例,但不作為侷限,P-型本體區114的摻雜濃度約為5e16cm-3至5e17cm-3之間。而且,N-型源極區116可以用1e18cm-3至1e20cm-3之間的濃度重摻雜。在頂面上,製備一個頂部金屬層120,接觸N-型源極區116和P-型本體區114。
藉由額外的製程,製備成品元件100,如圖2D所示。例如,完成頂部製程之後,進行背部研磨,將基板102的背部減薄至預設厚度的剩餘基板102-1。作為示例,基板102-1的厚度約為1μm至10μm。要注意的是,只要背部研磨製程不會一直觸及P-型層104,剩餘基板102-1的厚度就不重要。藉由背部注入,在基板102-1的背面形成第二P-型層132,並藉由低溫退火,部分激化摻雜物。此後,在底面上 製備背部金屬層134,作為汲極電極,然後藉由後期金屬退火,合成&製成歐姆接觸。
依據上述實施例,在進行製備IGBT元件的頂部金屬層的頂部製程之前,藉由磊晶生長,以結晶形式共同形成N-型緩衝層106及其摻雜物。根據實施方法,激化P-型層104,既可以在磊晶生長時激化,也可以藉由頂部製程中的熱循環激化。由於P-型或N-型層摻雜物已經被激化,因此之後無需退火過程激化摻雜物。
圖3表示依據本發明的一個方面,一種反向傳導的IGBT元件的實施例。通常來說,反向傳導的IGBT元件需要將N-型緩衝區或N-型漂流區選擇性地短接至集電極。短接會形成反並聯二極體,使IGBT中的電流反向傳導(也就是說電流從陰極/發射極端流至陽極/集電極端)。因此,重摻雜的N-型區通常嵌入在IGBT的陽極/集電極區中。應注意的是,本發明說明以N-型IGBT元件為例,進行解釋說明。改變區域和層的極性,本發明說明也適用於P-型IGBT元件。另外,在以下說明中,對於圖3和圖4A至圖4F中與圖1和圖2A至圖2D所討論的有關內容相同的元件,使用相同的末二位數字編號標記。為了簡便,參考圖1和圖2A至圖2D,並結合上述說明,下文將不再贅述這些相同元件的內容。
圖3表示複數個N-型反向傳導IGBT元件300,反向傳導IGBT元件300除了初始材料包括一個重摻雜N-型區350,用於每個反向傳導的IGBT元件之外,其他都與圖1所示之IGBT元件100基本類似。N-型區350穿過P-型層304、基板302-1和第二P-型層332延伸。N-型區350在一端與N-型層306接觸,在另一端與背部金屬層334接觸。
IGBT結構包括一個溝槽閘極312、一個平面閘極318、一個N-型源極區314、一個P-型本體區316形成在初始材料中,頂部金屬層320沉積在如圖3所示的IGBT結構的頂面上。另外,第二P-型層332和背部金屬層334形成在基板302-1的背部。第二P-型層332在基板302-1和背部金屬層334之間提供歐姆接觸。
圖4A至圖4F表示圖3所示之半導體元件的製備製程的一系列剖面圖。圖4A表示N-型、P-型或本質半導體材料的輕摻雜基板302。在一個示例中,N-型/P-型基板302的摻雜濃度範圍約在1e12至1e15cm-3之間(或小於1e15cm-3)。在一個實施例中,從藉由磊晶生長製程,在基板302中製備P-型層304開始。作為示例,但不作為侷限,P-型層304的摻雜濃度約在1e15cm-3至1e18cm-3之間,高於基板302。P緩衝層304的厚度約為2至5μm。然後,利用帶遮罩的注入,在基板302中製備重摻雜的N-型區350,如圖4C所示。作為示例,但不作為侷限,可以藉由100KeV至1000KeV的能量下,5e14至1e16cm-2的劑量下的離子注入,製備N-型區350。在另一個實施例中,藉由P-型摻雜物的全面注入,從在基板302中製備P-型層304開始準備製程。在本實施例中,P-型層304的深度和摻雜濃度可以藉由注入能量和注入劑量控制。作為示例,但不作為侷限,可以藉由200KeV至1000KeV的能量下,1e12至1e14cm-2的劑量下的離子注入,製備P-型區304。然後,藉由帶遮罩的注入,在基板302中製備N-型區350,如圖4C所示。在本實施例中,可以在製備注入的P-型層304之前,製備N-型區350。
製備P-型層304和N-型區350之後,利用三步磊晶生長,製備N-型層306、N-型磊晶層308以及N-型注入增強層309,如圖4D所示。後續製程形成頂部IGBT結構,如圖4E所示。利用額外的製程製 備成品反向傳導IGBT元件300,如圖4F所示。例如,在頂部製程之後,藉由背部研磨,將基板302的背部研磨至剩餘基板302-1。藉由背部注入,在基板102-1的底面上製備第二P-型層332,藉由低溫退火,部分激化摻雜物。然後,在底面上製備背部金屬層334,作為汲極電極。藉由背部研磨,使N-型層306電連接,產生RC效果。
下表1表示各種半導體功率元件的性能對比。元件1為基板頂部沒有P-型層的傳統元件。元件2具有電導率為0.9歐-cm、厚度為5μm的磊晶生長的P-型層。對於元件3來說,將3500KeV、5e12cm-2劑量的硼注入到基板中,製備P-型層。對於元件4來說,藉由500KeV、7.5e12cm-2劑量的注入,形成P-型層。從表中可見,本發明所述之元件(例如元件2-4)具有較低的Vce(SAT),從而提高了在感應熱開關損耗不占主導地位的應用中的性能。
儘管以上是本發明的較佳實施例的完整說明,但是也有可能使用各種可選、修正和等效方案。因此,本發明的範圍不應侷限於以上說明,而應由所附的申請專利範圍及其全部等效內容決定。本發明之方法中所述步驟的順序並不用於侷限進行相關步驟的特定順序的要求。任何可選件(無論首選與否),都可與其他任何可選件(無論首選與否) 組合。在以下申請專利範圍中,除非特別聲明,否則不定冠詞「一個」或「一種」都指下文內容中的一個或複數個項目的數量。除非在指定的申請專利範圍中用「意思是」特別指出,否則所附的申請專利範圍應認為是包括意義及功能的限制。申請專利範圍中沒有用「意思是」特別指出用於特定功能的任意項目,都不應認為是35 USC § 112(f)中具體所述的「意思」或「步驟」。
儘管本發明的內容已經藉由上述較佳實施例作了詳細介紹,但應當認識到上述的描述不應被認為是對本發明的限制。在本發明所屬技術領域中具有通常知識者閱讀了上述內容後,對於本發明的多種修改和替代都將是顯而易見的。因此,本發明的保護範圍應由所附的申請專利範圍來限定。
100‧‧‧N-型IGBT元件
102-1‧‧‧基板
104‧‧‧P-型層
106‧‧‧N-型緩衝層
108‧‧‧N-型漂流層
109‧‧‧N-型注入增強層
112‧‧‧導電材料
113‧‧‧溝槽
114‧‧‧P-型本體區
115‧‧‧電介質材料
116‧‧‧N-型源極區
117‧‧‧絕緣層
118‧‧‧平面閘極
120‧‧‧頂部金屬層
132‧‧‧第二P-型層
134‧‧‧背部金屬層

Claims (24)

  1. 一種半導體基板結構,其包括:一個第一導電類型或者與第一導電類型相反的第二導電類型之輕摻雜半導體基板;一個第一導電類型之半導體第一緩衝層,形成在該輕摻雜半導體基板上方,其中該半導體第一緩衝層的摻雜濃度大於該輕摻雜半導體基板的摻雜濃度;一個第二導電類型之半導體第二緩衝層,形成在該半導體第一緩衝層上方;以及一個第二導電類型之半導體磊晶層,形成在該半導體第二緩衝層上方,其中該半導體磊晶層的摻雜濃度大於該半導體第二緩衝層的摻雜濃度。
  2. 如申請專利範圍第1項所述之半導體基板結構,其中第一導電類型為P-型,第二導電類型為N-型。
  3. 如申請專利範圍第1項所述之半導體基板結構,其更包括一個形成在該半導體磊晶層上方的第二導電類型之注入增強層,其中該注入增強層的摻雜濃度大於第二導電類型之該半導體磊晶層的摻雜濃度。
  4. 如申請專利範圍第1項所述之半導體基板結構,其更包括一個或複數個第二導電類型之重摻雜區,穿過一部分該半導體第一緩衝層,從該半導體第二緩衝層延伸到相應的部分該輕摻雜半導體基板中。
  5. 一種半導體功率元件,其包括: 一個半導體基板,由第一導電類型或者與第一導電類型相反的第二導電類型之輕摻雜半導體基板構成;一個第一導電類型之半導體第一緩衝層,形成在該輕摻雜半導體基板上方,其中該半導體第一緩衝層的摻雜濃度大於該輕摻雜半導體基板的摻雜濃度;一個第二導電類型之半導體第二緩衝層,形成在該半導體第一緩衝層上方;以及一個第二導電類型之半導體磊晶層,形成在該半導體第二緩衝層上方,其中該半導體磊晶層的摻雜濃度大於該半導體第二緩衝層的摻雜濃度;一個或複數個半導體功率元件結構,形成在該半導體基板結構頂部。
  6. 如申請專利範圍第5項所述之半導體功率元件,其中一個或複數個半導體功率元件結構包括形成在該半導體基板結構中的一個或複數個溝槽,其中一導電材料沉積在該溝槽中,一電介質材料沿著該溝槽基材在該導電材料和該溝槽側壁之間。
  7. 如申請專利範圍第6項所述之半導體功率元件,其中一個或複數個半導體功率元件結構更包括一個或複數個平面閘極,每個平面閘極都形成在相應的該溝槽上方,一絕緣層在每個平面閘極和相應的該溝槽之間。
  8. 如申請專利範圍第7項所述之半導體功率元件,其中一個或複數個半導體功率元件結構更包括一個或複數個第二導電類型之重摻雜接觸區,每個重摻雜接觸區都被第一導電類型之一本體區包圍,其中該本體區形成在兩個相鄰該溝 槽之間的基板結構中;一個或複數個絕緣結構形成在接觸結構附近,並用絕緣材料填充。
  9. 如申請專利範圍第5項所述之半導體功率元件,其中一個或複數個半導體功率元件結構包括一個或複數個IGBT元件可控矽整流器、MOS控制的可控矽整流器或反向傳導的IGBT元件。
  10. 如申請專利範圍第5項所述之半導體功率元件,其中第一導電類型為P-型,第二導電類型為N-型。
  11. 如申請專利範圍第5項所述之半導體功率元件,更包括一個第二導電類型之注入增強層,形成在該半導體磊晶層上方,其中該注入增強層的摻雜濃度大於第二導電類型的該半導體磊晶層的摻雜濃度。
  12. 如申請專利範圍第5項所述之半導體功率元件,更包括一個或複數個第二導電類型之重摻雜區,穿過一部分該半導體第一緩衝層,從該半導體第二緩衝層延伸到相應的部分該輕摻雜半導體基板中。
  13. 一種改善半導體功率元件中之注入控制方法,其包括下列步驟:製備一半導體基板,由一個第一導電類型或與第一導電類型相反的第二導電類型之輕摻雜半導體基板構成;在該輕摻雜半導體基板上方,製備一個第一導電類型之半導體第一緩衝層,其中該半導體第一緩衝層的摻雜濃度大於該輕摻雜半導體基板的摻雜濃度; 在該半導體第一緩衝層上方,製備一個第二導電類型之半導體第二緩衝層;以及在該半導體第二緩衝層上方,製備一個第二導電類型之半導體磊晶層,其中該半導體磊晶層的摻雜濃度大於該半導體第二緩衝層的摻雜濃度。
  14. 如申請專利範圍第13項所述之改善半導體功率元件中之注入控制方法,其中第一導電類型為P-型,第二導電類型為N-型。
  15. 如申請專利範圍第13項所述之改善半導體功率元件中之注入控制方法,更包括在該半導體磊晶層上方製備一個第二導電類型之注入增強層,其中該注入增強層的摻雜濃度大於該半導體磊晶層的摻雜濃度。
  16. 如申請專利範圍第13項所述之改善半導體功率元件中之注入控制方法,其中製備第一導電類型之一層,包括磊晶生長第一導電類型之層。
  17. 如申請專利範圍第13項所述之改善半導體功率元件中之注入控制方法,其中製備該半導體第一緩衝層包括在輕摻雜之該半導體基板中,全面注入第一導電類型之一摻雜物。
  18. 如申請專利範圍第13項所述之改善半導體功率元件中之注入控制方法,其更包括製備一個或複數個第二導電類型之重摻雜基板區,穿過一部分該半導體第一緩衝層,從該半導體第二緩衝層到對應的部分該輕摻雜半導體基板中。
  19. 如申請專利範圍第18項所述之改善半導體功率元件中之注入控制方法,其中製備一個或複數個第二導電類型之該 重摻雜基板區包括在一部分第一導電類型層和該輕摻雜半導體基板中,帶遮罩的注入第二導電類型摻雜物。
  20. 如申請專利範圍第13項所述之改善半導體功率元件中之注入控制方法,其更包括在該半導體基板結構頂部,製備一個或複數個半導體功率元件結構。
  21. 如申請專利範圍第20項所述之改善半導體功率元件中之注入控制方法,其中製備一個或複數個半導體功率元件結構包括在該半導體基板結構中製備一個或複數個溝槽,在該溝槽中沉積一導電材料,一電介質材料沿著該溝槽基材在該導電材料和該溝槽側壁之間。
  22. 如申請專利範圍第21項所述之改善半導體功率元件中之注入控制方法,其中製備一個或複數個半導體功率元件結構更包括製備一個或複數個平面閘極,每個平面閘極都在相應的該溝槽上方,在每個平面閘極和相應的該溝槽之間製備一個絕緣層。
  23. 如申請專利範圍第22項所述之改善半導體功率元件中之注入控制方法,其中製備一個或複數個半導體功率元件結構更包括製備一個或複數個第二導電類型之重摻雜接觸區,其中每個重摻雜接觸區都被相應的第一導電類型之一本體區包圍,其中半導體形成在兩個相鄰該溝槽之間的該半導體基板結構中。
  24. 如申請專利範圍第20項所述之改善半導體功率元件中之注入控制方法,其中一個或複數個半導體功率元件結構包括一個或複數個IGBT元件可控矽整流器、MOS控制的可 控矽整流器或反向傳導的IGBT元件。
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