CN105322003A - 绝缘栅双极型晶体管及其制备方法 - Google Patents
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Abstract
本发明公开了一种绝缘栅双极型晶体管及其制备方法，所述绝缘栅双极型晶体管包括半导体衬底，在所述半导体衬底的正面外延生长成的N-漂移区；在上述N-漂移区上制备形成栅极和发射极的上部端子；在所述半导体衬底的背面形成集电极的下部端子；在半导体衬底表面形成栅极结构处设有刻蚀沟槽，在所述刻蚀沟槽内注入P型掺杂剂，P型掺杂剂扩散形成P型屏蔽层。本发明公开的绝缘栅双极型晶体管通过在栅极的下方加入一个P型屏蔽层，能缓解现有的IGBT导通压降大的问题，并消除关断时P型基区和N-漂移区的曲面发生的电场集中，从而能提高击穿电压，确保IGBT工作过程中的可靠性。
Description
技术领域
本发明涉及晶体管技术领域，具体涉及一种绝缘栅双极型晶体管及其制备方法。
背景技术
绝缘栅双极型晶体管(Insulated-GateBipolarTransistor:IGBT)是广泛应用于逆变器、电机驱动等高电压大电流领域的电力元器件，应具有关断时的阻断电压，即击穿电压(breakdownvoltage)高，导通压降低的特点。
图1所示的是现有技术中的IGBT结构剖面图，为了图纸的简洁明了，图1所示的剖面仅为左侧，右侧是与左侧对称的；如图1所示，为了具备高击穿电压的性能，现有技术中采用了延伸N-漂移区的物理长度或采用低浓度晶圆（衬底）的方法，但是，这会导致N-漂移区的电阻增加，从而出现导通压降增大，电力损耗加大等问题；
为了解决导通压降增大问题，通常采用的方法是减小P基区（P-base）之间的结型场效应管（JunctionField-EffectTransistor，JFET）中的电阻，但是这会导致关断（OFF）时凹入式栅极(recessedgate)出现电场增强效应（Fieldenhancementeffect）（即P基区和N-漂移区的曲面电场增强），从而导致击穿电压降低的副作用。
发明内容
针对现有技术中存在的上述缺陷，本发明公开了一种绝缘栅双极型晶体管及其制备方法，能缓解现有的IGBT导通压降大的问题，并消除关断时P型基区和N-漂移区的曲面发生的电场集中，从而能提高击穿电压，确保IGBT工作过程中的可靠性。
本发明的技术方案如下：
一种绝缘栅双极型晶体管，包括半导体衬底，在所述半导体衬底的正面外延生长成的N-漂移区；在上述N-漂移区上制备形成栅极和发射极的上部端子；在所述半导体衬底的背面形成集电极的下部端子；在半导体衬底表面形成栅极结构处设有刻蚀沟槽，在所述刻蚀沟槽内注入P型掺杂剂，P型掺杂剂扩散形成P型屏蔽层。
作为优选，所述P型屏蔽层的厚度为0.1μm～10μm；所述P型屏蔽层的浓度为1011cm-3至1019cm-3。
本发明还公开了上述绝缘栅双极型晶体管的制备方法，包括如下步骤：
S1、准备半导体衬底，在所述半导体衬底上外延生长形成预定厚度的N-漂移区，在所述半导体衬底的背面形成集电极的下部端子；
S2、对半导体衬底上表面上预定形成栅极的部分进行沟槽刻蚀，在刻蚀处内注入P型掺杂剂；
S3、在刻蚀的所述沟槽内壁上形成绝缘膜，在所述绝缘膜的表面形成由导体构成的导电栅极；
S4、在预定形成基区的部位刻蚀掉导体，并在该刻蚀部位注入P型掺杂剂；
S5、对步骤S2注入的P型掺杂剂及步骤S4注入的P型掺杂剂进行热处理，使其扩散，形成P型屏蔽层和基区；
S6、在所述N-漂移区上进行光刻加工，在光刻处注入N型掺杂物，引出形成发射极。
进一步的，所述P型掺杂剂为+3价的硼离子，通过扩散或离子注入工艺注入所述沟槽的刻蚀处。
作为优选，所述绝缘膜由可以采用二氧化硅、氧氮化硅、氮化硅、氧化铪材料中的一种或多种制成。
作为优选，所述构成导电栅极的导体由多晶硅、钨、铝中的一种或上述物质的化合物制成。
本发明公开的绝缘栅双极型晶体管通过在栅极的下方加入一个P型屏蔽层，能缓解现有的IGBT导通压降大的问题，并消除关断时P型基区和N-漂移区的曲面发生的电场集中，从而能提高击穿电压，确保IGBT工作过程中的可靠性。
附图说明
图1为现有技术中的绝缘栅双极型晶体管的剖面图；
图2为本发明的绝缘栅双极型晶体管在一实施例中的剖面图；
图3为本发明在一实施例中的工艺流程图。
具体实施方式
下面结合附图对本发明的具体实施方式做详细阐述。
如图2所示，本发明公开了一种绝缘栅双极型晶体管，包括半导体衬底2，在所述半导体衬底2的正面外延生长成的N-漂移区3；在上述N-漂移区3上制备形成栅极6和发射极7的上部端子；在所述半导体衬底2的背面形成集电极的下部端子；在半导体衬底2表面形成栅极结构处设有刻蚀沟槽，在所述刻蚀沟槽内注入P型掺杂剂，P型掺杂剂扩散形成P型屏蔽层9；
作为优选，所述P型屏蔽层9的厚度为0.1μm～10μm；所述P型屏蔽层的浓度为1011cm-3至1019cm-3，0.1μm和10μm是考虑实际IGBT实施例的尺寸和栅极的大小选择的最小厚度和最大厚度，实际上，小于0.1μm的P型屏蔽层难以实现，大于10μm的P型屏蔽层也难以通过硅的扩散实现。
本发明公开的绝缘栅双极型晶体管通过在栅极的下方加入一个P型屏蔽层，能缓解现有的IGBT导通压降大的问题，并消除关断时P型基区和N-漂移区的曲面发生的电场集中，从而能提高击穿电压，确保IGBT工作过程中的可靠性。
本发明还公开了上述绝缘栅双极型晶体管的制备方法，包括如下步骤：
S1、准备半导体衬底2，在所述半导体衬底上外延生长形成预定厚度的N-漂移区3，在所述半导体衬底2的背面形成集电极1的下部端子；
S2、对半导体衬底2上表面上预定形成栅极6的部分进行沟槽刻蚀，在刻蚀处内注入P型掺杂剂，在具体实施中，此时注入的P型掺杂剂可为+3价的硼离子，通过扩散或离子注入工艺来实现；
S3、在刻蚀的所述沟槽内壁上形成绝缘膜，在所述绝缘膜的表面形成由导体构成的导电栅极；所述绝缘膜就是栅极氧化膜，可以采用二氧化硅、氧氮化硅、氮化硅、氧化铪等材料中的一种或多种制成；所述构成导电栅极的导体由多晶硅、钨、铝中的一种或这些物质的化合物制成；
S4、在预定形成基区的部位刻蚀掉导体，并在该刻蚀部位注入P型掺杂剂，形成P型掺杂区；
S5、对步骤S2注入的P型掺杂剂及步骤S4注入的P型掺杂剂进行热处理，使其扩散，形成P型屏蔽层9和基区4；热处理工序是为了基区和P型屏蔽层的退火而进行的；
S6、在所述N-漂移区上进行光刻加工，在光刻处注入N型掺杂物，在N型掺杂区5引出形成发射极7。
如上述工艺步骤所示，本发明与现有技术公开的述绝缘栅双极型晶体管的制备方法的IGBT不同，在栅极下方插入P型屏蔽层，而且在形成栅极前，先进行沟槽蚀刻工序，蚀刻后立即注入P型掺杂物，无需使用掩膜，而且屏蔽层的形成是与热加工形成基区4同时进行的，因此能节省热预算。
以上所述的本发明实施方式，并不构成对本发明保护范围的限定。任何在本发明的精神和原则之内所作的修改、等同替换和改进等，均应包含在本发明的权利要求保护范围之内。
Claims (7)
1.一种绝缘栅双极型晶体管，其特征在于：包括半导体衬底，在所述半导体衬底的正面外延生长成的N-漂移区；在上述N-漂移区上制备形成的栅极和发射极的上部端子；在所述半导体衬底的背面形成包括集电极的下部端子；在半导体衬底表面形成栅极结构处设有刻蚀沟槽，在所述刻蚀沟槽内注入P型掺杂剂，P型掺杂剂扩散形成P型屏蔽层。
2.如权利要求1所述的绝缘栅双极型晶体管，其特征在于：所述P型屏蔽层的厚度为0.1μm～10μm。
3.如权利要求1或2所述的绝缘栅双极型晶体管，其特征在于：所述P型屏蔽层的浓度为1011cm-3至1019cm-3。
4.如权利要求1～3中任一项所述的绝缘栅双极型晶体管的制备方法，其特征在于，包括步骤：
S1、准备半导体衬底，在所述半导体衬底上外延生长形成预定厚度的N-漂移区，在所述半导体衬底的背面形成集电极的下部端子；
S2、对半导体衬底上表面上预定形成栅极的部分进行沟槽刻蚀，在刻蚀处内注入P型掺杂剂；
S3、在刻蚀的所述沟槽内壁上形成绝缘膜，在所述绝缘膜的表面形成由导体构成的导电栅极；
S4、在预定形成基区的部位刻蚀掉导体，并在该刻蚀部位注入P型掺杂剂；
S5、对步骤S2注入的P型掺杂剂及步骤S4注入的P型掺杂剂进行热处理，使其扩散，形成P型屏蔽层和基区；
S6、在所述N-漂移区上进行光刻加工，在光刻处注入N型掺杂物，引出形成发射极。
5.如权利要求4所述的绝缘栅双极型晶体管的制备方法，其特征在于：所述P型掺杂剂为+3价的硼离子，通过扩散或离子注入工艺注入所述沟槽的刻蚀处。
6.如权利要求4所述的绝缘栅双极型晶体管的制备方法，其特征在于：所述绝缘膜由可以采用二氧化硅、氧氮化硅、氮化硅、氧化铪材料中的一种或多种制成。
7.如权利要求4所述的绝缘栅双极型晶体管的制备方法，其特征在于：所述构成导电栅极的导体由多晶硅、钨、铝中的一种或上述物质的化合物制成。
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Cited By (2)
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| CN113270492A (zh) * | 2021-05-13 | 2021-08-17 | 重庆邮电大学 | 一种沟槽型GaN绝缘栅双极型晶体管 |
| CN113540224A (zh) * | 2021-07-19 | 2021-10-22 | 重庆邮电大学 | 一种N衬底沟槽型GaN绝缘栅双极型晶体管 |
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| CN113270492A (zh) * | 2021-05-13 | 2021-08-17 | 重庆邮电大学 | 一种沟槽型GaN绝缘栅双极型晶体管 |
| CN113540224A (zh) * | 2021-07-19 | 2021-10-22 | 重庆邮电大学 | 一种N衬底沟槽型GaN绝缘栅双极型晶体管 |
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