JP2019514215A - 絶縁ゲートパワー半導体デバイスおよびその製造方法 - Google Patents
絶縁ゲートパワー半導体デバイスおよびその製造方法 Download PDFInfo
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Abstract
Description
技術分野
本発明は、パワーエレクトロニクス分野に関し、特に、独立請求項1のプリアンブルに記載のデバイス、または、独立請求項12に記載の絶縁ゲートパワー半導体デバイスの製造方法に関する。
本発明の目的は、パワー半導体デバイスを提供することである。パワー半導体デバイスは、従来技術のデバイスと比較して低いオン状態損失および高い耐圧の双方を有しており、精密な製造ステップを避けた簡単で速い製造方法によって製造される。
図1では、本発明の絶縁ゲートパワー半導体デバイスの場合のエミッタ側22の構造が示されている。デバイスは、エミッタ側22のエミッタ電極2とコレクタ側27のコレクタ電極25とを備える。コレクタ側27はエミッタ側22の反対側に配置されている。(n−)ドープドリフト層5が、エミッタ側22とコレクタ側27との間に配置されている。pドープベース層4が、ドリフト層5とエミッタ側22との間に配置されている。ベース層4は、エミッタ電極2に接触する。また、ドリフト層のドーピング濃度よりも高いドーピング濃度を有するnドープソース層3もエミッタ側22に配置されている。ベース層4によってドリフト層5から分離されるソース層3は、エミッタ電極2に接触する。ソース層3は、各ゲート電極7、7’の両側に配置されるように配置可能である。
1 本発明のIGBT、10 基板、2 エミッタ電極、22エミッタ側、23 第1の側、25 コレクタ電極、27 コレクタ側、28 第2の側、3 ソース層、4 ベース層、5 ドリフト層、55 バッファ層、6 コレクタ層、7、7’ トレンチゲート電極、70 ゲート層、72 第1の絶縁層、74 第2の絶縁層、75 トレンチ側面、76 トレンチ底部、77 トレンチ深さ、 78 保護ピロー、80 トレンチ凹部、83 側面、84 凹部底面、9、9’ 保護ピロー、95 エンハンス層、97 エンハンス層深さ。
Claims (15)
- シリコン基板を主な材料とする絶縁ゲートパワー半導体デバイス(1)であって、
エミッタ側(22)のエミッタ電極(2)と前記エミッタ側(22)の反対側に配置されたコレクタ側(27)のコレクタ電極(25)と、
前記エミッタ側(22)と前記コレクタ側(27)との間に配置された、第1の導電型のドリフト層(5)と、
前記ドリフト層(5)と前記エミッタ側(22)との間に配置され、前記エミッタ電極(2)に接触する、前記第1の導電型とは異なる第2の導電型のベース層(4)と、
前記エミッタ側(22)に配置され、前記ベース層(4)によって前記ドリフト層(5)から分離され、前記エミッタ電極(2)に接触するソース層(3)と、
導電ゲート層(70)と、前記導電ゲート層(70)を取り囲んで前記ドリフト層(5)、前記ベース層(4)、および前記ソース層(3)から前記導電ゲート層(70)を分離し、トレンチ底部(76)を有するトレンチゲート電極(7、7’)と、
前記ベース層(4)を前記ドリフト層(5)から分離し、エンハンス層深さ(97)に最大エンハンス層ドーピング濃度を有する、前記ドリフト層(5)のドーピング濃度よりも高いドーピング濃度を有する前記第1の導電型のエンハンス層(95)と、
前記トレンチ底部(76)を覆う前記第2の導電型の保護ピロー(8)とを備え、
前記保護ピロー(8)と前記トレンチゲート電極(7、7’)との間のエッジ領域を覆い、最大プラズマエンハンス層ドーピング濃度を有する、前記ドリフト層(5)のドーピング濃度よりも高いドーピング濃度を有する前記第1の導電型のプラズマエンハンス層(9、9’)を備え、
前記第1の導電型のドーピング濃度は前記エンハンス層(95)と前記プラズマエンハンスメント層(9、9’)との間の局所的なドーピング濃度最小値から前記エミッタ側(22)に向けて前記最大エンハンス層ドーピング濃度まで、および、前記最大プラズマエンハンス層ドーピング濃度まで上昇し、前記プラズマエンハンス層は前記保護ピロー(8)への接合部において前記ドーピング濃度最大値を有することを特徴とする、絶縁ゲートパワー半導体デバイス。 - 前記最大エンハンス層ドーピング濃度は前記最大プラズマエンハンス層ドーピング濃度よりも高いことを特徴とする、請求項1に記載の絶縁ゲートパワー半導体デバイス。
- 前記最大エンハンス層ドーピング濃度は前記最大プラズマエンハンス層ドーピング濃度よりも少なくとも2倍高いことを特徴とする、請求項2に記載の絶縁ゲートパワー半導体デバイス。
- 前記エンハンス層(95)は、3*1016cm−3よりも低い、2.5*1016cm−3よりも低い、または2*1016cm−3よりも低い最大ドーピング濃度を有することを特徴とする、請求項1から3のいずれか1項に記載の絶縁ゲートパワー半導体デバイス。
- 前記局所的なドーピング濃度最小値は前記最大プラズマエンハンス層ドーピング濃度の半分以下であることを特徴とする、請求項1から4のいずれか1項に記載の絶縁ゲートパワー半導体デバイス。
- 前記エンハンス層(95)の厚さは3μmよりも小さい、2μmよりも小さい、または1.5μmよりも小さいことを特徴とする、請求項1から5のいずれか1項に記載の絶縁ゲートパワー半導体デバイス。
- 前記プラズマエンハンス層(9、9’)は、前記保護ピロー(8)が前記ドリフト層(5)から分離されるように前記保護ピロー(8)を取り囲むことを特徴とする、請求項1から6のいずれか1項に記載の絶縁ゲートパワー半導体デバイス。
- 前記プラズマエンハンス層(9、9’)は前記保護ピロー(8)と前記エンハンス層(95)との間のエッジを取り囲むだけであり、前記保護ピロー(8)は前記トレンチ底部(76)下方の前記ドリフト層(5)に接触することを特徴とする、請求項1から7のいずれか1項に記載の絶縁ゲートパワー半導体デバイス。
- 複数のトレンチゲート電極(7、7’)を備え、各エンハンス層ドーピング濃度プロファイルについての局所的な最大ドーピング濃度が2つの隣接するトレンチゲート電極(7、7’)間の全領域にわたって同じ深さで存在することを特徴とする、請求項1から8のいずれか1項に記載の絶縁ゲートパワー半導体デバイス。
- 複数のトレンチゲート電極(7、7’)を備え、前記トレンチゲート電極(7、7’)の各々において、前記トレンチ底部(76)を覆う保護ピロー(8)と、前記保護ピロー(8)と前記トレンチゲート電極(7、7’)との間の前記エッジ領域を取り囲むプラズマエンハンス層(9)とが配置され、2つの隣接するトレンチゲート電極(7、7’)間に配置され互いに対向する前記プラズマエンハンス層(9,9’)は、前記ドリフト層(5)によって互いに分離されていることを特徴とする、請求項1から9のいずれか1項に記載の絶縁ゲートパワー半導体デバイス。
- 複数のトレンチゲート電極(7、7’)を備え、前記トレンチ底部(76)を覆う保護ピロー(8)と、前記保護ピロー(8)と前記トレンチゲート電極(7、7’)との間の前記エッジ領域を取り囲むプラズマエンハンス層(9)とが前記トレンチゲート電極(7、7’)の各々において配置され、2つの隣接するトレンチゲート電極(7、7’)に配置され互いに対向する前記プラズマエンハンス層(9,9’)は互いに接触することを特徴とする、請求項1から10のいずれか1項に記載の絶縁ゲートパワー半導体デバイス。
- 絶縁ゲートパワー半導体デバイス(1)の製造方法であって、
(a)第1の側(23)と前記第1の側(23)と反対側の第2の側(28)とを有する、第1の導電型のシリコンを主な材料とする基板(10)を設けるステップを備え、完成したデバイスにおいて未修正のドーピング濃度を有する前記基板(10)の一部がドリフト層(5)を形成し、完成したデバイスにおいて、前記第1の側(23)がエミッタ層(22)を形成し、前記第2の側(28)がコレクタ側(27)を形成し、前記方法はさらに、
(b)前記第1の側(23)に、前記第1の導電型のエンハンス層(95)と、前記ドリフト層(5)と前記エミッタ側(22)との間に配置される、前記第1の導電型とは異なる第2の導電型のベース層(4)と、前記エミッタ側(22)に配置され前記ベース層(4)によって前記ドリフト層(5)から分離される、前記第1の導電型のソース層(3)とを形成するステップを備え、
前記エンハンス層(95)は、前記ドリフト層(5)のドーピング濃度よりも高いドーピング濃度を有し、前記ベース層(4)を前記ドリフト層〈5)から分離し、前記エンハンス層(95)はエンハンス層深さ(97)において最大エンハンス層ドーピング濃度を有し、前記方法はさらに、
(c)凹部底部(84)を有するトレンチ凹部(80)を前記基板(10)にトレンチ深さ(90)まで形成するステップと、
(d)ステップ(c)の後に、前記凹部底部(84)において前記第2の導電型のドーパントを添加するステップと、
(e)前記凹部底部(84)を覆うように、前記第2の導電型の前記ドーパントを拡散することによって保護ピロー(8)を形成するステップと、
(f)ステップ(e)の後に前記凹部(80)に第1の絶縁ゲート層(72)を形成し、前記凹部(80)に導電材料を充填して前記ゲート層(70)を形成するステップとを備え、 トレンチゲート電極(7、7’)は前記ゲート層(70)と前記第1の絶縁層(72)とを含み、前記方法はさらに、
(g)前記ベース層(4)および前記ソース層(3)と接触するエミッタ電極(2)を前記第1の側(23)に、コレクタ電極(25)を前記第2の側(28)に形成するステップを備え、
(h)ステップ(c)の後でステップ(d)の前に、前記凹部底部(84)において前記第1の導電型のドーパントを添加するステップと、
(i)ステップ(h)の後でステップ(d)の前に、前記第1の導電型の前記ドーパントを前記基板(10)に拡散することによって、最大プラズマエンハンス層ドーピング濃度を有するプラズマエンハンス層(9、9’)を形成するステップとを備え、
前記プラズマエンハンス層(9、9’)が前記保護ピロー(8)と前記トレンチゲート電極(7、7’)との間のエッジを覆うように、かつ、前記プラズマエンハンス層が前記保護ピロー(8)との接合部において前記ドーピング濃度最大値を有するように、前記第1の導電型のドーパントは前記第2の導電型のドーパントよりも前記トレンチ底部(76)から遠くまで拡散され、
前記第1の導電型のドーピング濃度が前記最大エンハンス層ドーピング濃度から前記プラズマエンハンス層(9、9’)に向けて減少するように前記エンハンス層(95)および前記プラズマエンハンス層(9、9’)が形成され、前記第1の導電型の前記ドーピング濃度が前記エンハンス層(95)と前記プラズマエンハンス層(9、9’)との間で局所的なドーピング濃度最小値を有するように前記第1の導電型のドーピング濃度が前記最大プラズマエンハンス層ドーピング濃度から前記エンハンス層(95)に向けて減少することを特徴とする、絶縁ゲートパワー半導体デバイスの製造方法。 - ステップ(b)における前記エンハンス層(95)の形成とステップ(h)およびステップ(i)における前記プラズマエンハンス層(9、9’)の形成とは、前記最大エンハンス層ドーピング濃度が完成したデバイスにおける前記最大プラズマエンハンス層ドーピング濃度よりも高くなるように行なわれることを特徴とする、請求項12に記載の方法。
- 前記最大エンハンス層ドーピング濃度は、完成したデバイスにおける前記最大プラズマエンハンス層ドーピング濃度よりも少なくとも2倍高いことを特徴とする、請求項13に記載の方法。
- ステップ(b)における前記エンハンス層(9)の形成とステップ(h)およびステップ(i)における前記プラズマエンハンス層(9、9’)の形成とは、前記局所的なドーピング濃度最小値が完成したデバイスにおける前記プラズマエンハンス層(9、9’)の前記最大ドーピング濃度の半分以下であることを特徴とする、請求項12〜14のいずれか1項に記載の方法。
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