TWI548059B - 高壓場平衡金屬氧化物場效應電晶體 - Google Patents

高壓場平衡金屬氧化物場效應電晶體 Download PDF

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TWI548059B
TWI548059B TW102126806A TW102126806A TWI548059B TW I548059 B TWI548059 B TW I548059B TW 102126806 A TW102126806 A TW 102126806A TW 102126806 A TW102126806 A TW 102126806A TW I548059 B TWI548059 B TW I548059B
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安荷 叭剌
哈姆紮 依瑪茲
馬督兒 博德
管靈鵬
胡軍
金鐘五
丁永平
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萬國半導體股份有限公司
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Description

高壓場平衡金屬氧化物場效應電晶體
本發明特別是有關於一種半導體功率器件。更確切地說，本發明係一種帶有場平衡金屬氧化物場效應電晶體(FBM)的改良型功率器件結構的新型結構和製備方法，以便承受高擊穿電壓，同時獲得很低的汲源電阻RdsA。
配置和製備高壓半導體功率器件的傳統技術出於各種權衡考慮，在進一步提升性能方面，仍然面臨許多困難與局限。在垂直半導體功率器件中，作為性能屬性的汲源電阻(即導通狀態電阻，通常用RdsA表示(即汲源電阻×主動區))，與功率器件可承受的擊穿電壓之間存在一種取捨關係。通常認可的擊穿電壓(BV)和RdsA之間的關係表示為：RdsA與BV2.5成正比。為了降低RdsA，製備的外延層摻雜濃度較高。然而，重摻雜外延層也會降低半導體功率器件可承受的擊穿電壓。
為了解決這些性能取捨帶來的困難與局限，我們嘗試了很多器件結構。美國專利4,941,026中提出了一種早期嘗試提高擊穿電壓的方式。Temple器件利用一種深溝槽，用閘極電極填充深溝槽，用厚氧化物內襯深溝槽。這種類型的器件允許更大的耗盡，從而提高漂流區的摻雜濃度。摻雜濃度越高，獲得的RdsA越低。然而，這種結構將承載幾乎全部 電壓的負擔，轉移到內襯溝槽的氧化層上。為了承載更多的電壓，就要提高氧化物厚度，這也增加了器件的壓力。因此，擊穿電壓局限於額定電壓低於200V的低壓器件。
第1圖表示一種傳統的浮動島和厚底部溝槽氧化物金屬氧化物半導體(FITMOS)場效應電晶體(FET)的剖面圖，在溝槽閘極中配置厚底部氧化物，在溝槽閘極下方配置浮動P-摻雜島，以改善電場形狀。浮動島中的P-摻雜物的電荷補償，可以提高N-外延摻雜濃度，從而降低RdsA。另外，溝槽閘極中的厚底部氧化物降低了閘汲耦合，從而降低了閘汲電荷Qgd。在頂部外延層和浮動島附近的下層上，器件還具有承載較高擊穿電壓的優勢。然而，存在浮動P-區，會在開關時產生較高的動態導通電阻。
在美國專利7,291,894中，Sapp等人提出了一種保持高BV的功率電晶體，同時降低了器件的閘汲電容(Cgd)。在Sapp電晶體中，透過用氧化物代替溝槽閘極，降低了Cgd。為了補充刪除電極引起的BV降低，要在製備氧化物之前，用P-型摻雜物摻雜溝槽壁。雖然這種P-摻雜區提供了一種電荷平衡機制，可以恢復因刪除溝槽電極引起的BV損失，但是必須獲得實際的電荷平衡，以承受高擊穿。與之類似，美國專利6,762,455中Oppermann等人提出的器件，也是利用氧化物填充的溝槽。在Oppermann器件中，可以像Sapp那樣摻雜溝槽側壁，但是Oppermann還提出了一個下部P-摻雜區形成在溝槽下方。但是，這也會像Sapp器件一樣，受到相同的局限。溝槽中沒有電極，要實現高擊穿的話，會對真實的電荷平衡產生很大的壓力。
在美國專利5,637,898中，Baliga提出了一種功率電晶體，設計目標是具有高擊穿電壓和低導通狀態電阻。這種Baliga功率電晶體是 一種在半導體襯底中的垂直場效應電晶體，包括一個底部在漂流區中的溝槽以及絕緣閘電極，用於根據所載入的導通閘極偏壓，調製通道和漂流區的導電性。絕緣閘電極包括一個在溝槽中的導電閘極，以及一個內襯通道和漂流區附近的溝槽側壁的絕緣區。絕緣區在溝槽側壁和閘極之間，具有不均勻的剖面面積。透過防止在溝槽底部發生高電場擁擠，提高了電晶體的正向電壓閉鎖性能。絕緣區沿漂流區附近延伸的那部分側壁的厚度較大，沿通道區附近延伸的那部分側壁的厚度較小。漂流區也是非均勻摻雜，具有線性分級的摻雜結構，從漂流區到通道區的方向上降低，提供很低的導通狀態電阻。這種器件的電荷補償是通道閘極電極實現的。然而，存在很大的閘極電極，可以顯著增大這種結構的閘汲電容，導致較高的開關損耗。另外，這種Baliga器件在漂流區中具有線性分級的摻雜結構，造成了額外的製備複雜性。
在美國專利7,335,944中，Banerjee等人提出了一種電晶體，包括第一和第二溝槽，限定了一個在半導體襯底中的臺面結構。第一和第二場板部分分別沉積在第一和第二溝槽中，透過厚電介質層，每個第一和第二場板部分都與臺面結構分隔開。臺面結構包括多個部分，每個部分都具有基本恆定的摻雜濃度梯度，一個部分的梯度至少比另一個部分的梯度大10%，也就是說，漂流區中的摻雜結構梯度的變化，作為漂流區垂直深度的函數。每個場板都電連接到源極電極。在這種器件中，透過連接到源極上的場板，獲得電荷平衡。但是，製備這種器件需要十分複雜的製備製程，包括深溝槽、厚襯裏氧化物以及摻雜濃度梯度等。
美國專利7,649,223中，Kawashima提出了一種部分超級結器件。超級結晶體管提供了一種獲得低RdsA，同時保持高BV的方式。超級結器件含有交替的P-型和N-型摻雜立柱，形成在漂流區中。在MOSFET斷開狀態中，立柱在很低的電壓下完全耗盡，從而可以承受很高 的擊穿電壓。在這種Kawashima器件中，P-摻雜立柱部分形成在N-摻雜外延層的深度中，其中MOSFET器件結構形成在N-摻雜外延層中。對於超級結來說，RdsA的增大與BV成正比，它比傳統的半導體結構增幅要小。但是，超級結器件需要複雜的製程和許多額外的掩膜步驟，因此製造成本比較昂貴。
基於上述原因，有必要提出半導體功率器件的新型器件結構和製備方法，實現降低導通狀態電阻，同時增大功率器件可承受的擊穿電壓，從而解決上述難題與局限。
關於新型改良的半導體功率器件結構及製備方法，用於製備帶有低RdsA和很高的可承受擊穿電壓的半導體功率器件，本發明的實施例可以克服原有技術的缺點。
確切地說，本發明的一個方面在於，提出了一種新型改良的器件結構及製備方法，透過在半導體襯底的頂面附近製備重摻雜外延層，然後在重摻雜外延層中製備內襯氧化物的溝槽並用導電材料填充，用於製備低RdsA的半導體功率器件。溝槽中的導電材料，透過形成在每個源極溝槽下方的掩埋P-區，連接到源極電極，作為重摻雜漂流區的電荷補償層，使它可以承載高壓，同時保持很低的串聯電阻。
本發明的另一方面在於，提出了一種新型改良的器件結構及製備方法，用於製備含有頂部結構的半導體功率器件，用作帶有電荷補償漂流區的MOSFET，還提供由導電材料(例如多晶矽)填充的溝槽，連接到源極電極，並且包括掩埋P-區，部分導電溝槽在溝槽側壁附近具有P-摻雜區，使掩埋P-區放電。
本發明的另一方面在於，提出了一種新型改良的器件結構及製備方法，用於製備含有頂部結構的半導體功率器件，用作帶有電荷補償漂流區的MOSFET，還提供由導電材料(例如多晶矽)填充的溝槽，連接到源極電極，並且包括掩埋P-區，導電溝槽具有P-摻雜區包圍著每個溝槽側壁。
簡言之，依據較佳實施例，半導體功率器件形成在半導體襯底中，在重摻雜區承載的輕摻雜區上方的半導體襯底頂面附近具有一個重摻雜區。半導體功率器件還包括一個源極區和一個閘極區，沉積在半導體襯底頂面附近，以及一個汲極區沉積在半導體襯底的底面上。半導體功率器件還包括在重摻雜區中打開的源極溝槽，內襯電介質，然後用導電溝槽填充材料填充，導電溝槽填充材料與頂面附近的源極區電接觸。半導體功率器件還包括掩埋P-區，沉積在源極溝槽底部，用導電類型與重摻雜區相反的摻雜物摻雜。
在一個較佳實施例中，半導體功率器件還包括摻雜區，源極溝槽的側壁包圍著摻雜區，並用導電類型與掩埋P-區相同的摻雜物摻雜，使掩埋P-區放電。
200‧‧‧FBM器件
201‧‧‧FBM器件
202‧‧‧重摻雜區
203‧‧‧電壓閉鎖區
204‧‧‧表面遮罩區
205‧‧‧汲極電極
206‧‧‧本體區
206’‧‧‧重摻雜P+接頭
207‧‧‧電介質層
207‧‧‧氧化物
208‧‧‧源極區
209‧‧‧輕摻雜耗盡區
211‧‧‧遮罩電極
212‧‧‧閘極電極
214‧‧‧源極電極
219‧‧‧P-鏈接
225‧‧‧溝槽
229‧‧‧小窗
A‧‧‧位置
B‧‧‧位置
400‧‧‧FBM
408‧‧‧源極區
409‧‧‧掩埋P-區
441‧‧‧電流
445‧‧‧電晶體
500‧‧‧FBM器件
503‧‧‧電壓閉鎖區
504‧‧‧表面遮罩區
504‧‧‧N-型外延半導體層
506’‧‧‧P+注入接頭
507‧‧‧生長氧化層
509‧‧‧掩埋P-區
511‧‧‧填充材料
519‧‧‧P-鏈接
525‧‧‧溝槽
529‧‧‧P-鏈接掩膜
535‧‧‧溝槽掩膜
604‧‧‧表面遮罩區
606’‧‧‧P+注入接頭
607‧‧‧絕緣材料
609‧‧‧掩埋P-區
611‧‧‧填充材料
619‧‧‧P-鏈接
625‧‧‧溝槽
635‧‧‧溝槽掩膜
700‧‧‧FBM器件
703‧‧‧輕摻雜電壓閉鎖區
704‧‧‧表面遮罩區
704’‧‧‧表面遮罩區
704”‧‧‧表面遮罩區
709‧‧‧掩埋P-區
719‧‧‧P-鏈接
725‧‧‧溝槽
729‧‧‧P-鏈接掩膜
735‧‧‧溝槽掩膜
第1圖表示一種原有技術的場效應電晶體器件的剖面示意圖。
第2A圖表示依據本發明的一個實施例，一種場平衡MOSFET(FBM)器件的剖面圖。
第2B圖表示依據本發明的一個實施例，一種FBM器件的剖面圖，以及P-鏈接的工作方式。
第2C圖表示依據本發明的一個實施例，一種FBM器件的俯視圖，用於表示在本體區的掩埋摻雜區之間，可以製備鏈接的位置。
第2D-2E圖表示依據本發明的另外兩個實施例，FBM器件的剖面圖。
第3A-3D圖所示圖表表示FBM器件不同的設計變數之間的關係。
第4A-4B圖表示依據本發明的一個實施例，一種FBM器件的剖面圖，用於解釋說明器件不容易受高電流雪崩模式故障影響的原因。
第5A-5H圖表示第2A圖所示FBM器件的製備製程的一系列剖面圖。
第6A-6G圖表示第2D圖所示FBM器件的製備製程的一系列剖面圖。
第7A-7D圖表示依據本發明的一個實施例，一種FBM器件的製備製程的一系列剖面圖。
本申請案是關於2011年10月25日存檔的共同受讓的、共同待決的申請序列號13/199,381的申請案，特此引用其全文，以作參考。
本申請案是關於共同受讓的、共同待決的申請序列號13/,的申請案，即Lingpeng Guan等人發明的題為《用於高壓器件的端接設計》(代理人案號ANO-054/US)，與本申請案在同一天存檔，特此引用其全文，以作參考。
本申請案是關於共同受讓的、共同待決的申請序列號13/,的申請案，即Guan Lingpeng等人發明的題為《用於高壓半導體器件的拐角佈局》(代理人案號ANO-055/US)，與本申請案在同一天存檔，特此引用其全文，以作參考。
儘管為了解釋說明，以下詳細說明包含了許多具體細節，但是本領域的技術人員應明確以下細節的各種變化和修正都屬於本發明的範圍。因此，提出以下本發明的典型實施例，並沒有使所聲明的方面損失任何普遍性，也沒有提出任何局限。
在以下詳細說明中，參照附圖，表示本發明可以實施的典型實施例。就這一點而言，根據圖中所示方向，使用“頂部”、“底部”、“正面”、“背面”、“向前”、“向後”等方向術語。由於本發明實施例的零部件，可以位於各種不同方向上，因此所用的方向術語僅用於解釋說明，不用於局限。應明確，無需偏離本發明的範圍，就能實現其他實施例，做出結構或邏輯上的變化。因此，以下詳細說明不用於局限，本發明的範圍應由所附的申請專利範圍限定。
第2A圖表示依據本發明的一個實施例，一種場平衡MOSFET(FBM)的剖面圖。FBM 200形成在半導體襯底中，半導體襯底含有第一導電類型的重摻雜區202，例如濃度約為2-4e10/cm3的N-型襯底，作为FBM 200的汲極區。汲極電極205形成在半導體襯底重摻雜區202底面。第一導電類型的輕摻雜電壓閉鎖區203，例如濃度約為1e14/cm3至1e15/cm3的N-型，位於重摻雜區202上方。重摻雜表面遮罩區204，也是濃度約為1e15/cm3至5e16/cm3的第一導電類型，位於電壓閉鎖區203上方。作為示例，但不作為局限，表面遮罩區204的摻雜濃度比電壓閉鎖區的摻雜濃度高5-100倍。FBM 200還包括多個溝槽225，內襯氧化層等電介質層207，並用導電溝槽填充材料填充，構成遮罩電極211。作為示例，但不作為局限，遮罩電極211可以用多晶矽製成。作為示例，但不作為局限，電介質層207在整個溝槽深度上，具有大致均勻的厚度，在溝槽底部可以稍微薄一些，可以在溝槽底部將其製備得較厚，或者在溝槽底部附近變成錐形較高。遮罩電極211電連接到源極電極214。 第二導電類型(例如P-型)的輕摻雜耗盡區209，形成在溝槽225的底部。第二導電類型的輕摻雜耗盡區209也稱為掩埋P-區209。作為示例，但不作為局限，表面遮罩區204可以比溝槽225加上掩埋P-區209的總深度更淺，或者深度大致相等。上文所述的術語“深度大致相等”的意思是，表面遮罩區204的深度在溝槽225加上掩埋P-區209的總深度的±10%以內。
第一導電類型的源極區208形成在表面遮罩區204的頂面附近。源極區電連接到源極電極214。第二導電類型的上部本體區206包圍著源極區208。重摻雜P+接頭206’也在源極區附近。平面閘極電極212形成在覆蓋著源極電極214的以及源極區208頂面附近區域的頂面上。
當掩埋P-區209沒有連接到本體區上時，掩埋P-區209會形成一個P-N結電容器。由於存在浮動P-區會在開關時產生較高的動態導通電阻，從而在開關時可能會出現問題。因此，適當摻雜鏈接219，例如對於N-型器件200來說，可以是P-摻雜鏈接(P-鏈接)，形成在掩埋P-區209和上部本體區206之間所選的位置處，以便為掩埋P-區209打開放電的通路。第2A圖表示兩個區域之間的P-鏈接219。如第2B圖所示，可以選擇P-鏈接219的摻雜濃度，使區域在反向偏壓下大幅耗盡。器件頂部附近所示的等電位線，處於比器件底部的電壓更低的電壓下。另外，陰影越黑表示電勢越低。為了使P-鏈接219大幅耗盡，P-鏈接219的摻雜濃度可以低於上部本體區206的摻雜濃度。
依據一個實施例，P-鏈接219僅處於所選區域。由於溝槽225可以降低器件的BV，或者使其導通電阻變差，因此並不是每個溝槽225都將掩埋P-區209連接到上部本體區206上。但是，所有的掩埋P-區209都透過P-鏈接，在某個位置上回連到源極上。另外，選擇性地將P-鏈接219分佈在器件的有源區上，可以使掩埋P-區209大幅耗盡。作為 示例，但不作為局限，第2C圖表示P-鏈接219的可能位置的俯視圖。在本例中，透過打開掩膜層中的一個小窗229，使很深的擴散連接掩埋P-區和上部本體區206，P-鏈接219形成在器件溝槽225的末端。
依據本發明的另一個實施例，在每個位置上，掩埋P-區209都透過P-鏈接219，電連接到上部本體區206上。依據本實施例，第2D圖表示FBM器件201的剖面圖。儘管可以降低器件的BV，本實施例在製備過程中需要一個較少的掩膜。與被迫在掩膜層中開窗，用於注入P-鏈接219不同，不需要掩膜就可以進行全面帶角度的注入。
依據本發明的另一個實施例，可以透過將溝槽225中的溝槽填充材料211連接到閘極電勢，而不是源極電勢，來控制FBM的開關速度。第2E圖表示在最左邊的溝槽中，製備帶有這種接頭的FBM器件200。這種接頭將會增大閘汲電容Cgd，閘汲電容Cgd會降低FBM器件201的開關速度。透過選擇將連接到閘極而不是源極上的溝槽225的幾率，可以控制Cgd的增大。這樣做是十分有益的，這是因為在很高的開關速度下，會出現過多的電磁感應(EMI)問題。
本發明的實施例保持了擊穿電壓(BV)，同時使RdsA最小。依據本發明的實施例，擊穿電壓(BV)在表面遮罩區204和電壓閉鎖區203之間分開。作為示例，但不作為局限，設計FBM器件的擊穿電壓為660V，可以配置表面遮罩區204承受140V，配置電壓閉鎖區203承受520V。電壓閉鎖區203作為傳統的外延層，遵循下述關係式：RdsABV2.5。因此，由於電壓閉鎖區203所承受的電壓從660V降至520V，導致RdsA成比例地降低(660/520)2.5=1.81。例如，如果器件的RdsA一開始是82mΩ˙cm2，那麼外延層必須承受整體的660V，電壓閉鎖區203只需承受520V，僅僅需要降低45.2mΩ˙cm2的RdsA。
配置表面遮罩區204，承受剩餘的電壓，增大的電阻可忽略不計。為了達到上述目標，使RdsA最小，要重摻雜表面遮罩區204。然而，摻雜濃度增大後，外延層本身無法承受足夠的電壓。因此，必須對表面遮罩區204進行電荷補償。電荷補償由兩個單獨的部分進行：(1)由氧化物207製成的MOS電容器，包圍著遮罩電極211；以及(2)掩埋P-區209。兩種部件均可配置以便各自承受期望的電壓量。作為示例，但不作為局限，表面遮罩區204所承受的電壓，由掩埋P-區209承擔一半，另一半由氧化物207承擔。
如果需要掩埋P-區209承受較大部分的電壓，那麼可以設計掩埋P-區延伸到半導體襯底中較深的地方。掩埋P-區中摻雜濃度的變化不會強烈影響FBM 200BV的變化。第3A圖表示目標濃度60%的變化使器件的BV僅僅降低了5V左右。正是由於允許製程變化很大的同時，仍然可以保持很高的BV，因此提高了器件的耐用性。然而，P-鏈接219的摻雜濃度變化會降低FBM 200的BV。如第3D圖所示，目標濃度30%的變化會降低BV 30V左右。要注意的是，擊穿電壓對摻雜濃度的敏感性一般不會受P-鏈接數量的影響。
如果需要氧化物承受較大的電壓，那麼可以增大溝槽225的深度，以及/或者增大氧化物207的厚度。氧化物厚度和承載電壓量之間的關係，可以用方程1表示：
其中N(y)為摻雜濃度，是深度y的函數，m為臺面結構寬度，tox為溝槽氧化物厚度，d為溝槽深度，BV為擊穿電壓，以及εsi 和εox分別為矽和氧化物的介電常數。第3B圖表示氧化物207的厚度與FBM 200的BV之間的真實關係，第3C圖表示溝槽225的深度與FBM 200的BV之間的真實關係。
為了承受一部分BV，掩埋P-區也增強了FBM 200的耐用性。由於寄生雙極NPN電晶體(由N-源極區、P-本體區以及N-外延層製成)接通，無法斷開，因此MOSFET不能處於非箝位元感應開關(UIS)模式。原有技術透過降低電阻，或將雪崩區移出NPN電晶體，試圖防止寄生NPN電晶體445接通。如第4A圖所示，當FBM 400處於雪崩模式時，電流441大多流經溝槽側壁的周圍，而不是在源極區408下方。這樣可以避免電流流經寄生雙極NPN電晶體445附近，從而防止器件閉鎖。另外，選取摻雜濃度，使碰撞電離產生的電子-空穴濃度最大的位置，趨於器件的深處。由於器件的溫度在碰撞電離濃度高的位置上會升高，高溫會使NPN更容易接通445，從而可以進一步增強器件的耐用性。如第4B圖所示，碰撞電離最高的區域在掩埋P-區409中(位置A)，以及電壓閉鎖層的深處(位置B)。因此，將位置A和B移至離寄生NPN雙極電晶體較遠的地方，會使器件更加耐用。
本器件的主要優勢在於，在反向恢復時，二極體性能遠遠優於傳統的電荷平衡MOSFET。在電荷平衡MOSFET中，在低壓時P-N立柱的耗盡，導致在器件閉鎖很大的電壓之前，移除所有儲存的電荷。一旦儲存的電荷消失，電流會迅速降至零，致使“快照”恢復。當整個外加電路雜散電感時，很高的dI/dt(電流變化速度)會使高壓過沖，導致器件受損。在FBM結構中，器件的下部像傳統的功率MOSFET那樣儲存電荷，直到達到很高的閉鎖電壓時，才會除去電荷。當電壓聚集時，電荷移除較慢的主要原因在於“軟”二極體恢復，這是某些功率電路的優勢特點，降低了電壓過沖，減少器件受損以及EMI問題。
製備上述類型的FBM器件還有許多不同的技術。作為示例，第5A-5H圖為表面遮罩區504的剖面圖，用於表示製備第2A圖所示類型的FBM器件的方法。由於本實施例僅需要7個掩膜(以下每個製程步驟對應一個掩膜：(1)鏈接，(2)溝槽，(3)多晶矽閘極，(4)源極，(5)接頭，(6)金屬以及(7)鈍化)，從而降低了製造成本。與原有技術的超級結器件通常需要多達17個掩膜相比，這樣可以大幅節省成本。如第5A圖所示，重摻雜N-型外延半導體層504形成在輕摻雜電壓閉鎖區503上方。要注意的是，為了簡便，第5A-5G圖僅表示出了閉鎖區503的最上部。如第5A圖所示，然後在表面遮罩區504的表面上，例如透過形成鈍化層的圖案，製備一個P-鏈接掩膜529。然後，在表面遮罩區504中P-鏈接519需要的位置上，注入P-型摻雜物。
如第5B圖所示，然後例如透過形成光致抗蝕劑層的圖案，或者利用低溫氧化物(LTO)沉積技術或熱氧化，在表面遮罩區504的表面上，形成硬掩膜氧化物的圖案，形成一個溝槽掩膜535，並用光致抗蝕劑掩膜刻蝕。透過溝槽掩膜535，在重摻雜表面遮罩區504中形成溝槽525到預定義深度。溝槽525穿過P-鏈接519延伸，使P-摻雜區仍然沿側壁。作為示例，但不作為局限，可以透過反應離子刻蝕(RIE)形成溝槽525。如第5C圖所示，透過0°傾斜的全面垂直P-型摻雜注入，形成掩埋P-區509。如第5D圖所示，沿溝槽525的側壁和底面，生長氧化層507。P-鏈接519和掩埋P-區509也允許擴散。這樣可以使P-鏈接519與掩埋P-區509相連。擴散製程和氧化物製備可以同時進行。另外，擴散掩埋P-區509，使溝槽525和掩埋P-區509的總深度接近表面遮罩區504的深度。作為示例，但不作為局限，表面遮罩區504的深度可以比溝槽525加上掩埋P-區509的累積深度淺或大致相同。如上所述，大致相同的深度包括溝槽525和掩埋P-區509的累積深度的±10%以內。
然後，繼續進行標準的製備製程，製成如第2A圖所示的FBM器件。第5E圖表示用溝槽填充材料511填充溝槽，並回刻多晶矽和氧化物材料。第5F圖表示JFET注入，限定閘極氧化和多晶矽柵極。第5G圖表示本體注入和驅動。最後，第5H圖表示源極掩膜和注入508、源極驅動、自對準的P+注入接頭506’、含有硼酸的矽玻璃(BPSG)沉積、接頭形成以及金屬沉積掩膜和刻蝕之後，最終的FBM器件500。
依據本發明的另一個實施例，透過選擇性的側壁注入，製備P-鏈接519。從而可以省去如第5A圖所示最初的P-鏈接掩膜。然而，對於選擇性的側壁注入仍然需要一個額外的掩膜，因此需要7個掩膜。在溝槽側壁內襯氧化物之前，掩膜所選的溝槽，實現傾斜注入部分溝槽。
依據本發明的另一個實施例，如第2D圖所示製備FBM，使得每個掩埋P-區209都通過P-鏈接219，連接到本體區206上。本實施例的優點在於，可以減少製備FBM器件所需的掩膜層數量。然而，本實施例需要一個大的端接區。由於掩埋P-區連接整個器件，因此端接區中必須斷開連接，從而避免汲極電極205和源極電極214之間短接。在共同受讓的美國專利申請號13/,(ANO-054/US)中提出了適用於本發明實施例端接區，特此引用，以作參考。
第6A-6F圖表示依據本實施例的一種製備方法。如第6A圖所示，溝槽掩膜635形成在表面遮罩區604的表面上，例如透過形成光致抗蝕劑層的圖案，或者利用低溫氧化物(LTO)沉積技術或熱氧化，透過光致抗蝕劑掩膜刻蝕，形成硬掩膜氧化物的圖案。然後，在重摻雜表面遮罩區604中形成溝槽625到預定義深度。作為示例，但不作為局限，可以透過活性離子刻蝕(RIE)製備溝槽625。如第6B圖所示，透過0°傾斜的全面垂直P-型摻雜注入，製備掩埋P-區609。而且在第6B圖中，利用 側壁注入，製備P-鏈接619。作為示例，但不作為局限，側壁注入可以透過以一定傾斜角度的離子注入進行側壁注入，例如以15-30度傾斜。還可選擇，沿每個溝槽側壁生長一個P-型外延層，製備側壁注入。如第6C圖所示，沿溝槽625的側壁和底面，生長一層絕緣材料607，例如氧化層。P-鏈接619和掩埋P-區609也可以擴散。這樣可以透過掩埋P-區609連接P-鏈接619。擴散製程和氧化物製備可以同時進行。另外，擴散掩埋P-區609，使每個溝槽625和掩埋P-區609的總深度與表面遮罩區604的深度類似。作為示例，但不作為局限，表面遮罩區604的深度可以比溝槽625加上掩埋P-區609的累積深度淺或大致相同。如上所述，大致相同的深度包括溝槽625和掩埋P-區609的累積深度的±10%以內。
然後，繼續進行標準的製備製程，製成如第2D圖所示的FBM器件。第6D圖表示用溝槽填充材料611(例如多晶矽)和填充溝槽，並回刻絕緣材料607和溝槽填充材料611。第6E圖表示JFET注入，限定閘極氧化和多晶矽閘極。第6F圖表示本體注入和驅動。最後，第6G圖表示源極掩膜和注入608、源極驅動、自對準的P+注入接頭606’、含有硼酸的矽玻璃(BPSG)沉積、接頭形成以及金屬沉積掩膜和刻蝕之後，最終的FBM器件600。
依據本發明的另一個實施例，透過在本體結和溝槽底部之間大約一半處，引入一個單獨的掩埋層，並且利用擴散合併這些區域，製備P-鏈接219。本方法允許在襯底中形成較深的溝槽。第7A-7D圖表示如何使用本方法製備FBM器件700。首先，第7A圖表示一個部分完成的表面遮罩區704’形成在輕摻雜電壓閉鎖區703上方。要注意的是，第7A-7D圖僅表示出了閉鎖區703的最頂部。然後，在部分完成的表面遮罩區704’的表面上，例如透過形成光致抗蝕劑層的圖案，製備一個P-鏈接掩膜729。在表面遮罩區704’中P-鏈接719所需的位置處注入P-型摻雜物。第7B 圖表示剩餘的表面遮罩區704”外延生長在注入的P-鏈接719上方。
然後，第7C圖表示在表面遮罩區704”的表面上，製備一個溝槽掩膜735，例如透過形成光致抗蝕劑層的圖案，或者利用低溫氧化物(LTO)沉積技術或熱氧化，透過光致抗蝕劑掩膜刻蝕，形成硬掩膜氧化物的圖案。然後，在重摻雜表面遮罩區704’和表面遮罩區704”中形成溝槽725到預定義深度。溝槽725也穿過P-鏈接719延伸，使P-摻雜區仍然沿溝槽725的側壁。作為示例，但不作為局限，可以透過活性離子刻蝕(RIE)製備溝槽725。如第7C圖所示，透過0°傾斜的全面垂直P-型摻雜注入，製備掩埋P-區709。如第7D圖所示，沿溝槽725的側壁和底面，生長一個氧化層707。P-鏈接719和掩埋P-區709也可以擴散。這樣可以透過掩埋P-區709連接P-鏈接719。擴散製程和氧化物製備可以同時進行。另外，擴散掩埋P-區709，使每個溝槽725和掩埋P-區709的總深度與表面遮罩區704的深度類似。作為示例，但不作為局限，表面遮罩區704的深度可以比溝槽725加上掩埋P-區709的累積深度淺或大致相同。一般而言，相同深度包括溝槽725和掩埋P-區709的累積深度的±10%以內。剩餘的製程步驟與之前的實施例的製程相同，製成的FBM器件700中除了溝槽725更深之外，其他都與FBM器件500大致相同。如上所述，溝槽越深，表面遮罩區704可承受的電壓越高。另外，為了給器件中每個掩埋P-區709提供P-鏈接719，也可以改變本實施例。
儘管以上是本發明的較佳實施例的完整說明，但是也有可能使用各種可選、修正和等效方案。因此，本發明的範圍不應局限於以上說明，而應由所附的申請專利範圍及其全部等效內容決定。本方法中所述步驟的順序並不用於局限進行相關步驟的特定順序的要求。任何可選件(無論首選與否)，都可與其他任何可選件(無論首選與否)組合。在以下權利要求中，除非特別聲明，否則不定冠詞“一個”或“一種”都指下文內 容中的一個或多個專案的數量。除非在指定的權利要求中用“意思是”特別指出，否則所附的申請專利範圍應認為是包括意義及功能的限制。申請專利範圍中沒有用“意思是”特別指出用於特定功能的任意專案，都不應認為是35 USC § 112,¶ 6中具體所述的“意思”或“步驟”。
200‧‧‧FBM器件
212‧‧‧閘極電極
214‧‧‧源極電極
207‧‧‧電介質層
204‧‧‧表面遮罩區
211‧‧‧遮罩電極
206‧‧‧本體區
206’‧‧‧重摻雜P+接頭
219‧‧‧P-鏈接
209‧‧‧輕摻雜耗盡區
225‧‧‧溝槽
208‧‧‧源極區
203‧‧‧電壓閉鎖區
202‧‧‧重摻雜區
205‧‧‧汲極電極

Claims (20)

  1. 一種半導體器件，其包括：一第一導電類型的一半導體襯底；沉積在該半導體襯底之頂面上的該第一導電類型的一外延層，其特徵在於，該外延層包括重摻雜的一表面遮罩區，其位於輕摻雜的一電壓閉鎖區之上方；一個與該第一導電類型相反的第二導電類型的本體區，該第一導電類型的一源極區以及一個沉積在該表面遮罩區之頂面附近的閘極，一個沉積在該半導體襯底之底面上的汲極；多個形成在該表面遮罩區中的溝槽，其中該些溝槽內襯一溝槽絕緣材料，並用一導電溝槽填充材料填充，配置該些溝槽與該表面遮罩區上方的源極電極電接觸，並且與該源極區電接觸；多個第二導電類型的掩埋摻雜區，其中每一個該些溝槽中的下方均接觸地形成有一個掩埋摻雜區，並且其中該些掩埋摻雜區延伸的深度與該表面遮罩區的底面大致相同；以及一個或多個第二導電類型的電荷鏈接通路，沿該些溝槽的一個或多個溝槽壁，用於將該些掩埋摻雜區電連接到該本體區。
  2. 如申請專利範圍第1項所述之器件，其中配置該表面遮罩區，以承載大約1/3的一擊穿電壓(BV)，配置該電壓閉鎖區，以承載大約2/3的擊穿電壓。
  3. 如申請專利範圍第2項所述之器件，其中配置該些掩埋摻雜區，以承載該表面遮罩區所承受的該擊穿電壓的一半，該溝槽絕緣材料承載該表面遮罩區所承受的剩餘該擊穿電壓 (BV)。
  4. 如申請專利範圍第1項所述之器件，其中部分該些溝槽中的該溝槽填充材料與該源極電極絕緣，並且電連接到該閘極電極。
  5. 如申請專利範圍第1項所述之器件，其中該表面遮罩區的摻雜濃度比該電壓閉鎖區的摻雜濃度大5-100倍。
  6. 如申請專利範圍第1項所述之器件，其中該些掩埋摻雜區中的每一個掩埋摻雜區，都透過該或該些電荷鏈接通路中的一個通路，連接到該源極區上。
  7. 如申請專利範圍第1項所述之器件，其中該溝槽填充材料包括多晶矽。
  8. 如申請專利範圍第1項所述之器件，其中該溝槽絕緣材料為氧化物材料。
  9. 如申請專利範圍第1項所述之器件，其中該電荷鏈接通路的摻雜濃度低於該本體區的摻雜濃度。
  10. 如申請專利範圍第1項所述之器件，其中該溝槽絕緣材料的厚度大致均勻。
  11. 如申請專利範圍第1項所述之器件，其中該些溝槽之底部的該溝槽絕緣材料較厚。
  12. 如申請專利範圍第1項所述之器件，其中該溝槽絕緣材料的厚度在該些溝槽之底部附近逐漸地增高。
  13. 一種製備半導體器件的方法，其包括下列步驟：a)製備一個第一導電類型的半導體襯底； b)在該半導體襯底的一頂面上製備一第一導電類型的外延層，其中該外延層包括一個重摻雜的一表面遮罩區，位於輕摻雜的一電壓閉鎖區上方；c)在該表面遮罩區的頂面附近，製備與該第一導電類型相反的一第二導電類型的本體區；d)在該表面遮罩區的該頂面附近，製備一第一導電類型的源極區；e)在該表面遮罩區的該頂面上，製備多個閘極；f)在該半導體襯底的底面上製備一個汲極；g)在該表面遮罩區中製備多個溝槽，其中該些溝槽內襯一溝槽絕緣材料，並用一導電溝槽填充材料填充，配置該些溝槽與該表面遮罩區上方的一源極電極電接觸，並且與該源極區電接觸；h)製備多個第二導電類型的掩埋摻雜區，其中每一個該些溝槽中的下方均接觸地形成有一個掩埋摻雜區，並且其中該些掩埋摻雜區延伸的深度與該表面遮罩區的底面大致相同；並且i)製備一個或多個第二導電類型的電荷鏈接通路，沿該些溝槽的一個或多個溝槽壁，用於將該些掩埋摻雜區電連接到該本體區。
  14. 如申請專利範圍第13項所述之方法，其中沿該些溝槽中的一個或多個溝槽的一個或多個溝槽壁，注入該些第二導電類型的掩埋摻雜區，形成該些電荷鏈接通路。
  15. 如申請專利範圍第13項所述之方法，其中形成該電荷鏈接通路是透過： a)在該電壓閉鎖區上，製備該表面遮罩區的第一部分；b)在一個或多個所選位置處的該表面遮罩區的該第一部分之該頂面內，注入該些第二導電類型的掩埋摻雜區；並且c)在該第一部分和注入的該些掩埋摻雜區上方，形成該表面遮罩區的第二部分。
  16. 如申請專利範圍第13項所述之方法，其中該些掩埋摻雜區中的每一個掩埋摻雜區都透過該電荷鏈接通路中的通路，連接到該源極區上。
  17. 如申請專利範圍第16項所述之方法，其中沿該些溝槽中每個該溝槽的該溝槽壁，注入該第二導電類型的掩埋摻雜區，形成該電荷鏈接通路。
  18. 如申請專利範圍第16項所述之方法，其中沿該些溝槽中該溝槽的該溝槽壁，生長該外延層，形成該電荷鏈接通路。
  19. 如申請專利範圍第16項所述之方法，其中形成該電荷鏈接通路是透過：a)製備該電壓閉鎖區和該表面遮罩區的第一部分；b)在將要製備的該些溝槽中的每該溝槽的位置處，該表面遮罩區之該頂面內，注入該些第二導電類型的掩埋摻雜區；並且c)在該電壓閉鎖區和注入的該些掩埋摻雜區上方，形成該表面遮罩區的第二部分。
  20. 一種製備半導體器件的方法，其包括下列步驟： a)在一第一導電類型的一半導體襯底的頂面上，製備該第一導電類型的一外延層，其中該外延層包括一個重摻雜的一表面遮罩區，位於一個輕摻雜的一電壓閉鎖區上方；b)在該外延層製備多個溝槽和多個第二導電類型的掩埋摻雜區，其中每一個該些溝槽中的下方均接觸地形成有一個掩埋摻雜區，並且其中該掩埋摻雜區延伸的深度與該表面遮罩區的頂面大致相同；c)沿該些溝槽的一個或多個溝槽壁，製備一個或多個第二導電類型的電荷鏈接通路；d)用一溝槽絕緣材料內襯該溝槽；e)用一導電填充材料填充該溝槽的剩餘部分；f)在該表面遮罩區的頂面附近，製備與一第一導電類型相反的第二導電類型的本體區，其中配置一個或多個電荷鏈接通路，將該掩埋摻雜區電連接到該本體區；g)在該表面遮罩區的頂面附近，製備多個閘極；h)在該表面遮罩區的該頂面附近，製備一第一導電類型的源極區；i)在該外延層上方製備一源極電極，並且與該源極區，該本體區以及該導電填充材料電接觸；以及j)在該半導體襯底的底面上製備一個汲極電極與形成在該半導體襯底底面的汲極區電接觸。
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US9450083B2 (en) 2016-09-20
US20160351659A1 (en) 2016-12-01
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US8785279B2 (en) 2014-07-22

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