TWI529801B - 依電漿加工法之加工形狀的預測模擬裝置與模擬方法及程式 - Google Patents

依電漿加工法之加工形狀的預測模擬裝置與模擬方法及程式 Download PDF

Info

Publication number
TWI529801B
TWI529801B TW101107151A TW101107151A TWI529801B TW I529801 B TWI529801 B TW I529801B TW 101107151 A TW101107151 A TW 101107151A TW 101107151 A TW101107151 A TW 101107151A TW I529801 B TWI529801 B TW I529801B
Authority
TW
Taiwan
Prior art keywords
processing method
etching
surface movement
deposition
movement amount
Prior art date
Application number
TW101107151A
Other languages
English (en)
Chinese (zh)
Other versions
TW201239983A (en
Inventor
小野耕平
岩崎拓也
Original Assignee
瑞穗資訊總研股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 瑞穗資訊總研股份有限公司 filed Critical 瑞穗資訊總研股份有限公司
Publication of TW201239983A publication Critical patent/TW201239983A/zh
Application granted granted Critical
Publication of TWI529801B publication Critical patent/TWI529801B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/20—Design optimisation, verification or simulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H01L21/30655—Plasma etching; Reactive-ion etching comprising alternated and repeated etching and passivation steps, e.g. Bosch process

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Evolutionary Computation (AREA)
  • General Engineering & Computer Science (AREA)
  • Geometry (AREA)
  • Plasma & Fusion (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Plasma Technology (AREA)
TW101107151A 2011-03-07 2012-03-03 依電漿加工法之加工形狀的預測模擬裝置與模擬方法及程式 TWI529801B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2011049680A JP5685762B2 (ja) 2011-03-07 2011-03-07 プラズマ加工形状シミュレーション装置及びプログラム

Publications (2)

Publication Number Publication Date
TW201239983A TW201239983A (en) 2012-10-01
TWI529801B true TWI529801B (zh) 2016-04-11

Family

ID=46798049

Family Applications (1)

Application Number Title Priority Date Filing Date
TW101107151A TWI529801B (zh) 2011-03-07 2012-03-03 依電漿加工法之加工形狀的預測模擬裝置與模擬方法及程式

Country Status (6)

Country Link
US (1) US20140005991A1 (enExample)
EP (1) EP2685489A4 (enExample)
JP (1) JP5685762B2 (enExample)
KR (1) KR101588691B1 (enExample)
TW (1) TWI529801B (enExample)
WO (1) WO2012121081A1 (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9201998B1 (en) 2014-06-13 2015-12-01 Kabushiki Kaisha Toshiba Topography simulation apparatus, topography simulation method and recording medium
JP6117746B2 (ja) 2014-07-30 2017-04-19 ソニーセミコンダクタソリューションズ株式会社 エッチング特性推定方法、プログラム、情報処理装置、加工装置、設計方法、および、製造方法
US10138550B2 (en) * 2014-09-10 2018-11-27 Toshiba Memory Corporation Film deposition method and an apparatus
WO2016132759A1 (ja) * 2015-02-20 2016-08-25 ソニー株式会社 情報処理装置、加工装置、推定方法、プログラム、および、加工方法
US10032681B2 (en) * 2016-03-02 2018-07-24 Lam Research Corporation Etch metric sensitivity for endpoint detection
US10572697B2 (en) 2018-04-06 2020-02-25 Lam Research Corporation Method of etch model calibration using optical scatterometry
CN111971551B (zh) 2018-04-10 2025-02-28 朗姆研究公司 机器学习中的光学计量以表征特征
WO2019199697A1 (en) 2018-04-10 2019-10-17 Lam Research Corporation Resist and etch modeling
CN110457780A (zh) * 2019-07-23 2019-11-15 上海卫星装备研究所 介质深层充电电位和内部充电电场获取方法及存储介质
US12360510B2 (en) 2021-04-20 2025-07-15 Lam Research Corporation Large spot spectral sensing to control spatial setpoints
CN113378444B (zh) * 2021-08-13 2021-11-05 墨研计算科学（南京）有限公司 一种淀积工艺的仿真方法及装置
JPWO2024005047A1 (enExample) * 2022-07-01 2024-01-04

Family Cites Families (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5070469A (en) * 1988-11-29 1991-12-03 Mitsubishi Denki Kabushiki Kaisha Topography simulation method
DE4241045C1 (de) 1992-12-05 1994-05-26 Bosch Gmbh Robert Verfahren zum anisotropen Ätzen von Silicium
US5421934A (en) * 1993-03-26 1995-06-06 Matsushita Electric Industrial Co., Ltd. Dry-etching process simulator
US5733820A (en) * 1995-04-27 1998-03-31 Sharp Kabushiki Kaisha Dry etching method
JP3592826B2 (ja) * 1996-03-05 2004-11-24 株式会社東芝 膜形状予測方法
JPH1174326A (ja) * 1997-08-29 1999-03-16 Hitachi Ltd 半導体断面観察装置
US6151532A (en) * 1998-03-03 2000-11-21 Lam Research Corporation Method and apparatus for predicting plasma-process surface profiles
US6329292B1 (en) * 1998-07-09 2001-12-11 Applied Materials, Inc. Integrated self aligned contact etch
US6650426B1 (en) * 1999-07-12 2003-11-18 Sc Technology, Inc. Endpoint determination for recess etching to a precise depth
US6326307B1 (en) * 1999-11-15 2001-12-04 Appllied Materials, Inc. Plasma pretreatment of photoresist in an oxide etch process
US6617257B2 (en) * 2001-03-30 2003-09-09 Lam Research Corporation Method of plasma etching organic antireflective coating
US6558965B1 (en) * 2001-07-11 2003-05-06 Advanced Micro Devices, Inc. Measuring BARC thickness using scatterometry
US7169695B2 (en) * 2002-10-11 2007-01-30 Lam Research Corporation Method for forming a dual damascene structure
JP4482308B2 (ja) * 2002-11-26 2010-06-16 東京エレクトロン株式会社 プラズマ処理装置及びプラズマ処理方法
JP5404984B2 (ja) * 2003-04-24 2014-02-05 東京エレクトロン株式会社 プラズマモニタリング方法、プラズマモニタリング装置及びプラズマ処理装置
US7271107B2 (en) * 2005-02-03 2007-09-18 Lam Research Corporation Reduction of feature critical dimensions using multiple masks
JP4745035B2 (ja) * 2005-11-24 2011-08-10 株式会社東芝 シミュレーション装置、シミュレーションプログラムおよびシミュレーション方法
US8165854B1 (en) * 2006-01-11 2012-04-24 Olambda, Inc. Computer simulation of photolithographic processing
JP4909609B2 (ja) * 2006-03-01 2012-04-04 株式会社東芝 加工形状シミュレーション方法、半導体装置の製造方法及び加工形状シミュレーションシステム
US8709951B2 (en) * 2007-07-19 2014-04-29 Texas Instruments Incorporated Implementing state-of-the-art gate transistor, sidewall profile/angle control by tuning gate etch process recipe parameters
JP5322413B2 (ja) * 2007-08-16 2013-10-23 株式会社東芝 シミュレーション方法およびシミュレーションプログラム
US8815744B2 (en) * 2008-04-24 2014-08-26 Fairchild Semiconductor Corporation Technique for controlling trench profile in semiconductor structures
JP2010134352A (ja) * 2008-12-08 2010-06-17 Fujifilm Corp カラーフィルタの製造方法及び固体撮像素子
US8049327B2 (en) * 2009-01-05 2011-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Through-silicon via with scalloped sidewalls
JP5428450B2 (ja) * 2009-03-30 2014-02-26 ソニー株式会社 イオン照射ダメージの予測方法とイオン照射ダメージのシミュレータ、およびイオン照射装置とイオン照射方法
JP5562591B2 (ja) * 2009-07-31 2014-07-30 富士フイルム株式会社 着色硬化性組成物、カラーフィルタ及びその製造方法
JP5440021B2 (ja) * 2009-08-24 2014-03-12 ソニー株式会社 形状シミュレーション装置、形状シミュレーションプログラム、半導体製造装置及び半導体装置の製造方法
US8283988B2 (en) * 2010-02-25 2012-10-09 Seiko Epson Corporation Resonator element, resonator, oscillator, and electronic device
US9620338B2 (en) * 2010-03-16 2017-04-11 Mizuho Information & Research Institute, Inc. System, method, and program for predicting processing shape by plasma process
JP5732843B2 (ja) * 2010-12-21 2015-06-10 ソニー株式会社 シミュレータ、加工装置、ダメージ評価方法、及び、ダメージ評価プログラム
US9287097B2 (en) * 2011-11-30 2016-03-15 Sony Corporation Predicting ultraviolet ray damage with visible wavelength spectroscopy during a semiconductor manufacturing process
JP5539547B2 (ja) * 2012-01-24 2014-07-02 キヤノン株式会社 液体吐出ヘッド及びその製造方法
US9147610B2 (en) * 2012-06-22 2015-09-29 Infineon Technologies Ag Monitor structures and methods of formation thereof
JP6065612B2 (ja) * 2012-06-28 2017-01-25 ソニー株式会社 シミュレーション方法、シミュレーションプログラム、加工装置およびシミュレータ
JP5974840B2 (ja) * 2012-11-07 2016-08-23 ソニー株式会社 シミュレーション方法、シミュレーションプログラム、シミュレータ、加工装置、半導体装置の製造方法
US9317632B2 (en) * 2013-03-14 2016-04-19 Coventor, Inc. System and method for modeling epitaxial growth in a 3-D virtual fabrication environment
JP6177671B2 (ja) * 2013-11-25 2017-08-09 ソニーセミコンダクタソリューションズ株式会社 シミュレーション方法、シミュレーションプログラムおよびシミュレータ

Also Published As

Publication number Publication date
KR20140016924A (ko) 2014-02-10
WO2012121081A1 (ja) 2012-09-13
EP2685489A4 (en) 2014-09-24
US20140005991A1 (en) 2014-01-02
KR101588691B1 (ko) 2016-01-27
EP2685489A1 (en) 2014-01-15
JP5685762B2 (ja) 2015-03-18
TW201239983A (en) 2012-10-01
JP2012186394A (ja) 2012-09-27

Similar Documents

Publication Publication Date Title
TWI529801B (zh) 依電漿加工法之加工形狀的預測模擬裝置與模擬方法及程式
TWI496185B (zh) 依電漿加工法之加工形狀的預測系統，其方法及程式
JP6899659B2 (ja) 反射スペクトルマッチングおよび表面動力学モデル最適化によるエッチングプロファイル最適化のための方法および装置
TWI805580B (zh) 透過邊緣放置誤差預測之設計佈局圖案近接校正
US10386828B2 (en) Methods and apparatuses for etch profile matching by surface kinetic model optimization
US20230049157A1 (en) Performance predictors for semiconductor-manufacturing processes
Makabe et al. Plasma electronics: applications in microelectronic device fabrication
US10197908B2 (en) Photoresist design layout pattern proximity correction through fast edge placement error prediction via a physics-based etch profile modeling framework
Kolobov Fokker–Planck modeling of electron kinetics in plasmas and semiconductors
JP6065612B2 (ja) シミュレーション方法、シミュレーションプログラム、加工装置およびシミュレータ
JP2010282636A (ja) プラズマプロセスによる表面プロファイルを予測するための方法及び装置
Kokkoris et al. Simulation of SiO 2 and Si feature etching for microelectronics and microelectromechanical systems fabrication: A combined simulator coupling modules of surface etching, local flux calculation, and profile evolution
Xiao et al. Multiscale modeling and neural network model based control of a plasma etch process
JP5112624B2 (ja) プロセスチャンバ及びプラズマチャンバを操作する方法
Džafić et al. Plasma sheath modelling to predict etch-induced overlay
KR100575894B1 (ko) 플라즈마 공정 챔버의 최적화 진단시스템 및 진단방법
Ishchuk et al. ViPER: simulation software for high aspect ratio plasma etching of silicon
Ventzek et al. Application and simulation of low temperature plasma processes in semiconductor manufacturing
Ahn et al. Deep transfer operator learning for predicting low temperature plasma sheath dynamics in semiconductor processing
Kazanskiy et al. Simulation of technological process of microstructures etching in high-voltage gas discharge plasma
Main et al. Kinetic simulations of low-temperature plasmas used for plasma processing: ICP and feature-scale models
KR20250168426A (ko) 컴퓨터 프로그램, 정보 처리 방법 및 정보 처리 장치
Xiao et al. Multiscale Modeling and Recurrent Neural Network Based Optimization of a Plasma Etch Process. Processes 2021, 9, 151
Sethian Modern Interface Methods for Semiconductor Process Simulation
Radjenović et al. Influence of charging on SiO2 etching profile evolution etched by fluorocarbon Plasmas

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees