TWI528519B - 封裝結構及傳輸線之形成方法 - Google Patents
封裝結構及傳輸線之形成方法 Download PDFInfo
- Publication number
- TWI528519B TWI528519B TW102143710A TW102143710A TWI528519B TW I528519 B TWI528519 B TW I528519B TW 102143710 A TW102143710 A TW 102143710A TW 102143710 A TW102143710 A TW 102143710A TW I528519 B TWI528519 B TW I528519B
- Authority
- TW
- Taiwan
- Prior art keywords
- microbump
- linear
- layer
- microbumps
- transmission line
- Prior art date
Links
- 230000005540 biological transmission Effects 0.000 title claims description 67
- 238000000034 method Methods 0.000 title claims description 41
- 229910052751 metal Inorganic materials 0.000 claims description 66
- 239000002184 metal Substances 0.000 claims description 66
- 239000000758 substrate Substances 0.000 claims description 59
- 230000008054 signal transmission Effects 0.000 claims description 40
- 239000000463 material Substances 0.000 claims description 20
- 239000004744 fabric Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 283
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 21
- 230000008569 process Effects 0.000 description 19
- 229910000679 solder Inorganic materials 0.000 description 19
- 239000010949 copper Substances 0.000 description 18
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 17
- 229910052802 copper Inorganic materials 0.000 description 17
- 238000002161 passivation Methods 0.000 description 14
- 239000011241 protective layer Substances 0.000 description 14
- 239000004065 semiconductor Substances 0.000 description 12
- 229910052759 nickel Inorganic materials 0.000 description 10
- 239000011135 tin Substances 0.000 description 8
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 7
- 229910052718 tin Inorganic materials 0.000 description 7
- 239000003989 dielectric material Substances 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 5
- 239000004020 conductor Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 229910052709 silver Inorganic materials 0.000 description 5
- 239000004332 silver Substances 0.000 description 5
- 229910001316 Ag alloy Inorganic materials 0.000 description 4
- QCEUXSAXTBNJGO-UHFFFAOYSA-N [Ag].[Sn] Chemical compound [Ag].[Sn] QCEUXSAXTBNJGO-UHFFFAOYSA-N 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 229920002577 polybenzoxazole Polymers 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000003491 array Methods 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 229910001128 Sn alloy Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910001080 W alloy Inorganic materials 0.000 description 1
- PQIJHIWFHSVPMH-UHFFFAOYSA-N [Cu].[Ag].[Sn] Chemical compound [Cu].[Ag].[Sn] PQIJHIWFHSVPMH-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- 239000010955 niobium Substances 0.000 description 1
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920000307 polymer substrate Polymers 0.000 description 1
- 239000007779 soft material Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5225—Shielding layers formed together with wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6605—High-frequency electrical connections
- H01L2223/6627—Waveguides, e.g. microstrip line, strip line, coplanar line
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
- H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01028—Nickel [Ni]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
- H01P5/00—Coupling devices of the waveguide type
- H01P5/02—Coupling devices of the waveguide type with invariable factor of coupling
- H01P5/022—Transitions between lines of the same kind and shape, but with different dimensions
- H01P5/028—Transitions between lines of the same kind and shape, but with different dimensions between strip lines
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Description
本發明係關於半導體封裝,且特別是關於一種封裝結構及傳輸線之形成方法。
電子裝置可簡單區分為例如由積體電路晶片、封裝結構、印刷電路板、及系統所構成之階層,封裝結構為積體電路晶片與印刷電路板之間的介面,由半導體材料(例如矽)製造積體電路晶粒,隨後使用引線接合(wire bonding,WB)、捲帶式自動接合(tape automated bonding,TAB)、或覆晶組裝技術(flip chip bumping assembly techniques)將晶粒組裝為半導體封裝結構,例如四方平面封裝(quad flat packs,QFP)、引腳陣列封裝(pin grid arrays,PGA)、球型陣列封裝(ball grid arrays,BGA)、三維積體電路(three dimensional integrated circuits,3DIC)、晶圓級封裝(wafer level packages,WLP)、或層疊式封裝(package on package,PoP)裝置,然後將封裝之晶粒直接貼附至一印刷電路板或另一基板以作為二級封裝。
三維積體電路亦稱為垂直內連接封裝技術,其利用了晶片的垂直維度來減少內連接長度,並達到更佳的積體效率。三維積體電路封裝所使用的技術包括引線接合、微凸塊、通孔電極等等。可使用一矽轉接板(interposer)來形成三維積體電路封裝,其中此轉接板可提供安裝於轉接板上之晶粒的晶
粒對晶粒內連接。舉例而言,可藉由面對面(face-to-face)堆疊或面對背(face-to-back)堆疊而將二晶粒接合於彼此之上,其中下方晶粒藉由連接器(例如微凸塊)連接至轉接板。或者,亦可將複數晶粒平行安裝於一轉接板上,並藉由連接器(例如微凸塊)連接至轉接板。
半導體封裝結構可以無線資料及通訊系統來製作,其包括不同射頻(radio frequency,RF)傳輸結構,有時建立於晶片上或封裝結構內。可藉由稱為傳輸線之導電結構將電磁射頻波或信號傳送通過封裝結構或裝置。傳輸線可用於例如將單晶微波積體電路(Monolithic Microwave Integrated Circuit,MMIC)中的個別電子元件內連接,以及用於將微波多晶片模組(Multi Chip Modules,MCMs)中的單晶微波積體電路內連接。
通常,傳輸線包括至少二個導電部件或導線,其中之一形成一接地線(亦可視為一「接地面」),另外一個形成一信號傳輸線。信號傳輸線以多種方式排列,並與一個或多個接地面或接地線結合而形成不同類型的導電傳輸線,例如微帶線(microstrip)、共平面波導(coplanar waveguide,CPW)、接地共平面波導(coplanar waveguide,CPW)傳輸線,以提供不同射頻信號的用途。信號傳輸線及接地導電部件或接地面通常由某些類型的絕緣基板或材料(例如介電質)來支持。
隨著半導體技術的持續進步及晶片封裝尺寸的微縮,藉由實施例如三維積體電路晶粒堆疊,導電之互補式金氧半導體(complementary metal-oxide semiconductor,CMOS)
結構中的金屬層之間的距離變得更小,使金屬層之間的電容逐漸變大並而降低射頻裝置的效能。此外,隨著在先進半導體製作技術節點(例如20奈米製程)中晶粒封裝結構的微縮,要將傳輸線設計及製作於單一晶片或晶粒上變得越來越困難,故需要可用於設計及製作具有提昇效能之傳輸線的方法及裝置。
本發明一實施例提供一種封裝結構,包括:一裝置,包括:一基板;一絕緣層,位於基板之一第一側邊;以及一第一重佈線,位於裝置內;一微凸塊層,位於裝置上,包括一線狀微凸塊,其與第一重佈線以絕緣層分隔;以及一傳輸線,包括作為一接地面之第一重佈線及作為一信號傳輸線之線狀微凸塊。
本發明另一實施例提供一種封裝結構,包括:一第一裝置,包括:一基板;以及一絕緣層,位於基板上;以及一微凸塊層,位於第一裝置上,包括:一第一線狀微凸塊;一第二線狀微凸塊;以及一第三線狀微凸塊;其中,第一線狀微凸塊及第二線狀微凸塊形成一傳輸線之一對接地面,第三線狀微凸塊形成傳輸線之一信號傳輸線,且第一線狀微凸塊、第二線狀微凸塊及第三線狀微凸塊位於同一平面上並位於絕緣層之頂部,且彼此以一底膠材料分隔。
本發明又一實施例提供一種傳輸線之形成方法,包括:提供一裝置,包括:一基板;一絕緣層,位於基板之一第一側邊;以及一第一重佈層,位於裝置內,其中第一重佈層為傳輸線之一接地面;於裝置上形成一第一線狀微凸塊,藉由
絕緣層與第一重佈層分隔,其中第一線狀微凸塊為傳輸線之一信號傳輸線;以及以一絕緣底膠材料覆蓋第一線狀微凸塊。
100‧‧‧半導體裝置封裝結構
281、282、283‧‧‧開口槽
301‧‧‧裝置
302‧‧‧基板
303‧‧‧通孔電極
311‧‧‧介電層
321‧‧‧接觸焊墊
341‧‧‧鈍化保護層
361、371‧‧‧絕緣層
390‧‧‧凸塊底層金屬線
391‧‧‧凸塊底層金屬焊墊
470、482、484‧‧‧線狀微凸塊
471‧‧‧焊料凸塊
473‧‧‧鎳層
475‧‧‧銅層
480、4801、489‧‧‧第一重佈層/銅金屬層/接地面(接地面線、接地面重佈層)
481、4802‧‧‧第二重佈層
483‧‧‧介層窗
485‧‧‧微凸塊
490‧‧‧傳輸線
571‧‧‧底膠
601‧‧‧晶粒
603‧‧‧連接器
第1a~1f圖為數個剖面圖及一俯視圖,用以說明本發明中使用微凸塊層於封裝結構中形成微帶線傳輸線的一些實施例。
第2a~2e圖為數個剖面圖及一三維示意圖,用以說明本發明中使用微凸塊層於封裝結構中形成共平面光導傳輸線的一些實施例。
第3a~3d圖為數個剖面圖及一三維示意圖,用以說明本發明中使用微凸塊層於封裝結構中形成接地共平面光導傳輸線的一些實施例。
本揭露內容之實施例的製作及使用討論如下。然而應知曉的是,本揭露內容之實施例提供多個可實施於不同特定上下文條件中的可用概念。所討論之特定實施例係用以本揭露內容的特定製作及使用方式,並非用以限制本揭露內容。
如下所述,本揭露內容揭示了使用微凸塊層形成具有傳輸線之半導體裝置封裝結構的方法及裝置。此微凸塊層可包括微凸塊及線狀微凸塊,形成於一頂部晶粒與一底部晶粒之間,或一晶粒與一轉接板之間。可使用一裝置上的線狀微凸塊形成一信號傳輸線。可使用一裝置內的重佈層(redistribution layer,RDL)或使用額外線狀微凸塊形成一接地面。形成接地
面之重佈層可包括開口槽。線狀微凸塊上方及下方之底部裝置及頂部裝置可具有重佈層,以形成接地面的一部份。如此形成之傳輸線具有低電阻,並可節省傳輸線所佔有的區域。
應知曉的是,當元件或膜層被描述為「位於(另一元件或膜層)上」、「連接至」或「連接至」另一元件或膜層,其可直接位於另一元件或膜層上,或可直接「連接至」或「連接至」另一元件或膜層或另一相關元件。相反地,當一元件被描述為「直接位於(另一元件或膜層)上」、直接「連接至」或「連接至」另一元件或膜層,則不存在前述相關元件或膜層。
應知曉的是,雖然此處使用第一、第二、第三等名詞以描述不同元件、構件、區域、膜層、及/或區段,這些元件、構件、區域、膜層、及/或區段並不限於這些名詞。這些名詞僅用以分辨一元件、構件、區域、膜層、或區段與其它區域、膜層、或區段。因此,後述討論之一第一元件、構件、區域、膜層、或區段在不背離本發明所教示的概念時,亦可稱為一第二元件、構件、區域、膜層、或區段。
此處所使用之空間相對名詞,例如「之下」、「下方」、「低於」、「上方」、「高於」等等,係為了便於描述圖式所繪示之一元件或特徵與另一元件或特徵的關係。應知曉的是,這些空間相對名詞並非用以表示裝置在圖式所繪示者之外在使用或操作時的其它方位。舉例而言,若將圖式中裝置翻轉,則描述為在其它元件「下方」或「之下」的元件會位於其它元件「上方」。因此,例示性名詞「上方」或「下方」皆可同時代表「上方」或「下方」的方位。裝置亦可導向於其它方位(旋
轉90°或其它方位),此處之空間相對描述因而可以前述相同方式來解讀。
此處所使用的術語僅用以描述例示之特定實施例,並非用以限定本發明。此處所使用之單一形式的「一」及「前述」亦包括了複數形式,除非有明文指定。應知曉的是,當在說明書中使用名詞「包括」時,係指出存在所列舉之特徵、數字、步驟、操作、元件、及/或構件,但並非排除存在或加入一個或多個其它特徵、數字、步驟、操作、元件、構件、及/或前述之組合。
說明書中所使用的「一實施例」係指與實施例有關之一特定特徵、結構、或特性包括於至少一實施例中。因此,說明書中出現「在一實施例中」未必意指同一實施例。再者,特定特徵、結構、或特性可以任意適當方式結合至一個或多個實施例中。應知曉的是,後述圖式並非依尺度繪製,其僅用以繪示說明。
第1a圖之剖面圖繪示了本發明中使用微凸塊層於封裝結構中形成微帶線傳輸線的一些實施例。通常,微帶線傳輸線包括由一薄平導電部件所形成之一信號傳輸線及一接地面,其中信號傳輸線與接地面平行,且以某些類型之絕緣基板或材料(例如一介電質)與接地面分隔。
如第1a圖所示,半導體裝置封裝結構100包括傳輸線490,其可形成於裝置301上。裝置301可包括:具有通孔電極(through vias,TV)303之基板302、介電層311、複數接觸焊墊321、鈍化保護層341、絕緣層361、包括區段480及489之
重佈層(redistribution layer,RDL)、另一絕緣層371、以及凸塊底層金屬線390的凸塊底層金屬層(under bump metal layer,UBM layer),其包括覆蓋於絕緣層371開口之凸塊底層金屬焊墊391及在與重佈層區段480(或簡稱為第一重佈層480)平行之絕緣層371上。可於裝置301上形成一微凸塊層,微凸塊層可包括與第一重佈層480平行之凸塊底層金屬線390上之線狀微凸塊470、及設置於凸塊底層金屬焊墊391上之微凸塊485,其進一步連接至裝置301內的重佈層489。可於裝置301上設置晶粒601,其藉由連接器603連接至微凸塊485。可於裝置301與晶粒601之間的縫隙填充底膠571,以覆蓋線狀微凸塊470、微凸塊485、及連接器603。這些結構分別詳細討論於後述段落。
第一重佈層480、以絕緣層371與第一重佈層480分隔之線狀微凸塊470、及線狀微凸塊470下方之凸塊底層金屬線390形成傳輸線490,其中第一重佈層480為接地面,線狀微凸塊470及凸塊底層金屬線390形成信號傳輸線。在其它一些實施例中,可不存在凸塊底層金屬線390,可將線狀微凸塊470單獨設置於絕緣層371上來作為信號傳輸線。
裝置301可為一轉接板,包括一基板,其具有形成於基板內之通孔電極,以及複數接觸焊墊、鈍化保護層、絕緣層、重佈層、及凸塊底層金屬層。或者,裝置301亦可為一晶片或一積體電路晶粒的一部份,其可為一晶粒的前側或背側。當裝置301為一晶粒的一部分時,於積體電路裝置301上可設置晶粒601,並藉由連接器(例如微凸塊)進一步連接至一轉接板以形成一封裝結構,例如三維積體電路封裝結構(3DIC)。
在裝置301為一晶粒的一部分的情況下,其可稱為一底部晶粒,而晶粒601可稱為一頂部晶粒。當裝置301為一晶粒的背側時,可隨後藉由晶粒301及601之面對背方式堆疊來形成封裝結構100。當裝置301為一晶粒的前側時,可隨後藉由晶粒301及601之面對面方式堆疊來形成封裝結構100。或者,裝置301亦可為不具有通孔電極、上述任一或全部膜層之一封裝基板。可選擇性地使用這些裝置及任意其它適當裝置,其皆包含於本發明之範疇。
裝置301之基板302可為例如摻雜或未摻雜之矽基板、或絕緣層上矽晶(silicon-on-insulator,SOI)之主動層,其可用以提供裝置301支持。然而,基板302亦可為玻璃基板、陶瓷基板、高分子基板、或可提供適當保護及/或內連接功能之其它任意基板。這些及其它適當材料皆可用於基板302。可於基板302中形成複數主動或被動元件,例如電晶體、電容、電阻等等,其未繪示於第1a圖中。如本發明技術領域中具有通常知識者所知曉,可於裝置301的設計中使用不同主動或被動元件以產生所期望的結構及功能需求。
可形成貫穿基板302的複數通孔電極303。可藉由塗佈並顯影適當光阻隨後蝕刻基板302以產生貫穿孔來形成通孔電極303。可將用於通孔電極303之開口形成為延伸進基板302中至少大於其最終所需高度的深度。因此,此深度可為基板302表面下方的約1微米至約700微米之間。用於通孔電極303之開口可具有介於約1微米至約100微米之間的直徑,隨後可藉由一阻障層及一導電材料填充用於通孔電極303之開口,其可
使用例如化學氣相沈積(chemical vapor deposition,CVD)製程、電漿輔助化學氣相沈積(plasma enhanced chemical vapor deposition,PECVD)製程、濺鍍或有機金屬化學氣相沈積(metal organic chemical vapor deposition,MOCVD)製程等製程。可藉由一研磨製程(例如一化學機械研磨製程)移除用於通孔電極303之開口以外過剩的阻障層及導電材料。隨後,可藉由一平坦化製程(例如化學機械研磨或蝕刻製程)由基板302第二側邊實施一薄化製程,以露出用於通孔電極303之開口,並以延伸通過基板302之導電材料形成通孔電極303。可於基板302上形成介電層311,介電層311可為複數子層的集合,例如具有不同內嵌金屬層之金屬間介電層。
可於介電層311上形成複數接觸焊墊321。接觸焊墊321可藉由鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)、銀(Ag)、或其它導電材料來製作。可使用電解電鍍、濺鍍、物理氣相沈積、無電解電鍍製程來沈積接觸焊墊321。接觸焊墊321的尺寸、形狀、位置僅為繪示說明之用,其不限於此。複數接觸焊墊321可為相同或不同尺寸。
可於基板302、介電層311、及接觸焊墊321上形成鈍化保護層341,以作為結構支持及物理隔離。鈍化保護層341可使用氮化矽、二氧化矽、氮氧化矽、聚亞醯胺、苯并環丁烯(benzocyclobutene,BCB)、聚苯并噁唑(polybenzoxazole,PBO)、或其它絕緣材料來製作。可藉由使用一罩幕定義之光阻蝕刻製程移除鈍化保護層341的一部分來製作鈍化保護層341之開口,以露出接觸焊墊321。所製作之開口的尺寸、形狀、
位置僅用於繪示說明,其不限於此。
可於鈍化保護層341上及鈍化保護層之開口上形成絕緣層361(例如一高分子層361),以覆蓋接觸焊墊321。可於絕緣層361形成一開口以露出接觸焊墊321。可藉由使用一罩幕定義之光阻蝕刻製程移除絕緣層361的一部分來製作絕緣層361之開口,以露出接觸焊墊321。所製作之開口的尺寸、形狀、位置僅用於繪示說明,其不限於此。
可於絕緣層361上形成第一重佈層480及489。第一重佈層489可覆蓋露出之接觸焊墊321,但第一重佈層480可不連接至任何絕緣層361或371內的接觸窗或導電部件。反之,第一重佈層480可作為用於傳輸線490之接地面。雖然第1a圖係繪示單一介電層及內連接,但第一重佈層480及489亦可形成為介電質及導電材料之交替膜層,並可藉由任意適當製程形成(例如沈積、鑲嵌、雙重鑲嵌製程等)。第一重佈層480及489可藉由例如鋁、銅、或銅合金來製作。可藉由電解電鍍法、濺鍍法、物理氣相沈積法、無電解電鍍法來製作第一重佈層480及489。可藉由單一膜層或使用例如鈦、鈦鎢合金、氮化鉭、鉭、或鉻之接著層的多重膜層來製作第一重佈層480及489。裝置301可包括複數重佈層,以依據半導體裝置功能形成層間內連接之網路。
可於第一重佈層480及489上形成另一絕緣層371,其可為裝置301之頂層及表層。可形成絕緣層371之開口以露出第一重佈層489,但絕緣層371亦可覆蓋於第一重佈層480。可藉由使用一罩幕定義之光阻蝕刻製程移除絕緣層371的
一部分來製作絕緣層371之開口。所製作之開口的尺寸、形狀、位置僅用於繪示說明,其不限於此。絕緣層371可由高分子形成,例如以環氧樹脂、聚亞醯胺、苯并環丁烯、聚苯并噁唑、或其它絕緣材料來製作,但亦可使用其它相對軟的材料,其通常為有機介電材料。形成方法包括旋塗法或其它一般常用方法。絕緣層371的厚度可介於例如約5微米至約30微米。本敘述內容所記載之尺寸僅為例示之用,其可隨著積體電路的尺寸微縮而改變。
凸塊底層金屬層可包括凸塊底層金屬焊墊391及凸塊底層金屬線390。可將凸塊底層金屬焊墊391形成於絕緣層371之開口周圍並連接至第一重佈層489。可將凸塊底層金屬線390形成為與第一重佈層480平行,並以絕緣層371與第一重佈層480分隔。凸塊底層金屬焊墊391及凸塊底層金屬線390可由銅或銅合金形成,其可包括銀、鉻、鎳、錫、金、及前述之組合。可於前述銅層上形成額外膜層,例如一鎳層、一無鉛預焊層、或前述之組合。凸塊底層金屬焊墊391及凸塊底層金屬線390可具有介於約1微米至約20微米之間的厚度。凸塊底層金屬焊墊391亦可稱為接觸焊墊。
前述裝置301僅為一例示性之實施例,其可有多種其它不同於第1a圖及上述內容所述者之變化。舉例而言,在某些實施例中絕緣層361可不存在,在某些實施例中可具有鈍化保護層341。裝置301可在一絕緣層中僅具有一個重佈層。
晶粒601可藉由微凸塊層而與裝置301進行封裝,而晶粒601與裝置301之間的縫隙可藉由一底膠571覆蓋。晶粒
601連接至連接器603,其設置於微凸塊層中的微凸塊485上。
可使用連接器603提供微凸塊485與晶粒601之間的連接。連接器603可為接觸凸塊,例如微凸塊或控制崩潰晶片接合(controlled collapse chip connection,C4)之凸塊,並可包括一材料(例如錫)或其它適當材料(例如銀或銅)。在一實施例中,連接器603可為焊錫(tin solder)凸塊,可藉由任意適當方法(例如蒸鍍法、電鍍法、印刷法、移焊法、焊球放置法等)將一層錫層形成為較佳厚度(約100微米)來形成連接器603。於前述結構上形成錫層後,可實施一回流製程以將材料形塑為所期望之凸塊形狀。
可於晶粒601與裝置301之間使用底膠571來強化晶粒601對裝置301的附著能力,並防止熱應力使晶粒601與裝置301之間的連接斷裂。通常,選擇底膠571所使用的材料(例如有機樹脂)以控制其熱膨脹及收縮係數。首先,塗佈液體有機樹脂,使其流入晶粒601與裝置301表面之間的縫隙,隨後在其固化時控制發生於底膠內的收縮。
微凸塊層可包括微凸塊485及線狀微凸塊470,其中微凸塊485被用以連接至其它晶粒,例如晶粒601,線狀微凸塊470則為傳輸線490的一部分。可在少量或沒有額外成本下同時形成線狀微凸塊470及微凸塊485,其可為相同高度,並可由相同材料製成。可藉由微凸塊485的高度來定義微凸塊層的高度,其視使用於封裝結構的技術而定。舉例而言,對於目前的技術,微凸塊層的高度可在約10微米至約50微米的範圍之內,例如為約27微米。
微凸塊485可包括形成於銅層475上之焊料凸塊471。可於焊料凸塊471與銅層475之間選擇性形成鎳層473。焊料凸塊471可包括導電焊料材料,例如錫、鎳、金、銀、銅、鉍、前述之合金、或前述材料與其它導電材料之組合。舉例而言,焊料凸塊471可為銅-錫銀合金焊料凸塊。可藉由例如濺鍍法、蒸鍍法、電鍍法、印刷法、移焊法、焊球放置法等先將銅層475形成為例如約15微米之厚度來形成微凸塊485後,再形成鎳層473,最後形成焊料層471(例如一無鉛焊料錫銀合金層),並依序使用相同或相似方法形成各層。隨後,可實施一回流步驟以將焊料層471形塑為所期望之凸塊形狀,如焊料凸塊471所示。亦可使用可產生微凸塊485之任意適當方法,例如可使用新控制崩潰晶片接合製程(Controlled Collapse Chip Connection New Process,C4NP)來製作微凸塊485。
可將微凸塊485設置於裝置301之凸塊底層金屬焊墊391上,其有時可視為一接觸焊墊。可將凸塊底層金屬焊墊391填充或部份填充於絕緣層371之一開口。可進一步將凸塊底層金屬焊墊391連接至一金屬層,例如裝置301內之第一重佈層489或凸塊底層金屬焊墊391下方之一接觸焊墊321。微凸塊485之高度尺寸可為約10微米至約50微米。然而隨著特徵尺寸及封裝尺寸的持續下降,前述實施例中的尺寸可變得比上述尺寸小。另一方面,微凸塊485可具有較大的尺寸,例如一覆晶凸塊或一封裝凸塊的尺寸,視其在特定用途的效益而定。
可藉由實質相似於用於微凸塊485的材料來製作線狀微凸塊470。可將線狀微凸塊470設置於凸塊底層金屬層
390上,其與第一重佈層480平行。第一重佈層480、以絕緣層371與第一重佈層480分隔之線狀微凸塊470、及線狀微凸塊470下方之凸塊底層金屬層390形成傳輸線490,其中第一重佈層480為接地面,線狀微凸塊470及凸塊底層金屬層390則形成信號傳輸線。
如第1a圖所示,線狀微凸塊470(其可為信號傳輸線的一部份)可包括複數膜層:例如凸塊底層金屬層390上的膜層475可為一銅層,膜層475上的膜層473可為一鎳層,膜層473上的膜層471可為一無鉛焊料例如銀錫合金。另一方面,線狀微凸塊470亦可為僅二層,例如凸塊底層金屬線390上之膜層475可為一銅層,膜層471可為一無鉛焊料層(例如錫銀合金),而不具有由鎳所構成之膜層473。膜層471可為由錫銀合金所製作之一無鉛焊料層,其具有銀約1%至約2%,錫約99%至約98%。前述三層膜層471、473、475的高度可為約略相同或不相同,其可依據不同需求而改變。舉例而言,由銅所構成之膜層475、由鎳所構成之膜層473、由無鉛焊料所構成之膜層471的高度比例可為約15/1.5/10。線狀微凸塊470的總高度可在約10微米至約50微米之範圍內,例如27微米。在其它一些實施例中,信號傳輸線470及接地面480可具有約0.5~2微米之厚度。
線狀微凸塊470可為寬度為約10微米至約100微米的矩形。線狀微凸塊470的形狀可為窄的、寬的、或呈錐形(tapered)。線狀微凸塊470之主體部份的厚度可為實質一致。線狀微凸塊470可具有其它形狀,例如俯視為圓形、八角形、矩形、在彼此相對之終端部份具有二梯形之細長六角形、橢圓
形、鑽石形。
在一些實施例中,為求效能而期望傳輸線490中接地面寬度為信號傳輸線寬度的約1.5倍,此約為線狀微凸塊470之寬度。為了更好的效能,在一些實施例中,進一步期望接地面線480寬度成為信號傳輸線470寬度的約2倍。此外,寬度係視接地面線480與信號傳輸線470之間的距離而定,其可藉由絕緣層371或其它一些介電層或基板來填充。隨著接地面線480與信號傳輸線470之間的距離增加,信號傳輸線470所對應的寬度也會增加。在一些實施例中,在接地面線480與信號傳輸線470之間的距離為20微米時,信號傳輸線470的理想寬度為約27.6微米。
第1a圖之封裝結構100的簡圖繪示於第1(b)圖中。如第1b圖所示,可將封裝結構100形成於裝置301上。裝置301包括基板302、基板302上之絕緣層371、裝置301內之第一重佈層480以及絕緣層371上之凸塊底層金屬線390。可將線狀微凸塊470形成於裝置301上方並與凸塊底層金屬線390接觸。第一重佈層480、以絕緣層371與第一重佈層480分隔之線狀微凸塊470以及線狀微凸塊470下方之凸塊底層金屬線390形成傳輸線490,其中第一重佈層480為接地面,線狀微凸塊470及凸塊底層金屬線390則形成信號傳輸線。或者,第一重佈層480亦可為信號傳輸線,線狀微凸塊470及凸塊底層金屬線390則形成接地面,如第1c圖所示。一底膠471可覆蓋線狀微凸塊470及凸塊底層金屬線390。可將一晶粒設置於裝置301及底膠571上方,並藉由連接器連接至微凸塊,其未繪示於第1b圖中。第1b圖所示
之封裝結構100僅為簡圖,封裝結構100中亦可具有其它未繪示之膜層。舉例而言,在第一重佈層480下方可具有更多膜層,例如低介電常數金屬間介電層(inter-metal dielectric,IMD)之銅金屬層、鈍化保護層等等。
傳輸線490的另一實施例以相似方式繪示於第1d圖中。如第1d圖所示,可將封裝結構100形成於裝置301上。裝置301可包括基板302及位於基板302上之絕緣層371。裝置301進一步包括一第一重佈層480及位於絕緣層371內及基板302上之一第二重佈層481。可藉由介層窗483連接第一重佈層480及第二重佈層481。可於裝置301上方形成線狀微凸塊470。在本實施例中,無凸塊底層金屬線位於線狀微凸塊470下方。底膠571可覆蓋線狀微凸塊470。可將一晶粒設置於裝置301及底膠571上方,並藉由連接器連接至微凸塊,其未繪示於第1d圖中。重佈層480、481及以絕緣層371與重佈層480、481分隔之線狀微凸塊470形成傳輸線490,其中重佈層480、481為接地面,線狀微凸塊470則為信號傳輸線。或者,第二重佈層481亦可為其它一些金屬層,而非一第二重佈層。舉例而言,可將寬度為約0.1微米至約3.5微米之銅金屬層481連接至第一重佈層480並一起形成接地面,且線狀微凸塊470為信號傳輸線。第1d圖中的各個部件細節可與第1a圖所繪示者實質相同。
傳輸線490的另一實施例繪示於第1e圖中。如第1e圖所示,可將封裝結構100形成於裝置301上。裝置301包括基板302及絕緣層371,其中絕緣層371位於基板302的第一側邊。裝置301可進一步包括位於基板302相對於前述第一側邊之一
第二側邊的一第一重佈層480。可於裝置301上形成線狀微凸塊470,線狀微凸塊470可與絕緣層371接觸。或者,線狀微凸塊470亦可位於絕緣層371上且不與絕緣層371接觸。在本實施例中,於線狀微凸塊470下方不具有凸塊底層金屬線。或者,於線狀微凸塊470下方亦可形成凸塊底層金屬線。底膠571可覆蓋線狀微凸塊470。可將一晶粒設置於裝置301及底膠571上,並藉由連接器連接至微凸塊,其未繪示於第1e圖中。第一重佈層480及以絕緣層371及基板302與第一重佈層480分隔之線狀微凸塊470形成傳輸線490,第一重佈層480為接地面,線狀微凸塊470則為信號傳輸線。第1e圖中的各個元件細節可與第1a圖所繪示者實質相同。
傳輸線490之另一實施例的俯視圖繪示於第1f圖。如第1f圖所示,可將封裝結構100形成於基板302上,其可為一裝置之基板。可將第一重佈層480形成於基板302上,並位於未繪示之一絕緣層內。可於第一重佈層480上方形成線狀微凸塊470。第一重佈層480、以絕緣層與第一重佈層480分隔之線狀微凸塊470形成傳輸線490,第一重佈層480為接地面,線狀微凸塊470則為信號傳輸線。第一重佈層480包括一個或複數個開口槽281、282、及283。開口槽281、282、及283可減緩波速並減少第一重佈層480所需長度,以達到期望效能。可僅具有一個開口槽或其它任意數量之開口槽,而非第1f圖所繪示之三個開口槽。第1f圖中的各個元件細節可與第1a圖所繪示者實質相同。
第1a~1f圖所繪示之微帶線(microstrip)傳輸線
僅為傳輸線的一種。第2a~2c圖繪示了本發明另外一些實施例中使用微凸塊層形成於封裝結構內之共平面波導(coplanar waveguide,CPW)傳輸線的剖面圖及三維示意圖。共平面波導傳輸線係藉由一對接地面分隔一信號傳輸線而形成,其全部位於同一平面並位於一介電介質的頂部。
如第2a及2b圖所示,可將包括共平面波導傳輸線490之封裝結構100形成於裝置301上。裝置301可包括基板302及位於基板302上之絕緣層371。裝置301可具有其它未繪示之膜層(例如鈍化保護層)以及接觸窗。可於裝置301上方形成包括線狀微凸塊470、484、及482之微凸塊層。線狀微凸塊470、484、及482可與絕緣層371接觸。或者,線狀微凸塊470、484、及482亦可位於絕緣層371上方且不與絕緣層371接觸。在第2a圖所繪示之實施例中,於線狀微凸塊470下方不具有凸塊底層金屬線。或者,於線狀微凸塊470、484、及482下方亦可形成凸塊底層金屬線390,如第2b圖所繪示。底膠571可覆蓋線狀微凸塊470、484、及482。可將一晶粒設置於裝置301及底膠571上,並藉由連接器連接至微凸塊,其未繪示於第2a及2b圖。
如第2a圖所示,線狀微凸塊470、484、及482形成傳輸線490,線狀微凸塊484及482為一對接地面,線狀微凸塊470則為信號傳輸線。如第2b圖所示,線狀微凸塊470、484、482以及連接至各個線狀微凸塊之凸塊底層金屬線390形成傳輸線490,線狀微凸塊484、482及其連接之凸塊底層金屬線390為一對接地面,線狀微凸塊470及其連接之凸塊底層金屬線390則為信號傳輸線。線狀微凸塊470、484、482全部皆位於同一
平面上並位於一介電介質頂部(例如絕緣層371),且以底膠571分隔。第2a~2b圖中的各個元件細節可與第1a圖所繪示者實質相同。
或者,如第2c圖所示,對於封裝結構100,亦可於裝置301內形成一些額外第一重佈層480並連接至線狀微凸塊470、484、及482,以形成傳輸線490。線狀微凸塊484、482及其連接之第一重佈層480為一對接地面,線狀微凸塊470及其連接之第一重佈層480則為信號傳輸線。線狀微凸塊470、484、482及其連接之第一重佈線480全部皆位於同一平面上並位於一介電介質頂部(例如絕緣層371),且以底膠571及絕緣層371分隔。第2c圖中的各個元件細節可與第2a~2b圖及第1a圖所繪示者實質相同。
或者,如第2d圖所示,封裝結構100亦可進一步包括位於線狀微凸塊470、484、482及底膠571上方之一第二裝置601。第二裝置601亦可包括一基板302及一絕緣層371。可將第一重佈層4801連接至裝置601內的各個線狀微凸塊470、484、及482,將第二重佈層4802連接至裝置301內的各個線狀微凸塊470、484、及482。可藉由第一重佈層4801、第二重佈層4802、及裝置301與裝置601之間的線狀微凸塊470、484、482來形成傳輸線490。線狀微凸塊484、482及其連接之重佈層4801、4802為一對接地面,線狀微凸塊470及其連接之重佈層4801、4802則為信號傳輸線。線狀微凸塊470、484、482及其連接之重佈層4801、4802皆位於同一平面上並位於一介電介質頂部(例如絕緣層371),且以底膠571及絕緣層371分隔。第2d圖中的各個
元件細節可與第2a~2b圖及第1a圖所繪示者實質相同。
裝置301及裝置601可包括基板302及位於基板302上之絕緣層371。裝置301及裝置601可具有其它未繪示之膜層,例如鈍化保護層、凸塊底層金屬層、及接觸窗。可將線狀微凸塊470、484、及482形成於裝置301上方以作為一微凸塊層。裝置301可為轉接板或為晶片或積體電路晶粒的一部份,其可為一晶粒或一封裝基板的背側或前側。同樣地,裝置601可為轉接板或為晶片或積體電路晶粒的一部份,其可為一晶粒或一封裝基板的背側或前側。可於這些裝置及其它任意適當裝置中擇一使用,本發明之範疇並不限於上述實施例。
傳輸線490之另一實施例的三維示意圖繪示於第2e圖中。第2e圖所示之傳輸線490在一些剖面方向中可具有第2d圖所示之剖面。第一重佈層4801可為第2d圖中平鋪於頂部裝置601之絕緣層中的重佈線,第二重佈層4802可為第2d圖中平鋪於底部裝置301之絕緣層中的重佈線。可將複數線狀微凸塊470、482、及484連接至重佈層4801及4802,複數線狀微凸塊484、482及其連接之重佈層4801、4802為一對接地面,複數線狀微凸塊470及其連接之重佈層4801、4802則為信號傳輸線。複數線狀微凸塊470、484、482及其連接之重佈層4801、4802全部皆位於同一平面上並位於一介電介質頂部(例如絕緣層371),且以底膠571及絕緣層371分隔,如第2d圖所示。
於介電質相對側提供接地面時會形成一共平面波導傳輸線的變形,其可稱為一有限接地面共平面波導(finite ground-plane coplanar waveguide,FGCPW)傳輸線,或簡稱為
一接地共平面波導(grounded coplanar waveguide,GCPW)。第3a~3d圖繪示了本發明一些實施例中使用微凸塊層於封裝結構內形成接地共平面波導傳輸線的剖面圖及三維示意圖。
如第3a圖所示,可將包括接地共平面波導傳輸線490之封裝結構100形成於裝置301上。裝置301可包括基板302及位於基板302上之絕緣層371。第一重佈層480位於裝置301內。裝置301可具有其它未繪示之膜層,例如低介電常數之金屬間介電層的銅金屬層、鈍化保護層、凸塊底層金屬層、及接觸窗。可將包括線狀微凸塊470、484、及482之一微凸塊層形成於裝置301上方。線狀微凸塊470、484、及482可與絕緣層371接觸。或者,線狀微凸塊470、484、及482亦可位於絕緣層371上方且不與絕緣層371接觸。在本實施例中,於線狀微凸塊470下方不具有凸塊底層金屬線。或者,於線狀微凸塊470、484、及482下方亦可形成一凸塊底層金屬線。底膠571可覆蓋線狀微凸塊470、484、及482上。可將一晶粒設置於裝置301及底膠571上,並藉由連接器連接至微凸塊,其未繪示於第3a圖中。
線狀微凸塊470、484、482及第一重佈層480形成接地共平面波導傳輸線490,線狀微凸塊484及482為一對接地面,第一重佈層480為一第三接地面,線狀微凸塊470則為信號傳輸線。線狀微凸塊470、484、及482全部皆位於同一平面上並位於一介電介質頂部(例如絕緣層371),且以底膠571分隔。或者,如第3b圖所示,亦可將複數重佈層區段480形成於裝置301內,並可將線狀微凸塊470形成於裝置301上,重佈層480為信號傳輸線,線狀微凸塊470則為接地面。第3a及3b圖中的各
個元件細節可與第2a圖及第1a圖所繪示者實質相同。
或者,如第3c圖所示,亦可將接地面重佈層480藉由介層窗483連接至線狀微凸塊484及482(其亦可為接地面),以形成用於接地共平面波導傳輸線490之接地面。線狀微凸塊470仍為信號傳輸線。線狀微凸塊470、484、及482全部皆位於同一平面上並位於一介電介質頂部(例如絕緣層371),且以底膠571及絕緣層371分隔。第3c圖中的各個元件細節可與第1a、2a、3a圖所繪示者實質相同。
或者,第3c圖之接地共平面波導傳輸線的三維示意圖亦可如第3(d)圖所示。可將第一重佈層480包含於第3c圖所示之裝置301內,並連接至微凸塊層之線狀微凸塊484及482。第一重佈層480與其連接之線狀微凸塊484及482、以及以絕緣層與第一重佈層480分隔之線狀微凸塊470形成接地共平面波導傳輸線490,第一重佈層480及線狀微凸塊484、482為接地面,線狀微凸塊470則為信號傳輸線。第一重佈層480包括一個或複數個開口槽281。開口槽281可減緩波速並減少第一重佈層480所需長度,以達到期望效能。可僅具有一個開口槽或其它任意數量之開口槽,而非第3d圖所繪示之開口槽。第3d圖中的各個元件細節可與第1a、2a、3a圖所繪示者實質相同。
雖然本揭露內容及其優點已描述如上,應知曉的是,在不脫離本揭露內容及申請專利範圍之精神及範圍內,當可作更動、替代及改變。再者,本申請案之保護範圍並未侷限於說明書內所述特定實施例中的製程、機器、製造、物質組成、裝置、方法及步驟,任何所屬技術領域中具有通常知識者可由
本揭露內容中理解現行或未來所發展出的製程、機器、製造、物質組成、裝置、方法及步驟,只要可以在此處所述實施例中實施大體相同功能或獲得大體相同結果皆可使用於本發明中。因此,本申請案之保護範圍包括上述製程、機器、製造、物質組成、裝置、方法及步驟,每一申請專利範圍構成個別的實施例,本申請案之保護範圍亦包括各個申請專利範圍及實施例的組合。
100‧‧‧半導體裝置封裝結構
301‧‧‧裝置
302‧‧‧基板
371‧‧‧絕緣層
390‧‧‧凸塊底層金屬線
470‧‧‧線狀微凸塊
480‧‧‧第一重佈層
490‧‧‧傳輸線
571‧‧‧底膠
Claims (10)
- 一種封裝結構,包括:一裝置,包括:一基板;一絕緣層,位於該基板之一第一側邊;以及一第一重佈線,位於該裝置內,包括一第一區段;一微凸塊層,位於該裝置上,包括一線狀微凸塊及一微凸塊,其中該線狀微凸塊及該微凸塊與一平面相交,該平面平行該絕緣層的一第一側,且其中該線狀微凸塊位於該第一區段上且與該第一區段以該絕緣層分隔;以及一傳輸線,包括作為一接地面之該第一區段及作為一信號傳輸線之該線狀微凸塊。
- 如申請專利範圍第1項所述之封裝結構,其中該信號傳輸線更包括一凸塊底層金屬線,位於該絕緣層上並連接至該線狀微凸塊。
- 如申請專利範圍第1項所述之封裝結構,其中該接地面更包括一金屬層,位於該裝置內並連接至該第一區段。
- 如申請專利範圍第1項所述之封裝結構,其中該第一區段包括一開口槽。
- 一種封裝結構,包括:一第一裝置,包括:一基板;以及一絕緣層,位於該基板上;以及一微凸塊層,位於該第一裝置上,包括: 一第一線狀微凸塊;一第二線狀微凸塊;一第三線狀微凸塊;以及一微凸塊;其中,該第一線狀微凸塊及該第二線狀微凸塊形成一傳輸線之一對接地面,該第三線狀微凸塊形成該傳輸線之一信號傳輸線,其中該第三線狀微凸塊位於該第一線狀微凸塊及該第二線狀微凸塊之間,而該微凸塊為一外部連接器,且該第一線狀微凸塊、該第二線狀微凸塊、該第三線狀微凸塊及該微凸塊與一平面相交,該平面平行該絕緣層的一第一側,且彼此以一底膠材料分隔。
- 如申請專利範圍第5項所述之封裝結構,其中該第一裝置更包括:一第一凸塊底層金屬線,位於該絕緣層上並連接至該第一線狀微凸塊;一第二凸塊底層金屬線,位於該絕緣層上並連接至該第二線狀微凸塊;以及一第三凸塊底層金屬線,位於該絕緣層上並連接至該第三線狀微凸塊。
- 如申請專利範圍第5項所述之封裝結構,其中該第一裝置更包括:一第一重佈層,位於該第一裝置內並連接至該第一線狀微凸塊;一第二重佈層,位於該第一裝置內並連接至該第二線狀 微凸塊;以及一第三重佈層,位於該第一裝置內並連接至該第三線狀微凸塊。
- 如申請專利範圍第7項所述之封裝結構,更包括:一第二裝置,位於該微凸塊層上,包括一第四重佈線,位於該第二裝置內並連接至該第一線狀微凸塊;一第五重佈線,位於該第二裝置內並連接至該第二線狀微凸塊;一第六重佈線,位於該第二裝置內並連接至該第三線狀微凸塊;一第四線狀微凸塊,連接至該第一重佈線及該第四重佈線;一第五線狀微凸塊,連接至該第二重佈線及該第五重佈線;以及一第六線狀微凸塊,連接至該第三重佈線及該第六重佈線。
- 一種傳輸線之形成方法,包括:提供一裝置,包括:一基板;一絕緣層,位於該基板之一第一側邊;以及一第一重佈層,位於該裝置內,其中該第一重佈層包括一第一區段,其為該傳輸線之一接地面;於該裝置上形成一微凸塊層,其中該微凸塊層包括一第一線狀微凸塊及一微凸塊,該第一線狀微凸塊層形成於 該第一區段上,且藉由該絕緣層與該第一區段分隔,而該微凸塊為一外部連接器,其中該第一線狀微凸塊及該微凸塊與一平面相交,該平面平行該絕緣層的一第一側,且其中該第一線狀微凸塊為該傳輸線之一信號傳輸線;以及以一絕緣底膠材料覆蓋該第一線狀微凸塊。
- 如申請專利範圍第9項所述之傳輸線之形成方法,更包括:於該裝置上形成一第二線狀微凸塊及一第三線狀微凸塊以作為該傳輸線之一對額外接地面,該微凸塊、該第一線狀微凸塊、該第二線狀微凸塊及該第三線狀微凸塊與一平面相交,該平面平行該絕緣層的一第一側,且彼此以該絕緣底膠材料分隔,其中該微凸塊、該第一線狀微凸塊、該第二線狀微凸塊及該第三線狀微凸塊的對應膜層由同一材料所構成。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/750,814 US9171798B2 (en) | 2013-01-25 | 2013-01-25 | Methods and apparatus for transmission lines in packages |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201431032A TW201431032A (zh) | 2014-08-01 |
TWI528519B true TWI528519B (zh) | 2016-04-01 |
Family
ID=51222730
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW102143710A TWI528519B (zh) | 2013-01-25 | 2013-11-29 | 封裝結構及傳輸線之形成方法 |
Country Status (5)
Country | Link |
---|---|
US (4) | US9171798B2 (zh) |
JP (2) | JP2014146787A (zh) |
KR (1) | KR101508422B1 (zh) |
CN (1) | CN103972212B (zh) |
TW (1) | TWI528519B (zh) |
Families Citing this family (40)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9171798B2 (en) * | 2013-01-25 | 2015-10-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus for transmission lines in packages |
US10204876B2 (en) * | 2013-03-07 | 2019-02-12 | Maxim Integrated Products, Inc. | Pad defined contact for wafer level package |
US9269640B2 (en) | 2013-10-31 | 2016-02-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Repairing monolithic stacked integrated circuits with a redundant layer and lithography process |
US9773754B2 (en) | 2014-12-05 | 2017-09-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Input output for an integrated circuit |
US10283171B2 (en) | 2015-03-30 | 2019-05-07 | Taiwan Semicondutor Manufacturing Company, Ltd. | Stacked die semiconductor device with separate bit line and bit line bar interconnect structures |
US10379156B2 (en) | 2015-05-29 | 2019-08-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bump ball testing system and method |
US9627411B2 (en) | 2015-06-05 | 2017-04-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Three-dimensional transistor and methods of manufacturing thereof |
CN105550432A (zh) * | 2015-12-11 | 2016-05-04 | 格科微电子(上海)有限公司 | 三维集成电路芯片及其电源网络布局方法 |
US10204205B2 (en) | 2016-01-07 | 2019-02-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of determining colorability of a semiconductor device and system for implementing the same |
US10037897B2 (en) | 2016-11-29 | 2018-07-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Inter-fan-out wafer level packaging with coaxial TIV for 3D IC low-noise packaging |
US10930603B2 (en) | 2016-03-22 | 2021-02-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Coaxial through via with novel high isolation cross coupling method for 3D integrated circuits |
US10043745B2 (en) | 2016-04-01 | 2018-08-07 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor package devices integrated with inductor |
US9905471B2 (en) | 2016-04-28 | 2018-02-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuit structure and method forming trenches with different depths |
US10222412B2 (en) | 2016-06-01 | 2019-03-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | IC degradation management circuit, system and method |
US10539617B2 (en) | 2016-06-02 | 2020-01-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Scan architecture for interconnect testing in 3D integrated circuits |
US10685911B2 (en) | 2016-06-30 | 2020-06-16 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor package and manufacturing method of the same |
US9893189B2 (en) | 2016-07-13 | 2018-02-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for reducing contact resistance in semiconductor structures |
JP6798252B2 (ja) * | 2016-10-31 | 2020-12-09 | 住友電気工業株式会社 | 高周波装置 |
US10163690B2 (en) | 2016-11-30 | 2018-12-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | 2-D interconnections for integrated circuits |
IL250253B (en) | 2017-01-24 | 2021-10-31 | Arbe Robotics Ltd | A method for separating targets and echoes from noise, in radar signals |
US10510631B2 (en) * | 2017-09-18 | 2019-12-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Fan out package structure and method of manufacturing the same |
US10665554B2 (en) * | 2017-10-30 | 2020-05-26 | Taiwan Semiconductor Manufacturing Company Ltd. | Magnetic structure for transmission lines in a package system |
IL255982A (en) | 2017-11-29 | 2018-01-31 | Arbe Robotics Ltd | Detection, mitigation and prevention of mutual interference between fixed water radars in vehicles |
IL259190A (en) | 2018-05-07 | 2018-06-28 | Arbe Robotics Ltd | System and method for frequency hopping MIMO FMCW imaging radar |
US10903151B2 (en) * | 2018-05-23 | 2021-01-26 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package and method of manufacturing the same |
US10573602B2 (en) * | 2018-06-22 | 2020-02-25 | Nanya Technology Corporation | Semiconductor device and method of forming the same |
IL260695A (en) | 2018-07-19 | 2019-01-31 | Arbe Robotics Ltd | Method and device for eliminating waiting times in a radar system |
IL260694A (en) | 2018-07-19 | 2019-01-31 | Arbe Robotics Ltd | Method and device for two-stage signal processing in a radar system |
IL260696A (en) | 2018-07-19 | 2019-01-31 | Arbe Robotics Ltd | Method and device for structured self-testing of radio frequencies in a radar system |
US11171090B2 (en) * | 2018-08-30 | 2021-11-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of manufacture |
IL261636A (en) | 2018-09-05 | 2018-10-31 | Arbe Robotics Ltd | Deflected MIMO antenna array for vehicle imaging radars |
US11172142B2 (en) | 2018-09-25 | 2021-11-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | Image sensor for sensing LED light with reduced flickering |
US10861808B2 (en) | 2018-11-21 | 2020-12-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bonding structure of dies with dangling bonds |
US11094614B2 (en) * | 2019-09-23 | 2021-08-17 | Littelfuse, Inc. | Semiconductor chip contact structure, device assembly, and method of fabrication |
IL271269A (en) | 2019-12-09 | 2021-06-30 | Arbe Robotics Ltd | Radom for a planar antenna for car radar |
US11239193B2 (en) | 2020-01-17 | 2022-02-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit package and method |
US11177065B2 (en) * | 2020-03-30 | 2021-11-16 | Qualcomm Incorporated | Thermal paths for glass substrates |
US11277902B2 (en) * | 2020-05-25 | 2022-03-15 | Arbe Robotics Ltd. | Single layer radio frequency integrated circuit package and related low loss grounded coplanar transmission line |
CN116845047B (zh) * | 2023-08-30 | 2024-01-09 | 之江实验室 | 晶圆基板布线方法、装置及可读存储介质 |
CN118016638B (zh) * | 2024-04-10 | 2024-07-12 | 成都天成电科科技有限公司 | 一种适用于晶圆级封装的低损耗宽带过渡结构 |
Family Cites Families (65)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6242438A (ja) * | 1985-08-19 | 1987-02-24 | Nec Corp | 伝送用膜基板 |
KR900008647B1 (ko) * | 1986-03-20 | 1990-11-26 | 후지쓰 가부시끼가이샤 | 3차원 집적회로와 그의 제조방법 |
US5726502A (en) * | 1996-04-26 | 1998-03-10 | Motorola, Inc. | Bumped semiconductor device with alignment features and method for making the same |
JPH1022449A (ja) | 1996-07-02 | 1998-01-23 | Matsushita Electric Ind Co Ltd | 半導体装置 |
JPH10308478A (ja) * | 1997-03-05 | 1998-11-17 | Toshiba Corp | 半導体モジュール |
JP3470020B2 (ja) * | 1997-09-02 | 2003-11-25 | 日本電信電話株式会社 | 半導体集積回路の配線構造 |
JP4015746B2 (ja) | 1997-10-30 | 2007-11-28 | 松下電器産業株式会社 | 半導体装置 |
JP3465617B2 (ja) | 1999-02-15 | 2003-11-10 | カシオ計算機株式会社 | 半導体装置 |
JP2000260912A (ja) * | 1999-03-05 | 2000-09-22 | Fujitsu Ltd | 半導体装置の実装構造及び半導体装置の実装方法 |
JP3473516B2 (ja) * | 1999-09-20 | 2003-12-08 | 日本電気株式会社 | 半導体集積回路 |
JP3287346B2 (ja) * | 1999-11-29 | 2002-06-04 | カシオ計算機株式会社 | 半導体装置 |
US6614325B1 (en) | 2000-08-31 | 2003-09-02 | Northrop Grumman Corporation | RF/IF signal distribution network utilizing broadside coupled stripline |
US7271489B2 (en) * | 2003-10-15 | 2007-09-18 | Megica Corporation | Post passivation interconnection schemes on top of the IC chips |
US6879492B2 (en) * | 2001-03-28 | 2005-04-12 | International Business Machines Corporation | Hyperbga buildup laminate |
JP2003100801A (ja) * | 2001-09-25 | 2003-04-04 | Mitsubishi Electric Corp | 半導体装置 |
US6674174B2 (en) * | 2001-11-13 | 2004-01-06 | Skyworks Solutions, Inc. | Controlled impedance transmission lines in a redistribution layer |
US6635970B2 (en) * | 2002-02-06 | 2003-10-21 | International Business Machines Corporation | Power distribution design method for stacked flip-chip packages |
US7145411B1 (en) | 2002-03-18 | 2006-12-05 | Applied Micro Circuits Corporation | Flexible differential interconnect cable with isolated high frequency electrical transmission line |
JP3580803B2 (ja) | 2002-08-09 | 2004-10-27 | 沖電気工業株式会社 | 半導体装置 |
US20040089946A1 (en) * | 2002-11-12 | 2004-05-13 | Amkor Technology, Inc. | Chip size semiconductor package structure |
US20050176233A1 (en) * | 2002-11-15 | 2005-08-11 | Rajeev Joshi | Wafer-level chip scale package and method for fabricating and using the same |
US7576436B2 (en) * | 2002-12-13 | 2009-08-18 | Advanced Semiconductor Engineering, Inc. | Structure of wafer level package with area bump |
CA2418674A1 (en) * | 2003-02-07 | 2004-08-07 | Tak Shun Cheung | Transmission lines and transmission line components with wavelength reduction and shielding |
JP2004266117A (ja) | 2003-03-03 | 2004-09-24 | Fujikura Ltd | 半導体パッケージ及びその製造方法 |
JP4046026B2 (ja) * | 2003-06-27 | 2008-02-13 | 株式会社日立製作所 | 半導体装置 |
JP3983205B2 (ja) | 2003-07-08 | 2007-09-26 | 沖電気工業株式会社 | 半導体装置及びその製造方法 |
TWI233682B (en) * | 2003-08-22 | 2005-06-01 | Advanced Semiconductor Eng | Flip-chip package, semiconductor chip with bumps, and method for manufacturing semiconductor chip with bumps |
US7160756B2 (en) * | 2004-10-12 | 2007-01-09 | Agency For Science, Techology And Research | Polymer encapsulated dicing lane (PEDL) technology for Cu/low/ultra-low k devices |
JP4581768B2 (ja) | 2005-03-16 | 2010-11-17 | ソニー株式会社 | 半導体装置の製造方法 |
JP4708148B2 (ja) * | 2005-10-07 | 2011-06-22 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US7397121B2 (en) * | 2005-10-28 | 2008-07-08 | Megica Corporation | Semiconductor chip with post-passivation scheme formed over passivation layer |
JP2007123740A (ja) | 2005-10-31 | 2007-05-17 | Sony Corp | フレキシブル基板、光送受信モジュール及び光送受信装置 |
JP2007134359A (ja) | 2005-11-08 | 2007-05-31 | Casio Comput Co Ltd | 半導体装置およびその製造方法 |
KR100731544B1 (ko) * | 2006-04-13 | 2007-06-22 | 한국전자통신연구원 | 다층배선 코플래너 웨이브가이드 |
US7393477B2 (en) * | 2006-08-15 | 2008-07-01 | United Microelectronics Corp. | Method of fabricating microlens structure |
JP2008103387A (ja) | 2006-10-17 | 2008-05-01 | Murata Mfg Co Ltd | 半導体装置 |
US8558353B2 (en) * | 2006-11-15 | 2013-10-15 | Texas Instruments Incorporated | Integrated circuit having an uppermost layer comprising landing pads that are distributed thoughout one side of the integrated circuit |
US7615865B2 (en) * | 2007-05-21 | 2009-11-10 | Stats Chippac, Ltd. | Standoff height improvement for bumping technology using solder resist |
US7759212B2 (en) * | 2007-12-26 | 2010-07-20 | Stats Chippac, Ltd. | System-in-package having integrated passive devices and method therefor |
US7880297B2 (en) * | 2007-12-31 | 2011-02-01 | Mediatek Inc. | Semiconductor chip having conductive member for reducing localized voltage drop |
JP2009218841A (ja) | 2008-03-10 | 2009-09-24 | Toshiba Corp | 高周波基板 |
TW200941601A (en) * | 2008-03-19 | 2009-10-01 | Chipmos Technologies Inc | Conductive structure of a chip |
US7851345B2 (en) * | 2008-03-19 | 2010-12-14 | Stats Chippac, Ltd. | Semiconductor device and method of forming oxide layer on signal traces for electrical isolation in fine pitch bonding |
US8028406B2 (en) * | 2008-04-03 | 2011-10-04 | International Business Machines Corporation | Methods of fabricating coplanar waveguide structures |
MX2010013267A (es) * | 2008-06-24 | 2011-02-25 | Ibm | Estructura de diseño, estructura y metodo para proporcionar una linea de transmision con retardo variable en la microplaqueta con impedancia caracteristica fija. |
US8138857B2 (en) * | 2008-06-24 | 2012-03-20 | International Business Machines Corporation | Structure, structure and method for providing an on-chip variable delay transmission line with fixed characteristic impedance |
US8334170B2 (en) * | 2008-06-27 | 2012-12-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for stacking devices |
US8279025B2 (en) * | 2008-12-09 | 2012-10-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Slow-wave coaxial transmission line having metal shield strips and dielectric strips with minimum dimensions |
US8324979B2 (en) | 2009-02-25 | 2012-12-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Coupled microstrip lines with ground planes having ground strip shields and ground conductor extensions |
JP2010251707A (ja) * | 2009-03-27 | 2010-11-04 | Fujitsu Ltd | 配線基板及び半導体装置 |
US8227904B2 (en) | 2009-06-24 | 2012-07-24 | Intel Corporation | Multi-chip package and method of providing die-to-die interconnects in same |
US7977783B1 (en) * | 2009-08-27 | 2011-07-12 | Amkor Technology, Inc. | Wafer level chip size package having redistribution layers |
JP2011100989A (ja) * | 2009-10-09 | 2011-05-19 | Renesas Electronics Corp | 半導体装置 |
KR101683814B1 (ko) | 2010-07-26 | 2016-12-08 | 삼성전자주식회사 | 관통 전극을 구비하는 반도체 장치 |
CN102959699B (zh) * | 2010-08-06 | 2015-12-09 | 松下电器产业株式会社 | 电路基板及其制造方法 |
KR20120032254A (ko) | 2010-09-28 | 2012-04-05 | 삼성전자주식회사 | 반도체 적층 패키지 및 이의 제조 방법 |
US9087840B2 (en) | 2010-11-01 | 2015-07-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Slot-shielded coplanar strip-line compatible with CMOS processes |
US8368202B2 (en) | 2010-11-24 | 2013-02-05 | Advanced Semiconductor Engineering, Inc. | Semiconductor device and semiconductor package having the same |
US8704364B2 (en) | 2012-02-08 | 2014-04-22 | Xilinx, Inc. | Reducing stress in multi-die integrated circuit structures |
KR101411813B1 (ko) * | 2012-11-09 | 2014-06-27 | 앰코 테크놀로지 코리아 주식회사 | 반도체 디바이스 및 그 제조 방법 |
US9035457B2 (en) * | 2012-11-29 | 2015-05-19 | United Microelectronics Corp. | Substrate with integrated passive devices and method of manufacturing the same |
US9064705B2 (en) | 2012-12-13 | 2015-06-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus of packaging with interposers |
US8896094B2 (en) * | 2013-01-23 | 2014-11-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus for inductors and transformers in packages |
US9171798B2 (en) * | 2013-01-25 | 2015-10-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus for transmission lines in packages |
US9041215B2 (en) * | 2013-03-12 | 2015-05-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Single mask package apparatus and method |
-
2013
- 2013-01-25 US US13/750,814 patent/US9171798B2/en active Active
- 2013-04-16 KR KR20130041635A patent/KR101508422B1/ko active IP Right Grant
- 2013-04-26 CN CN201310150868.5A patent/CN103972212B/zh active Active
- 2013-11-29 TW TW102143710A patent/TWI528519B/zh active
- 2013-11-29 JP JP2013247892A patent/JP2014146787A/ja active Pending
-
2015
- 2015-10-05 US US14/875,448 patent/US10269746B2/en active Active
-
2016
- 2016-12-02 JP JP2016235294A patent/JP6297126B2/ja active Active
-
2019
- 2019-04-22 US US16/390,218 patent/US10840201B2/en active Active
-
2020
- 2020-11-16 US US17/098,602 patent/US11978712B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
JP2014146787A (ja) | 2014-08-14 |
US20190244921A1 (en) | 2019-08-08 |
US20210082848A1 (en) | 2021-03-18 |
JP2017092479A (ja) | 2017-05-25 |
US10840201B2 (en) | 2020-11-17 |
US20140211438A1 (en) | 2014-07-31 |
US9171798B2 (en) | 2015-10-27 |
CN103972212A (zh) | 2014-08-06 |
TW201431032A (zh) | 2014-08-01 |
JP6297126B2 (ja) | 2018-03-20 |
US11978712B2 (en) | 2024-05-07 |
KR101508422B1 (ko) | 2015-04-07 |
US10269746B2 (en) | 2019-04-23 |
KR20140095940A (ko) | 2014-08-04 |
CN103972212B (zh) | 2016-12-28 |
US20160027750A1 (en) | 2016-01-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI528519B (zh) | 封裝結構及傳輸線之形成方法 | |
TWI523169B (zh) | 封裝體及其製造方法 | |
US9099540B2 (en) | Three-dimensional system-in-package architecture | |
US10418350B2 (en) | Semiconductor structures for assembly in multi-layer semiconductor devices including at least one semiconductor structure | |
KR101319701B1 (ko) | TSVs에 연결된 웨이퍼 후면의 상호접속 구조 | |
US9449945B2 (en) | Filter and capacitor using redistribution layer and micro bump layer | |
US9455237B2 (en) | Bowl-shaped solder structure | |
WO2015134993A1 (en) | Thermal vias disposed in a substrate proximate to a well thereof | |
WO2015134994A1 (en) | Thermal vias disposed in a substrate without a liner layer | |
US20220359406A1 (en) | Semiconductor Packages and Method of Manufacture | |
KR102469446B1 (ko) | 반도체 구조물 및 그 형성 방법 | |
US20240312898A1 (en) | Chip-on-wafer structure with chiplet interposer |