TWI500134B - 矽穿孔基板結構及其堆疊組合 - Google Patents

矽穿孔基板結構及其堆疊組合 Download PDF

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TWI500134B
TWI500134B TW099141056A TW99141056A TWI500134B TW I500134 B TWI500134 B TW I500134B TW 099141056 A TW099141056 A TW 099141056A TW 99141056 A TW99141056 A TW 99141056A TW I500134 B TWI500134 B TW I500134B
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substrate
perforated
conductor
insulating layer
conductor portion
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TW099141056A
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TW201222763A (en
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王寵智
曾培哲
林哲歆
顧子琨
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財團法人工業技術研究院
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Priority to TW099141056A priority Critical patent/TWI500134B/zh
Priority to US12/969,250 priority patent/US20120133030A1/en
Publication of TW201222763A publication Critical patent/TW201222763A/zh
Priority to US13/845,869 priority patent/US20130214390A1/en
Priority to US14/615,922 priority patent/US9257338B2/en
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Publication of TWI500134B publication Critical patent/TWI500134B/zh

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Description

矽穿孔基板結構及其堆疊組合
本發明係關於一種立體堆疊式積體電路(Three-Dimensional Integrated Circuit,3DIC)技術，特別是指一種具有矽穿孔(Through-Silicon Via,TSV)的矽穿孔基板結構及其堆疊組合結構。
立體堆疊式積體電路因具有高效能、低耗能、低成本、小尺寸、及積體電路異質整合等優勢，極有潛力成為晶片系統(System on Chip,SoC)技術發展的新方向，而矽穿孔封裝技術更位居關鍵的角色，可克服積體電路製程微縮和低介電值材料的限制，達到低成本及高效能的晶片間電氣互連。
然而，在晶片接合或組合技術上，常發生晶片間矽穿孔接合不準確或產生凸塊的狀況，而導致晶片間訊號傳遞錯誤或失真。由此又衍生矽穿孔接合處易產生裂痕(Bump crack)的可靠度問題，或導致接合處的電阻增加，甚至產生斷路的缺陷，尚待發展新技術以解決之。
根據本發明的一方面，第一實施例提供一種矽穿孔基板結構，包含：一基板，其具有一第一表面、一第二表面、及一矽穿孔，該矽穿孔由該第一表面貫穿該基板而通至該第二表面；及一導體部，其充填該矽穿孔，且該導體部包含：一導體柱，具有一第一端及一第二端，其基面分別對應於該第一表面及該第二表面；及一延伸部，形成於該導 體柱鄰近該第一或第二端的側面上。
根據本發明的另一方面，第二實施例提供一種基板堆疊的組合結構，其包含：一第一矽穿孔基板結構，其係為上述第一實施例中所述矽穿孔基板結構可能態樣的其中一種；及一第二矽穿孔基板結構，其堆疊於該第一矽穿孔基板結構上，該第二矽穿孔基板結構亦為上述第一實施例中所述矽穿孔基板結構可能態樣的其中一種；其中該第一及第二矽穿孔基板結構的矽穿孔互相對應。
以下將參照隨附之圖式詳細描述及說明本發明之特徵、目的、功能，及其達成所使用的技術手段；但所列舉之實施例僅為輔助說明，以利對本發明有更進一步的認知與瞭解，並不因此限制本發明的範圍及技術手段。在該等實施例的說明中，各層(膜)、區域、圖案或結構形成於基板、各層(膜)、區域、墊片或圖案之「上(on)」或「下(under)」的描述，該「上」及「下」係包括所有直接(directly)或間接(indirectly)被形成物。另外，對於各層之上或下，將以圖式為基準來進行說明。而為了說明上的便利和明確，圖式中各層的厚度或尺寸，係以概略的、誇張的、或簡要的方式表示，且各構成要素的尺寸並未完全為其實際尺寸。
請參照圖1，為根據本發明第一實施例之矽穿孔基板結構的立體結構示意圖，本實施例的矽穿孔基板結構100包含：具有矽穿孔130的基板110、及充填該矽穿孔的導體部120，以建構立體堆疊式積體電路，作為多層基板之 間訊號傳輸或散熱等功能的連接通道。
該基板110通常具有上下兩面，在本實施例中稱之為第一表面111及第二表面112。該基板110內含有至少一個矽穿孔，其係由該第一表面111貫穿該基板110而通至該第二表面112的穿孔；該矽穿孔130本身具有一空間而可於其中鋪設導體，而形成該基板110上下兩側的電性連接通道。在本說明書及圖示中，僅顯示單一個矽穿孔，以作為各實施例結構或製程的說明之便，但並不以此為限，該基板110亦可含有一個以上的矽穿孔130。此外，圖1係以截面為圓形的柱體做為本實施例矽穿孔130的主體結構，但並不以此為限，該矽穿孔130亦可為方形、菱形、多邊形、或其他形狀截面的柱體，端視實際的需求而定。
如圖1所示，為了電性隔絕該矽穿孔130內的導體與該基板110內的其他電路或元件，而形成一絕緣層114於該矽穿孔130的側面131；但並不以此為限，該基板110的第一表面111及第二表面112上亦可因不同的電路製程或設計而形成絕緣層114。此外，本文所稱的基板，可以是晶粒、晶片、晶圓、用以連接晶粒或晶片至印刷電路板的中介層(interposer)、或上述中之至少二者，皆屬本實施例的可實施範圍。
充填於該矽穿孔130中的導體部120，其主體為與該矽穿孔130相對應的導體柱125，具有上下兩端，在本實施例中稱之為第一端121及第二端122，分別對應於該基板110的第一表面111及第二表面112。本實施例的特徵在於該導體柱125是充填該矽穿孔130的實心柱體，以減低 電流傳導的電阻及提高結構的可靠性。本實施例的另一特徵在於該導體柱125的第一端121或第二端122可以具有一延伸部123，形成於該導體柱125鄰近該第一端121或該第二端122的側面(side surface)上，並且圍繞該導體柱125的柱體，如圖1所示。該延伸部123的導體結構可增加複數個矽穿孔基板結構100接合時的定位面積，以提高接合定位的容忍度，及因接合不佳所導致的寄生元件或電路效應；但並不以此為限，該延伸部123可設置於該導體柱125的其中一端，或同時設置於兩端，亦可以不予設置，端視實際狀況而定。
為了進一步使複數個矽穿孔基板結構100的矽穿孔易於對準及接合，並提高接合後的結構強韌度，該導體部120更包括：一凹陷部127，其形成於該第一端121的基面(base surface)內；及一突出部128，其形成於該第二端122的基面外，如圖1的實施例所示。值得注意的是：該突出部128的面積小於或等於該凹陷部127的面積，且該突出部128的高度大於或等於該凹陷部127的高度，以利於後續的基板堆疊結構對準及接合的製作。該導體部120的成分基本上為銅或類似的金屬材料，但並不以此為限，其組成亦可為其他常用於積体電路製程的導電材料。此外，如同圖1矽穿孔130的主體結構，本實施例導體部120的截面為圓形，但並不以此為限，該導體部120亦可為方形、菱形、多邊形、或其他形狀截面的柱體，端視實際的需求而定。
上述導體部120的凹陷部127及突出部128為上凹陷下突出的態樣，其亦可為上突出下凹陷的態樣；但不以此 為限，其亦可為如圖2A所示的上下皆突出的態樣，或是如圖2B所示的上下皆凹陷的態樣；如圖2A及2B所示的態樣可相對應的使用，以提供堆疊式積體電路較佳的對準及接合，此將於後文的實施例中說明。但導體部120的凹陷部或突出部可設置於該導體柱125的其中一端，或同時設置於兩端，亦可以不予設置，端視實際案例而定。
為了建構立體堆疊式積體電路，上述第一實施例中所述各種可能態樣的矽穿孔基板結構接著進行相互對應及堆疊組合。根據本發明之第二實施例包含：一第一矽穿孔基板結構，其係為上述第一實施例中所述矽穿孔基板結構可能態樣的其中一種；及一第二矽穿孔基板結構，其堆疊於該第一矽穿孔基板結構上，該第二矽穿孔基板結構亦為上述第一實施例中所述矽穿孔基板結構可能態樣的其中一種。另外，該第一及第二矽穿孔基板結構的矽穿孔為互相對應的對準及接合，以建構立體堆疊式積體電路。
請參照圖3A至3B，為本第二實施例之基板組合結構210/220/230範例1至3的結構示意圖。該範例1及2分別為上凹陷下突出與上突出下凹陷的矽穿孔基板結構態樣的堆疊組合，而該範例3為上下皆突出及上下皆凹陷的矽穿孔基板結構態樣的堆疊組合，其中對於矽穿孔基板結構的基板110及導體部120的相關描述皆類同於該第一實施例100所敘述者，且各基板110的第一表面及第二表面及其矽穿孔的側面皆具有絕緣層114，各導體柱的第一端及第二端亦皆具有圍繞該導體柱的延伸部。其中，當各個該矽穿孔基板結構相互堆疊組合時，相鄰的矽穿孔基板結構的 突出部及凹陷部相互對應，且該突出部的面積小於或等於該凹陷部的面積，該突出部的高度大於或等於該凹陷部的高度。基板組合的製程主要是：提供接合結構的突出部及凹陷部相互對應的基板110；對準各基板110的矽穿孔及其接合結構，並進行堆疊；及施壓於該堆疊基板，使接合處的突出部及凹陷部導體因受擠壓而密合。因此，在接合結構的突出部及凹陷部設計上，該突出部的面積小於或等於該凹陷部，該突出部的高度大於或等於該凹陷部，而以金屬作為材料的導體，例如：銅，當受到擠壓則產生變形，而助於接合處的密合，更進一步減低電流傳導的電阻及提高結構的可靠性。
藉由上凹陷下突出的矽穿孔基板結構態樣的堆疊組合，以下提供更多的實施範例。範例4為各矽穿孔基板結構的導體柱的上端不具有圍繞該導體柱的延伸部，但下端則具有圍繞該導體柱的延伸部，且圖4A為各基板110的上下表面及其矽穿孔的側面皆具有絕緣層114，而圖4B為只有矽穿孔的側面具有絕緣層114的矽穿孔基板結構態樣。範例5為各矽穿孔基板結構的導體柱的下端不具有圍繞該導體柱的延伸部，但上端則具有圍繞該導體柱的延伸部，且圖5A為各基板110的上下表面及其矽穿孔的側面皆具有絕緣層114，而圖5B為只有矽穿孔的側面具有絕緣層114的矽穿孔基板結構態樣。範例6為各矽穿孔基板結構的導體柱的上下端皆不具有圍繞該導體柱的延伸部，且圖6A為各基板110的上下表面及其矽穿孔的側面皆具有絕緣層114，而圖6B為只有矽穿孔的側面具有絕緣層114的矽穿 孔基板結構態樣。
範例7為各矽穿孔基板結構的導體柱的上下端皆不具有圍繞該導體柱的延伸部，但該矽穿孔側面上的絕緣層114更延伸至該導體部120第一端或/及第二端的基面上，並形成一凹陷區域，該凹陷區域的面積小於該導體柱的截面積，藉以對準及容置另一矽穿孔基板結構可能的突出部；圖7A為各基板110的上下表面及其矽穿孔的側面皆具有絕緣層114，而圖7B為只有矽穿孔的側面具有絕緣層114的矽穿孔基板結構態樣。但請注意，在第二實施例及其各範例中所述的第一及第二矽穿孔基板結構，或圖3至7所示的上、中、下層的矽穿孔基板結構不一定為相同的第一實施例態樣(雖然圖3至7之例所示者為相同的矽穿孔基板結構態樣)，亦可進行本實施例之基板堆疊的組合結構。
以下針對本發明實施例的矽穿孔基板結構，列舉一以銅作為該導體部組成材料的製作流程作為實施範例；請同時參照圖1的矽穿孔基板結構，及圖8A至8M的各製程步驟示意圖。首先，提供一已充填金屬導體(銅)的矽穿孔基板110，其表面形成有一氧化物絕緣層114，並研磨該矽穿孔基板110的背面(第二表面)至金屬銅露出，如圖8A所示。接著電鍍阻障層(Barrier layer)401及種子層(Seed layer)402於該矽穿孔基板110的正面(第一表面)上，如圖8B所示；該阻障層401及種子層402本身皆為導體。為製作導體部120的延伸部，以光微影製程(photolithography)在該種子層402上形成適當圖案的光阻層403，如圖8C所示。接著在該種子層402上電鍍銅膜404，而在光阻層403圖 案上將不會形成銅鍍膜，如圖8D所示。接著去除光阻層，再以化學機械研磨(chemical mechanical planarization,CMP)製程研磨該矽穿孔基板11，直到該氧化物絕緣層114，如圖8E所示。接著於該矽穿孔基板110的正面上黏貼一載片(Carrier)405，如圖8F所示；該矽穿孔基板110與該載片405之間為黏著劑406。接著在該矽穿孔基板110的背面上沉積一層氧化物絕緣層114，如圖8G所示。又以光微影製程在該矽穿孔基板110的背面上形成適當圖案的光阻層407，並進行氧化物絕緣層114的蝕刻，如圖8H所示。去除光阻層，並於該矽穿孔基板110的背面上電鍍銅，如圖8I所示。接著電鍍一阻障層408及種子層409於該矽穿孔基板110的背面上，如圖8J所示。以光微影製程在該矽穿孔基板110的背面上形成適當圖案的光阻層410，並電鍍銅膜411，如圖8K所示。接著去除光阻層及裸露出的該阻障層408及種子層409，如圖8L所示。最後，移除該載片405，即完成如同圖1之矽穿孔基板結構100，如圖8M所示。上述實施範例之製作流程亦可用以製作其他態樣的矽穿孔基板結構，並不限於上凹陷下突出的態樣。
唯以上所述者，包含：特徵、結構、及其它類似的效果，僅為本發明之較佳實施例，當不能以之限制本發明的範圍。上述各實施例所展示的特徵、結構、及其它類似的效果，亦可為該領域所屬的技藝人士在依本發明申請專利範圍進行均等變化及修飾，仍將不失本發明之要義所在，亦不脫離本發明之精神和範圍，故都應視為本發明的進一步實施狀況。此外，上述各實施例所描述者只能算是實施 範例，並不能因此限制本發明的範圍。例如，各實施例所使用的元件或單元，可為該領域所屬的技藝人士進行修改及實現，仍將不失本發明之要義。
100‧‧‧矽穿孔基板結構
110‧‧‧基板
111‧‧‧第一表面
112‧‧‧第二表面
114‧‧‧絕緣層
120‧‧‧導體部
121‧‧‧第一端
122‧‧‧第二端
123‧‧‧延伸部
125‧‧‧導體柱
127‧‧‧凹陷部
128‧‧‧突出部
130‧‧‧矽穿孔
131‧‧‧側面
210‧‧‧範例1之基板組合結構
220‧‧‧範例2之基板組合結構
230‧‧‧範例3之基板組合結構
401/408‧‧‧阻障層
402/409‧‧‧種子層
403/407/410‧‧‧光阻層
404/411‧‧‧銅膜
405‧‧‧載片
406‧‧‧黏著劑
圖1根據本發明第一實施例之矽穿孔基板結構的立體結構示意圖。
圖2A根據第一實施例之另一矽穿孔基板結構示意圖-上下皆為突出部的態樣。
圖2B根據第一實施例之另一矽穿孔基板結構示意圖-上下皆凹陷部的態樣。
圖3A根據本發明第二實施例之基板組合結構的結構圖(範例1)。
圖3B根據第二實施例之基板組合結構的示意圖(範例2)。
圖3C根據第二實施例之基板組合結構的示意圖(範例3)。
圖4A根據第二實施例之基板組合結構的示意圖(範例4之上下表面及其矽穿孔的側面皆具有絕緣層)。
圖4B根據第二實施例之基板組合結構的示意圖(範例4之只有矽穿孔的側面具有絕緣層)。
圖5A根據第二實施例之基板組合結構的示意圖(範例5之上下表面及其矽穿孔的側面皆具有絕緣層)。
圖5B根據第二實施例之基板組合結構的示意圖(範例5之 只有矽穿孔的側面具有絕緣層)。
圖6A根據第二實施例之基板組合結構的示意圖(範例6之上下表面及其矽穿孔的側面皆具有絕緣層)。
圖6B根據第二實施例之基板組合結構的示意圖(範例6之只有矽穿孔的側面具有絕緣層)。
圖7A根據第二實施例之基板組合結構的示意圖(範例7之上下表面及其矽穿孔的側面皆具有絕緣層)。
圖7B根據第二實施例之基板組合結構的示意圖(範例7之只有矽穿孔的側面具有絕緣層)。
圖8A~8M矽穿孔基板結構的實施範例之製程步驟示意圖。
100‧‧‧矽穿孔基板結構
110‧‧‧基板
111‧‧‧第一表面
112‧‧‧第二表面
114‧‧‧絕緣層
120‧‧‧導體部
121‧‧‧第一端
122‧‧‧第二端
123‧‧‧延伸部
125‧‧‧導體柱
127‧‧‧凹陷部
128‧‧‧突出部
130‧‧‧矽穿孔
131‧‧‧側面

Claims (23)

  1. 一種矽穿孔基板結構，其包括：一基板，其具有一第一表面、一第二表面、及一矽穿孔，該矽穿孔由該第一表面貫穿該基板而通至該第二表面；及一導體部，其充填該矽穿孔，該導體部包括：一導體柱，具有一第一端及一第二端，其基面分別對應於該第一表面及該第二表面；其中，該導體部更包括：一第一突出部，其形成於該第一端的基面外；以及一形成於該第二端的基面外之第二突出部或一形成於該第二端的基面內之凹陷部，其中該第一突出部的面積小於或等於該凹陷部，且該第一突出部的高度大於或等於該凹陷部。
  2. 如申請專利範圍第1項所述之矽穿孔基板結構，其中該導體部更包括一第一延伸部，形成於該導體柱鄰近該第一端的側面上。
  3. 如申請專利範圍第2項所述之矽穿孔基板結構，其中該第一延伸部圍繞該導體柱。
  4. 如申請專利範圍第2項所述之矽穿孔基板結構，其中該導體部更包括一第二延伸部，形成於該導體柱鄰近該第二端的側面上。
  5. 如申請專利範圍第4項所述之矽穿孔基板結構，其中該第二延伸部圍繞該導體柱。
  6. 如申請專利範圍第1項所述之矽穿孔基板結構，其中該 基板係選自：一晶粒、一晶片、一晶圓、一中介層、或上述中之至少二者。
  7. 如申請專利範圍第1項所述之矽穿孔基板結構，其中該基板更包括一第一絕緣層，其形成於該矽穿孔的側面上。
  8. 如申請專利範圍第7項所述之矽穿孔基板結構，其中該第一絕緣層更包括：一凹陷區域，其形成於該第一端基面上，該凹陷區域的面積小於或等於該導體部的截面積。
  9. 如申請專利範圍第8項所述之矽穿孔基板結構，其中該第一絕緣層更包括：一凹陷區域，其形成於該第二端基面上，該凹陷區域的面積小於或等於該導體部的截面積。
  10. 如申請專利範圍第7項所述之矽穿孔基板結構，其中該基板更包括一第二絕緣層，其形成於該第一表面上。
  11. 如申請專利範圍第10項所述之矽穿孔基板結構，其中該基板更包括一第三絕緣層，其形成於該第二表面上。
  12. 一種基板堆疊的組合結構，其包括複數個相互堆疊的矽穿孔基板結構，各個該矽穿孔基板結構包括：一基板，其具有一第一表面、一第二表面、及一矽穿孔，該矽穿孔由該第一表面貫穿該基板而通至該第二表面；及一導體部，其充填該矽穿孔，該導體部包括：一導體柱，具有一第一端及一第二端，其基面分別對應於該第一表面及該第二表面；其中，該導體部更包括：一第一突出部，其形成於該第一端的基面外；以及一形成於該第二端的基面外之第二突出部或一形成 於該第二端的基面內之凹陷部，其中該第一突出部的面積小於或等於該凹陷部，且該第一突出部的高度大於或等於該凹陷部。
  13. 如申請專利範圍第12項所述之基板堆疊的組合結構，其中該導體部更包括一第一延伸部，形成於該導體柱鄰近該第一端的側面上。
  14. 如申請專利範圍第13項所述之基板堆疊的組合結構，其中該第一延伸部圍繞該導體柱。
  15. 如申請專利範圍第13項所述之基板堆疊的組合結構，其中該導體部更包括一第二延伸部，形成於該導體柱鄰近該第二端的側面上。
  16. 如申請專利範圍第15項所述之基板堆疊的組合結構，其中該第二延伸部圍繞該導體柱。
  17. 如申請專利範圍第12項所述之基板堆疊的組合結構，其中該基板係選自：一晶粒、一晶片、一晶圓、一中介層、或上述中之至少二者。
  18. 如申請專利範圍第12項所述之基板堆疊的組合結構，其中該基板更包括一第一絕緣層，其形成於該矽穿孔的側面上。
  19. 如申請專利範圍第18項所述之基板堆疊的組合結構，其中該第一絕緣層更包括：一凹陷區域，其形成於該第一端基面上，該凹陷區域的面積小於或等於該導體部的截面積。
  20. 如申請專利範圍第19項所述之基板堆疊的組合結構，其中該第一絕緣層更包括：一凹陷區域，其形成於該第 二端基面上，該凹陷區域的面積小於或等於該導體部的截面積。
  21. 如申請專利範圍第18項所述之基板堆疊的組合結構，其中該基板更包括一第二絕緣層，其形成於該第一表面上。
  22. 如申請專利範圍第21項所述之基板堆疊的組合結構，其中該基板更包括一第三絕緣層，其形成於該第二表面上。
  23. 如申請專利範圍第12項所述之基板堆疊的組合結構，其中該等矽穿孔基板結構的矽穿孔互相對應。
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US13/845,869 US20130214390A1 (en) 2010-11-26 2013-03-18 Tsv substrate structure and the stacked assembly thereof
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