TWI485831B - 具有多層配線構造之半導體裝置及其製造方法 - Google Patents

具有多層配線構造之半導體裝置及其製造方法 Download PDF

Info

Publication number
TWI485831B
TWI485831B TW100133543A TW100133543A TWI485831B TW I485831 B TWI485831 B TW I485831B TW 100133543 A TW100133543 A TW 100133543A TW 100133543 A TW100133543 A TW 100133543A TW I485831 B TWI485831 B TW I485831B
Authority
TW
Taiwan
Prior art keywords
insulating layer
electronic component
semiconductor device
semiconductor wafer
layer
Prior art date
Application number
TW100133543A
Other languages
English (en)
Chinese (zh)
Other versions
TW201218350A (en
Inventor
新井一能
Original Assignee
兆探晶股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 兆探晶股份有限公司 filed Critical 兆探晶股份有限公司
Publication of TW201218350A publication Critical patent/TW201218350A/zh
Application granted granted Critical
Publication of TWI485831B publication Critical patent/TWI485831B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/08—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
    • H10W70/09—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/129—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed forming a chip-scale package [CSP]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/242—Dispositions, e.g. layouts relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/22—Configurations of stacked chips the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/291—Configurations of stacked chips characterised by containers, encapsulations, or other housings for the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
TW100133543A 2010-09-30 2011-09-19 具有多層配線構造之半導體裝置及其製造方法 TWI485831B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010220481A JP5758605B2 (ja) 2010-09-30 2010-09-30 半導体装置及びその製造方法

Publications (2)

Publication Number Publication Date
TW201218350A TW201218350A (en) 2012-05-01
TWI485831B true TWI485831B (zh) 2015-05-21

Family

ID=45889091

Family Applications (1)

Application Number Title Priority Date Filing Date
TW100133543A TWI485831B (zh) 2010-09-30 2011-09-19 具有多層配線構造之半導體裝置及其製造方法

Country Status (5)

Country Link
US (1) US9252099B2 (https=)
JP (1) JP5758605B2 (https=)
KR (1) KR101256321B1 (https=)
CN (1) CN102446888A (https=)
TW (1) TWI485831B (https=)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013047848A1 (ja) * 2011-09-30 2013-04-04 京セラ株式会社 配線基板、部品内蔵基板および実装構造体
US9613939B2 (en) 2013-01-10 2017-04-04 Heptagon Micro Optics Pte. Ltd. Opto-electronic modules including features to help reduce stray light and/or optical cross-talk
US9275925B2 (en) 2013-03-12 2016-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. System and method for an improved interconnect structure
CN103327741B (zh) * 2013-07-04 2016-03-02 江俊逢 一种基于3d打印的封装基板及其制造方法
CN108780791B (zh) * 2016-03-01 2023-01-10 索尼公司 半导体装置、电子模块、电子设备和用于生产半导体装置的方法
US20180261665A1 (en) * 2016-12-28 2018-09-13 Noda Screen Co., Ltd. Thin film capacitor and semiconductor device
US11227821B2 (en) 2020-04-21 2022-01-18 Toyota Motor Engineering & Manufacturing North America, Inc. Chip-on-chip power card with embedded thermal conductor

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006310419A (ja) * 2005-04-27 2006-11-09 Casio Comput Co Ltd 半導体装置の製造方法
JP2008047734A (ja) * 2006-08-17 2008-02-28 Sony Corp 半導体装置及び半導体装置の製造方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3651346B2 (ja) * 2000-03-06 2005-05-25 カシオ計算機株式会社 半導体装置およびその製造方法
JP2002299496A (ja) * 2001-03-30 2002-10-11 Fujitsu Ltd 半導体装置及びその製造方法
JP2004140037A (ja) * 2002-10-15 2004-05-13 Oki Electric Ind Co Ltd 半導体装置、及びその製造方法
US8704359B2 (en) * 2003-04-01 2014-04-22 Ge Embedded Electronics Oy Method for manufacturing an electronic module and an electronic module
JP4161909B2 (ja) * 2004-01-16 2008-10-08 ソニー株式会社 半導体装置の製造方法
JP4654598B2 (ja) * 2004-04-30 2011-03-23 ソニー株式会社 半導体装置およびその製造方法
JP4431747B2 (ja) 2004-10-22 2010-03-17 富士通株式会社 半導体装置の製造方法
JP4851794B2 (ja) 2006-01-10 2012-01-11 カシオ計算機株式会社 半導体装置
JP4844287B2 (ja) * 2006-04-26 2011-12-28 ソニー株式会社 半導体装置及びその製造方法
JP4874005B2 (ja) 2006-06-09 2012-02-08 富士通セミコンダクター株式会社 半導体装置、その製造方法及びその実装方法
JP4869991B2 (ja) * 2007-03-14 2012-02-08 富士通株式会社 キャパシタ内蔵ウェハレベルパッケージ及びその製造方法
JP2009289863A (ja) * 2008-05-28 2009-12-10 Casio Comput Co Ltd 半導体装置の製造方法
JP2010232230A (ja) 2009-03-25 2010-10-14 Casio Computer Co Ltd 半導体装置およびその製造方法
TWI521670B (zh) * 2009-05-14 2016-02-11 高通公司 系統級封裝

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006310419A (ja) * 2005-04-27 2006-11-09 Casio Comput Co Ltd 半導体装置の製造方法
JP2008047734A (ja) * 2006-08-17 2008-02-28 Sony Corp 半導体装置及び半導体装置の製造方法

Also Published As

Publication number Publication date
US9252099B2 (en) 2016-02-02
KR20120033977A (ko) 2012-04-09
JP5758605B2 (ja) 2015-08-05
US20120080788A1 (en) 2012-04-05
KR101256321B1 (ko) 2013-04-18
JP2012079725A (ja) 2012-04-19
CN102446888A (zh) 2012-05-09
TW201218350A (en) 2012-05-01

Similar Documents

Publication Publication Date Title
US11257747B2 (en) Semiconductor package with conductive via in encapsulation connecting to conductive element
TWI495064B (zh) 晶圓級半導體封裝件及其製造方法
TWI485831B (zh) 具有多層配線構造之半導體裝置及其製造方法
US12040287B2 (en) Semiconductor device package and method for manufacturing the same
US20130037929A1 (en) Stackable wafer level packages and related methods
CN107644848A (zh) 封装结构及其制造方法
US9903024B2 (en) Substrate having electrical interconnection structures and fabrication method thereof
US20200343184A1 (en) Semiconductor package and manufacturing method thereof
JP2005327984A (ja) 電子部品及び電子部品実装構造の製造方法
TW201742203A (zh) 整合扇出型封裝及其製造方法
US12125832B2 (en) Semiconductor device and method of manufacturing a semiconductor device
KR102424641B1 (ko) 반도체 패키지 및 그 형성 방법
US12002768B2 (en) Semiconductor package and manufacturing method thereof
US20200111747A1 (en) Semiconductor package, method of fabricating semiconductor package, and method of fabricating redistribution structure
JP4403407B2 (ja) 半導体装置およびその製造方法
US11848233B2 (en) Semiconductor package and manufacturing method thereof
KR20200139088A (ko) 반도체 디바이스 및 관련 방법
JP2010087021A (ja) 混成回路装置及びその製造方法並びに混成回路積層体
JP7048153B2 (ja) 半導体装置及び半導体装置の製造方法
TWI851040B (zh) 封裝、封裝結構、與積體電路封裝的形成方法
JP5245209B2 (ja) 半導体装置及びその製造方法
JP2011108733A (ja) 半導体装置及びその製造方法
US12412846B2 (en) Semiconductor package and methods of fabricating a semiconductor package
KR20120028008A (ko) 전자부품 내장형 인쇄회로기판 및 이의 제조 방법
JP2006216768A (ja) 半導体装置およびその製造方法

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees