TWI485831B - 具有多層配線構造之半導體裝置及其製造方法 - Google Patents

具有多層配線構造之半導體裝置及其製造方法 Download PDF

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TWI485831B
TWI485831B TW100133543A TW100133543A TWI485831B TW I485831 B TWI485831 B TW I485831B TW 100133543 A TW100133543 A TW 100133543A TW 100133543 A TW100133543 A TW 100133543A TW I485831 B TWI485831 B TW I485831B
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insulating layer
electronic component
semiconductor device
semiconductor wafer
layer
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TW201218350A (en
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Kazuyoshi Arai
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Tera Probe Inc
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Description

具有多層配線構造之半導體裝置及其製造方法
本發明係關於一種具有多層配線構造的半導體裝置及其製造方法。
特開2008-047734號公報上記載了一種埋設有複數個半導體晶片的SIP(System In Package;系統級封裝)型的半導體封裝(半導體裝置)。如專利文獻1上所記載,在未形成電路的基板(1)上層積兩層的絕緣層(6、7),於各絕緣層(6、7)上形有配線(9、13)圖案,裸晶片(5)埋設於下層的絕緣層(6),且上層的絕緣層(6、7)上層積厚的緩衝層(17),用氧化矽膜(16d)保護的別的裸晶片(16)埋設於緩衝層(17)中。
在特開2008-047734號公報上所記載的技術方面,由於在層積於基板(1)上的絕緣層(6)或緩衝層(17)中埋設有晶片(5、16),所以導致半導體封裝變厚。
此外,基板(1)為切開晶圓而成者。由於將晶片(5)搭載於晶圓上後,最後切斷晶圓,所以被切開的基板(1)的尺寸會比晶片(5)的尺寸更大。因此,導致半導體封裝的尺寸也大型化。
於是,本發明欲解決之課題為謀求半導體封裝等的半導體裝置的薄型化及小型化。
依據本發明之一態樣,其特徵在於具備:半導體晶片、層積於前述半導體晶片上的多層配線構造、及埋設於前述多層配線構造中的電子零件。
此外,依據本發明之其他態樣,其特徵在於:係在半導體晶圓的上方層積多層配線構造,並且在前述多層配線構造中嵌入電子零件,將前述半導體晶圓及前述多層配線構造切成晶片尺寸的方法。
以下,就用以實施本發明的形態,使用圖面進行說明。其中,對於以下所述的實施形態,雖然為了實施本發明而附上技術上較佳的各種限定,但並不是將本發明的範圍限定於以下的實施形態及圖示例。
圖1為半導體裝置1的斜視圖。圖2為半導體裝置1的剖面圖。
如圖1、圖2所示,半導體裝置1為SIP(System In Package;系統級封裝),具備半導體晶片10、多層配線構造30及電子零件60、80等。多層配線構造30層積於半導體晶片10表面的面10a上,電子零件60、80埋設於多層配線構造30中。
首先,參閱圖2、圖3,就半導體晶片10進行詳細說明。圖3為顯示半導體晶片10部份斷裂的狀態的斜視圖。在圖3中,顯示在半導體晶片10上未層積有多層配線構造30的狀態。
半導體晶片10乃封裝成晶片尺寸者,係所謂的CSP(Chip Size Package;晶片尺寸封裝)。特別是此半導體晶片10為在用樹脂密封單片化前的半導體晶圓的表面後,將其單片化成晶片尺寸而成者。即,在半導體晶片10是在CSP中的特別是WLP(Wafer Level Package;晶圓級封裝)。
半導體晶片10具備半導體基板11、鈍化膜13、絕緣膜14、密封層16、內部配線20及外部端子26等。
半導體基板11係由矽之類的半導體材料等構成。在半導體基板11表面的表層形成有積體電路。在半導體基板11表面的面上形成有複數個內部端子12。內部端子12為形成於半導體基板11表層的積體電路的配線的一部份,或為各種電氣元件(例如二極體、電晶體、電阻、電容器等)的電極。
半導體基板11表面的面被鈍化膜13所覆蓋。鈍化膜13含有氧化矽或氮化矽。鈍化膜13被絕緣膜14所覆蓋。絕緣膜14含有環氧系樹脂、聚醯亞胺系樹脂及其他樹脂。例如,在於絕緣膜14方面,可使用聚醯亞胺(PI)、聚苯噁唑(PBO)、環氧系、苯酚系、矽系等的塑膠材料或此等材料的複合材料等。
在鈍化膜13及絕緣膜14之中與內部端子12重疊的位置形成有開口15。內部端子12的一部份或全體位於開口15內,內部端子12的一部份或全體未被鈍化膜13及絕緣膜14所覆蓋。再者,也可以未形成絕緣膜14。
內部配線20形成於絕緣膜14上(無絕緣膜14時是在鈍化膜13上)。內部配線20為基底21與導體層22的積層體,基底21形成於絕緣膜14上(無絕緣膜14時,是在鈍化膜13上),導體層22形成於基底21上。基底21是由導體所構成。例如,基底21為銅(Cu)的薄膜、鈦(Ti)的薄膜、鈦上層積銅的薄膜及其他金屬薄膜。導體層22係將成長於種子層上的鍍覆圖案化而成者。導體層22是由銅及其他金屬構成。俯視時的導體層22的形狀與基底21的形狀大致相同。導體層22比基底21更厚。再者,內部配線20也可以不是導體的積層體。例如,內部配線20可以是導體的單層,也可以是層積有更多的導體層者。
內部配線20連接於內部端子12。具體而言,內部配線20橫過開口15上,內部配線20的基底21的一部份層積於內部端子12上。內部配線20的數量可以比內部端子12的數量更多,也可以更少,亦可相等。連接於1條內部配線20的內部端子12的數量為1或2個以上。較佳為每1條內部配線20連接1個內部端子12。
內部配線20的一部份成為連接盤23。在連接盤23上形成有外部端子26,內部配線20連接於外部端子26。因此,外部端子26利用內部配線20與內部端子12導通。連接於1條內部配線20的外部端子26的數量為1或2個以上。較佳為,每1條內部配線20連接1個外部端子26。此外,關於1個外部端子26,係以1個內部端子12是利用內部配線20導通更好。
外部端子26為設置成突起狀的柱狀電極。外部端子26由銅及其他金屬構成。外部端子26的高度(厚度)比導體層22的厚度更大。再者,雖然在圖3中,外部端子26排列成縱6列×橫6列的格子狀,但外部端子26的排列及數量未受限於此。
遮光性的密封層16形成於絕緣膜14上,內部配線20被密封層16所覆蓋。雖然外部端子26的頭頂面未被密封層16所覆蓋,但外部端子26的周面卻被密封層16所覆蓋而受到保護。密封層16的表面設置成與外部端子26的頭頂面齊平面、或在比外部端子26的頭頂面稍高的位置。
密封層16含有環氧系樹脂、聚醯亞胺系樹脂及其他絕緣性樹脂,最好是由絕緣性樹脂(環氧系樹脂、聚醯亞胺系樹脂等)中摻合有填充物(例如玻璃填充物)的纖維強化樹脂所構成。
再者,半導體晶片10可以是LGA(Land Grid Array;地柵陣列)方式的封裝。亦即,可以是作為端子的連接盤在半導體晶片10表面的面10a上排列成格子狀。
茲參閱圖1、圖2,就多層配線構造30進行說明。
多層配線構造30具有配線圖案31~34及絕緣層41~44。絕緣層41、絕緣層42、絕緣層43及絕緣層44從半導體晶片10起依絕緣層41、絕緣層42、絕緣層43、絕緣層44的順序層積於半導體晶片10表面的面10a上。配線圖案31位於絕緣層41與絕緣層42之間,配線圖案32位於絕緣層42與絕緣層43之間,配線圖案33位於絕緣層43與絕緣層44之間,配線圖案34形成於絕緣層44上。配線圖案31與配線圖案32被絕緣層42所隔開,配線圖案32與配線圖案33被絕緣層43所隔開,配線圖案33與配線圖案34被絕緣層44所隔開。
絕緣層41~44的邊緣與半導體晶片10的側面(周面)10c一致,多層配線構造30的側面(周面)30c與半導體晶片10的側面10c一致。
在絕緣層44上開有複數個通孔,在通孔內嵌入有層間連接導體54,層間連接導體54貫穿絕緣層44,配線圖案34與配線圖案33藉由層間連接導體54而導通。同樣地,配線圖案33與配線圖案32藉由貫穿絕緣層43的層間連接導體53而導通,配線圖案32與配線圖案31藉由貫穿絕緣層42的層間連接導體52而導通。
層間連接導體54與配線圖案34一體形成,層間連接導體53與配線圖案33一體形成,層間連接導體54與配線圖案32一體形成。此等導體與圖案也可以分開形成而互相接觸。
此外,在絕緣層41上開設有到達外部端子26的複數個通孔,在通孔內嵌入有層間連接導體51,層間連接導體51貫穿絕緣層41,配線圖案31與外部端子26藉由層間連接導體51而導通。
配線圖案31、32、33、34及層間連接導體51、52、53、54係由銅及其他金屬所構成。絕緣層41、42、43、44含有環氧系樹脂、聚醯亞胺系樹脂及其他絕緣性樹脂,較佳為,是由玻璃纖維強化環氧樹脂、玻璃布基材環氧樹脂、碳纖維強化環氧樹脂、碳布基材環氧樹脂,即由玻璃纖維強化聚醯亞胺樹脂、玻璃布基材聚醯亞胺樹脂、碳纖維強化聚醯亞胺樹脂、碳布基材聚醯亞胺樹脂及其他纖維強化樹脂等所構成。再者,雖然在圖2中,多層配線構造30具有4層的絕緣層41、42、43、44及4層的配線圖案31、32、33、34,但多層配線構造30的絕緣層及配線圖案的層數為2層以上即可。
在如以上的多層配線構造30中埋設有電子零件60、80。更具體而言,係電子零件60、80埋設於絕緣層44中。電子零件60為半導體晶片。電子零件60可以是裸晶片,也可以是已封裝化的半導體晶片。在電子零件60是已封裝化的半導體晶片的情況,不追究電子零件60的封裝方式。
在電子零件60是CSP中的特別是WLP的情況,電子零件60係建構成如圖4所示。圖4為顯示電子零件60一部份斷裂的狀態的斜視圖。如圖4所示,電子零件60具備半導體基板61、鈍化膜63、絕緣膜64、密封層66、內部配線70及外部端子76等。由於電子零件60與半導體晶片10只是外部端子76的數量、內部配線70的形狀及位置、形成於半導體基板61上的積體電路等不同,並且電子零件60與半導體晶片10同樣是WLP,所以對於電子零件60的詳細說明省略。電子零件60的尺寸比半導體晶片10的尺寸更小。再者,雖然在圖4中,外部端子76排列成縱3列×橫3列的格子狀,但外部端子76的排列及數量未受限於此。
如圖2所示,電子零件60被黏晶(die bonding)於絕緣層43上。具體而言,由導體構成的基底35形成於絕緣層43上,在電子零件60背面的面60b與基底35之間夾有黏接劑69,黏接劑69黏附於電子零件60背面的面60b與基底35上。基底35係連同配線圖案33一起被圖案化者。基底35和配線圖案33互相疏離,基底35和配線圖案33不導通。再者,也可以沒有基底35,而黏接劑69直接黏附於絕緣層43上。
絕緣層44係成膜於絕緣層43上,以覆蓋電子零件60全體,電子零件60埋設於絕緣層44中。
如圖4所示,在電子零件60背面的面60b上未形成端子,外部端子76的頭頂面在表面的面60a露出。因此,外部端子76未連接於配線圖案33。另一方面,如圖2所示,在絕緣層44上開設有複數個通孔,通孔內嵌入有層間連接導體55,層間連接導體55貫穿絕緣層44,配線圖案34與外部端子76藉由層間連接導體55而導通。
再者,也可以在電子零件60表面的面60a是朝向絕緣層43的狀態下,將電子零件60利用倒裝晶片(flip chip)方式等表面安裝於絕緣層43上。在此情況,沒有基底35,配線圖案33被圖案化成到達電子零件60的下方,外部端子76係藉由例如焊錫、導電糊、導電片、各向異性導電糊或各向異性導電梯台(pace)而與配線圖案33導通。由於外部端子76與配線圖案33導通,所以沒有層間連接導體55,而供層間連接導體55嵌入的通孔亦未開設在絕緣層44上。
電子零件80為主動零件(例如二極體、電晶體)或被動零件(例如電阻器、電容器)。此外,電子零件80為晶片電阻器、晶片電容器、晶片二極體、晶片電晶體及其他表面安裝型晶片零件。在電子零件80表面的面80a與背面的面80b上分別設有端子。在電子零件80背面的面80b是朝向絕緣層43的狀態下,電子零件80被黏晶於配線圖案33上,設於背面的面80b的端子與配線圖案33導通。
絕緣層44成膜於絕緣層43上,以覆蓋電子零件80全體,電子零件80埋設於絕緣層44中。在絕緣層44上開設有通孔,層間連接導體56嵌入通孔內,層間連接導體56貫穿絕緣層44,設於電子零件80表面的面80a上的端子與配線圖案34係藉由層間連接導體56而導通。
絕緣層44及配線圖案34為頂塗層90所覆蓋。在頂塗層90上形成有複數個開口,在開口內形成有焊錫凸塊92,焊錫凸塊92固定在配線圖案34上。雖然如圖1所示,焊錫凸塊92排列成縱5列×橫5列的格子狀,但焊錫凸塊92的排列及數量未受此所限。再者,也可以沒有焊錫凸塊92。
如圖2所示,由於電子零件60與電子零件80埋設於相同的絕緣層44中,所以只要加厚絕緣層44即可解決,而不加厚絕緣層41、42、43也可以。因此,可謀求半導體裝置1的薄型化。再者,埋設電子零件60的絕緣層與埋設電子零件80的絕緣層也可以不同。此外,電子零件60、80亦可不埋設絕緣層44,而是以埋設於絕緣層42或絕緣層43中。即使是多層配線構造30的絕緣層及配線圖案的層數為4層以外的情況,電子零件60、80也埋設於最下層的絕緣層以外的絕緣層中即可。
雖然埋設於多層配線構造30中的電子零件的數量為2個,但可以為1個,也可以為3個以上。電子零件的數量為2個以上的情況,全部的電子零件宜埋設於相同的絕緣層中。這是因為如上述,要謀求半導體裝置1的薄型化之緣故。
此半導體裝置1係表面安裝於印刷基板上而作使用。具體而言,若將半導體裝置1表面的面1a,即頂塗層90的表面朝向印刷基板,並使焊錫凸塊92接觸印刷基板的端子而將半導體裝置1載置於印刷基板上,而進行廻焊(reflow)焊錫凸塊92時,則可將半導體裝置1表面安裝於印刷基板上。
也可以將半導體裝置1用作電路基板。將半導體裝置1用作電路基板的情況,將電子零件表面安裝在頂塗層90,將該電子零件的端子藉由焊錫凸塊92而接合於配線圖案34。
再者,半導體裝置1的用途並不限於表面安裝於印刷基板上的電子零件、或表面安裝電子零件的電路基板。
如以上說明,由於半導體晶片10並不是搭載於尺寸比其更大的基板上,並且電子零件60、80埋設於層積於該半導體晶片10上的多層配線構造30中,所以可使半導體裝置1成為晶片尺寸(半導體晶片10的尺寸)。因此,可將半導體裝置1小型化。此外,由於多層配線構造30層積於半導體晶片10上,而不是層積於成為基底的基板上,所以僅該成為基底的基板的部份就可將半導體裝置1小型化。
接著,就半導體裝置1的製造方法進行說明。
當製造半導體裝置1時,使用進行單片化之前的半導體晶圓11A(圖示於圖5)。如圖5所示,半導體晶圓11A係藉由作為分割預定線的格子狀的切割道(dicing street)(境界線)11B而區分為複數個晶片區域11C。此等晶片區域11C排列成矩陣狀。在半導體晶圓11A表面的表層,積體電路形成於各晶片區域11C上。在半導體晶圓11A表面的面上形成有複數個內部端子12。鈍化膜13形成於半導體晶圓11A表面的面上。在鈍化膜13上形成有開口15,內部端子12在開口15內露出。半導體(例如矽)在半導體晶圓11A背面的面上露出。
如圖6所示,將絕緣膜14圖案化於鈍化膜13上後,利用無電電鍍法或氣相成長法(例如濺鍍法)或者此等方法的組合,在絕緣膜14上全體形成種子層21A的膜。種子層21A也成長於開口15的內壁面或內部端子12上。在將絕緣膜14圖案化時,將絕緣膜14區分為各晶片區域11C,並將通到內部端子12的開口15形成於絕緣膜14上。種子層21A為銅(Cu)的薄膜、鈦(Ti)的薄膜、將銅層積於鈦上的薄膜及其他的金屬薄膜。再者,也可以不形成絕緣膜14,而在鈍化膜13上形成種子層21A。
其次,如圖7所示,將導體層22圖案化。具體而言,將光阻劑等的光罩20B設置於種子層21A上,在將種子層21A用該光罩20B作部份覆蓋的狀態下,以種子層21A為電極而進行電鍍。在光罩20B上形成有符合要形成的導體層22的位置、形狀的狹縫,藉由電鍍使導體層22成長於種子層21A上且光罩20B的狹縫內。使導體層22成長得比種子層21A更厚。再者,若是光罩20B為光阻劑(例如乾膜光阻劑、溼式光阻劑)的情況,則藉由用曝光、顯影方式在光罩20B上形成狹縫。導體層22形成後,去除光罩20B。
其次,如圖8所示,將外部端子26圖案化。具體而言,將厚膜的光罩(例如乾膜光阻劑)30B設置於種子層21A及導體層22上,在將種子層21A及導體層22用光罩30B部份覆蓋的狀態下,以種子層21A及導體層22為電極而進行電鍍。在光罩30B上形成有符合要形成的外部端子26的位置、形狀的開口。藉由電鍍使外部端子26成長於開口內且導體層22上。再者,若是光罩30B為乾膜光阻劑、溼式光阻劑的情況,則藉由曝光、顯影將開口形成在光罩30B上。
外部端子26形成後,去除光罩30B。
其次,藉由用蝕刻去除種子層21A之中未與導體層22重疊的部份,而將種子層21A形狀加工成基底21。此時,雖然導體層22及外部端子26的表面一部份被蝕刻,但因導體層22及外部端子26相較於種子層21A仍相當地厚,所以導體層22及外部端子26會殘留。
其次,如圖9所示,藉由印刷法、液滴噴出法(噴墨法)、旋轉塗布法、滴下法及其他塗布法將密封層16形成於絕緣膜14(無絕緣膜14時,形成在鈍化膜13)上。當密封層16形成時,藉由密封層16覆蓋導體層22及外部端子26。再者,也可以藉由將半固化片(prepreg)貼附於絕緣膜14上,並使該半固化片硬化,而從半固化片形成密封層16,以取代塗布法。
其次,如圖10所示,研磨密封層16的表面,使外部端子26的頭頂面露出。
藉由使用圖5~圖10說明的步驟,製造進行單片化前的狀態之半導體晶片10。電子零件60為WLP的情況,要製作電子零件60時,在經過與使用圖5~圖10說明的步驟同樣的步驟後,進行切割處理等的單片化處理。藉此,可從一片晶圓製作複數個電子零件60。
外部端子26露出後,如圖11所示,藉由將半固化片熱壓接合於密封層16及外部端子26,從該半固化片形成絕緣層41。就半固化片而言,宜使用玻璃纖維強化環氧樹脂、玻璃布基材環氧樹脂、碳纖維強化環氧樹脂、碳布基材環氧樹脂,即使用使玻璃纖維強化聚醯亞胺樹脂、玻璃布基材聚醯亞胺樹脂、碳纖維強化聚醯亞胺樹脂、碳布基材聚醯亞胺樹脂及其他纖維強化樹脂半硬化而成者。再者,也可以用印刷法、液滴噴出法(噴墨法)、旋塗法、滴下法及其他塗布法形成絕緣層41的膜。
其次,如圖12所示,在絕緣層41上形成複數個通孔41a。通孔41a的形成處為與外部端子26重疊的位置,並使通孔41a貫穿到外部端子26。通孔41a的形成方法可以是將雷射光照射於絕緣層41的方法,也可以是以在絕緣層41上設置有光罩(例如金屬光罩、光阻劑、乾膜光阻劑)的狀態蝕刻絕緣層41的方法。
其次,如圖13所示,藉由電鍍法使層間連接導體51在通孔41a內成長,並且使導體膜31A在絕緣層41上成長。再者,層間連接導體51的形成法不限於電鍍法,也可以是將導電性構件(例如導電糊)嵌入通孔41a內的方法。
其次,如圖14所示,藉由以在導體膜31A上設置有光罩(圖示省略)的狀態蝕刻導體膜31A,而去除導體膜31A的一部份。藉此,從導體膜31A製作配線圖案31。配線圖案31形成後,去除光罩。再者,配線圖案31的形成方法不限於如圖13、圖14所示的減法(subtract),也可以是加法(additive)(半加法、全加法及其他加法)。
之後,同樣地依序形成絕緣層42、層間連接導體52、配線圖案32、絕緣層43、層間連接導體53及配線圖案33(參閱圖15)。於配線圖案33形成之際,基底35亦圖案化。再者,也可以不形成基底35。
其次,如圖16所示,將電子零件60黏晶於絕緣層42上,將電子零件80黏晶於配線圖案33上。關於電子零件60,使無端子的面60b向下,利用黏接劑69將該面60b黏接於基底35(無基底35時黏接於絕緣層43)。關於電子零件80,使一面80b向下,將形成於該面80b上的端子利用例如焊錫或導電性黏接劑等接合於配線圖案33。再者,關於電子零件60,也可以使有端子的面60a向下,將電子零件60倒裝晶片安裝於配線圖案33及絕緣層42上。此情況,將形成於該面60a上的端子(例如外部端子76)用焊錫或導電性黏接劑等接合於配線圖案33,以取得端子與配線圖案33的導通。
其次,如圖17所示,將絕緣層44成膜於絕緣層43及配線圖案33上,藉以使用絕緣層44覆蓋電子零件60、80。然後,在絕緣層44上形成複數個通孔後,將層間連接導體54、55、56分別形成於通孔內,並且形成配線圖案34。絕緣層44、層間連接導體54、55、56、配線圖案34的形成法與絕緣層41、層間連接導體51、配線圖案31的形成法同樣。再者,將電子零件60的端子(例如外部端子76)連接於配線圖案33時,不形成層間連接導體55及其所使用的通孔。
其次,如圖18所示,將頂塗層90圖案化後,在形成於頂塗層90上的開口內形成焊錫凸塊92。
其次,如圖19所示,藉由沿著切割道11B將半導體晶圓11A、密封層16、多層配線構造30及頂塗層90切斷成格子狀,而將半導體晶圓11A、密封層16、多層配線構造30及頂塗層90切成晶片尺寸。藉此,完成複數個半導體裝置1。分割半導體晶圓11A後的製品為半導體基板11。
再者,較佳為,在單片化之前,藉由研磨半導體晶圓11A的背面而將半導體晶圓11A薄型化。較佳為,半導體晶圓11A的研磨是在形成密封層16後進行。
如以上說明,由於在半導體晶圓11A的切斷前進行封裝(密封層16的形成)、多層配線構造30的形成、電子零件60、80的嵌入,之後進行切成晶片尺寸,所以可使半導體裝置1的尺寸成為半導體晶片10的尺寸。因此,可將半導體裝置1小型化。此外,由於在半導體晶圓11A上層積多層配線構造30,而不是在不同於形成有電路的半導體晶圓11A的晶圓上層積多層配線構造30,所以不需要與半導體晶圓11A不同的晶圓。因此,可謀求半導體裝置1的薄型化。
[變形例]
再者,可適用本發明的實施形態不限於上述的實施形態,可在不脫離本發明要旨的範圍內適當變更。
例如,也可以建構成圖20所示的半導體裝置101。在圖20所示的半導體裝置101與圖2所示的半導體裝置1之間互相對應的部份上附上同一符號。
如圖20所示,外部端子未形成於半導體晶片10上,而密封層16比圖2所示的情況更薄。形成於絕緣層41上的通孔開設到密封層16,層間連接導體51貫穿絕緣層41及密封層16而連接於內部配線20。
除了以上所說明的以外,於圖20所示的半導體裝置101與圖2所示的半導體裝置1之間互相對應的部份被同樣地設置。
圖20所示的半導體裝置101的製造方法與圖2所示的半導體裝置1的製造方法大致同樣。然而,當製造半導體晶片10時,形成密封層16而不形成外部端子,將層間連接導體51用的通孔藉由雷射光的照射而形成於密封層16上這點是與第1實施形態的情況不同。
1...半導體裝置
1a...半導體裝置1表面的面
10...半導體晶片
10a...半導體晶片10表面的面
10c...半導體晶片10的側面
11...半導體基板
12...內部端子
13...鈍化膜
14...絕緣膜
15...開口
16...密封層
20...內部配線
21、35...基底
22...導體層
23...連接盤
26...外部端子
30...多層配線構造
30c...多層配線構造30的側面(周面)
31~34...配線圖案
41~44...絕緣層
51~56...層間連接導體
60、80...電子零件
60a...電子零件60表面的面
60b...電子零件60背面的面
69...黏接劑
80a...電子零件80表面的面
80b...電子零件80背面的面
90...頂塗層
92...焊錫凸塊
圖1為關於本發明實施形態的半導體裝置的斜視圖。
圖2為關於同一實施形態的半導體裝置的剖面圖。
圖3為顯示關於同一施形態的半導體晶片之部份斷裂的狀態的斜視圖。
圖4為顯示關於同一實施形態的電子零件之部份斷裂的狀態的斜視圖。
圖5為製造關於同一實施形態的半導體裝置的方法的一步驟之剖面圖。
圖6為圖5的步驟後的步驟之剖面圖。
圖7為圖6的步驟後的步驟之剖面圖。
圖8為圖7的步驟後的步驟之剖面圖。
圖9為圖8的步驟後的步驟之剖面圖。
圖10為圖9的步驟後的步驟之剖面圖。
圖11為圖10的步驟後的步驟之剖面圖。
圖12為圖11的步驟後的步驟之剖面圖。
圖13為圖12的步驟後的步驟之剖面圖。
圖14為圖13的步驟後的步驟之剖面圖。
圖15為圖14的步驟後的步驟之剖面圖。
圖16為圖15的步驟後的步驟之剖面圖。
圖17為圖16的步驟後的步驟之剖面圖。
圖18為圖17的步驟後的步驟之剖面圖。
圖19為圖18的步驟後的步驟之剖面圖。
圖20為關於變形例的半導體裝置之剖面圖。
1...半導體裝置
1a...半導體裝置1表面的面
10...半導體晶片
10a...半導體晶片10表面的面
10c...半導體晶片10的側面
11...半導體基板
12...內部端子
13...鈍化膜
14...絕緣膜
15...開口
16...密封層
20...內部配線
21、35...基底
22...導體層
23...連接盤
26...外部端子
30...多層配線構造
30c...多層配線構造30的側面(周面)
31~34...配線圖案
41~44...絕緣層
51~56...層間連接導體
60、80...電子零件
60a...電子零件60表面的面
60b...電子零件60背面的面
69...黏接劑
80a...電子零件80表面的面
80b...電子零件80背面的面
90...頂塗層
92...焊錫凸塊

Claims (17)

  1. 一種半導體裝置,其包含以下:半導體晶片;層積於該半導體晶片上的多層配線構造;及埋設於該多層配線構造中的電子零件,該多層配線構造具有交替層積於該半導體晶片上的複數個絕緣層及複數個配線圖案,該多層配線構造的周面與半導體晶片的周面一致。
  2. 一種半導體裝置,其包含以下:半導體晶片;層積於該半導體晶片上的多層配線構造;及埋設於該多層配線構造中的電子零件,該多層配線構造,在俯視時的該半導體晶片的外緣的內側中,具有交替層積於半導體晶片上的複數個絕緣層及複數個配線圖案,該複數個配線圖案及該電子零件係配置在俯視時的該半導體晶片的外緣的內側。
  3. 如申請專利範圍第1或2項之半導體裝置,其中該半導體晶片已被封裝。
  4. 如申請專利範圍第3項之半導體裝置,其中該半導體晶片具有:半導體基板;及形成於該半導體基板上的內部配線;與為覆蓋該內部配線而形成於該半導體基板上的 密封層;該多層配線構造層積於該密封層上。
  5. 如申請專利範圍第1或2項之半導體裝置,其中該複數個絕緣層係藉由使半固化片(prepreg)硬化所形成的絕緣層。
  6. 如申請專利範圍第1或2項之半導體裝置,其更具備形狀和該電子零件不同的別的電子零件,該別的電子零件係埋設於在該複數個絕緣層之中埋設該電子零件的絕緣層。
  7. 如申請專利範圍第1或2項之半導體裝置,其中該多層配線構造係以貫穿該絕緣層的方式設置在該絕緣層,更具有使該複數個配線圖案導通的層間連接導體,該半導體晶片的端子和該電子零件的端子係透過該配線圖案及該層間連接導體導通。
  8. 如申請專利範圍第1或2項之半導體裝置,其中該電子零件係被動零件的表面安裝型晶片零件。
  9. 如申請專利範圍第1或2項之半導體裝置,其中該電子零件係藉由將半導體晶圓及覆蓋該半導體晶圓的密封層單片化成為晶片尺寸所得到的WLP。
  10. 如申請專利範圍第1或2項之半導體裝置,其中該電子零件係埋設在該複數個絕緣層之中最下層以外者。
  11. 如申請專利範圍第1或2項之半導體裝置,其中該複數個絕緣層之中埋設該電子零件的絕緣層係上面被形成為平坦的絕緣層。
  12. 如申請專利範圍第11項之半導體裝置,其中該複數個配線圖案之中被形成在比該電子零件還上層的配線圖案,係直接形成在該複數個絕緣層之中埋設該電子零件的絕緣層上,且以俯視時從該電子零件的內側起到達外側的方式形成。
  13. 如申請專利範圍第1或2項之半導體裝置,其中該複數個絕緣層之中比埋設該電子零件的絕緣層還下層的絕緣層係上面被形成為平坦的絕緣層,該複數個配線圖案之中被形成在比該電子零件還下層的配線圖案,係以俯視時從該電子零件的內側起到達外側的方式形成,且由該上面被形成為平坦的絕緣層所覆蓋。
  14. 一種半導體裝置之製造方法,其包含以下:第一步驟,係在具有積體電路並且上面具有複數片端子的半導體晶圓的上方,交替層積絕緣層和配線圖案,藉此形成由這些絕緣層和配線圖案所構成的多層配線構造,並且當形成該多層配線構造時在該多層配線構造中嵌入電子零件;及第二步驟,係將該半導體晶圓及該多層配線構造單片化成為晶片尺寸。
  15. 如申請專利範圍第14項之半導體裝置之製造方法,其中該第一步驟包含將該絕緣層的上面平坦化的步驟。
  16. 如申請專利範圍第15項之半導體裝置之製造方法,其中將該絕緣層的上面平坦化的步驟係利用熱壓接 合使該絕緣層的材料硬化,藉此形成該絕緣層。
  17. 如申請專利範圍第14項之半導體裝置之製造方法,其中該第一步驟包含以下步驟:利用熱壓接合使該絕緣層的材料硬化,藉此形成該複數個絕緣層之中埋設該電子零件的絕緣層,該複數個配線圖案之中被形成在比該電子零件還上層的配線圖案,係直接形成在該複數個絕緣層之中埋設該電子零件的絕緣層上,且以俯視時從該電子零件的內側起到達外側的方式形成。
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Families Citing this family (7)

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Publication number Priority date Publication date Assignee Title
WO2013047848A1 (ja) * 2011-09-30 2013-04-04 京セラ株式会社 配線基板、部品内蔵基板および実装構造体
US9613939B2 (en) 2013-01-10 2017-04-04 Heptagon Micro Optics Pte. Ltd. Opto-electronic modules including features to help reduce stray light and/or optical cross-talk
US9275925B2 (en) 2013-03-12 2016-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. System and method for an improved interconnect structure
CN103327741B (zh) * 2013-07-04 2016-03-02 江俊逢 一种基于3d打印的封装基板及其制造方法
DE112017001101T5 (de) 2016-03-01 2018-11-29 Sony Corporation Halbleitervorrichtung, elektronisches Modul, elektronische Einrichtung und Herstellungsverfahren für eine Halbleitervorrichtung
US20180261665A1 (en) * 2016-12-28 2018-09-13 Noda Screen Co., Ltd. Thin film capacitor and semiconductor device
US11227821B2 (en) 2020-04-21 2022-01-18 Toyota Motor Engineering & Manufacturing North America, Inc. Chip-on-chip power card with embedded thermal conductor

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006310419A (ja) * 2005-04-27 2006-11-09 Casio Comput Co Ltd 半導体装置の製造方法
JP2008047734A (ja) * 2006-08-17 2008-02-28 Sony Corp 半導体装置及び半導体装置の製造方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3651346B2 (ja) * 2000-03-06 2005-05-25 カシオ計算機株式会社 半導体装置およびその製造方法
JP2002299496A (ja) * 2001-03-30 2002-10-11 Fujitsu Ltd 半導体装置及びその製造方法
JP2004140037A (ja) * 2002-10-15 2004-05-13 Oki Electric Ind Co Ltd 半導体装置、及びその製造方法
US8704359B2 (en) * 2003-04-01 2014-04-22 Ge Embedded Electronics Oy Method for manufacturing an electronic module and an electronic module
JP4161909B2 (ja) * 2004-01-16 2008-10-08 ソニー株式会社 半導体装置の製造方法
JP4654598B2 (ja) * 2004-04-30 2011-03-23 ソニー株式会社 半導体装置およびその製造方法
JP4431747B2 (ja) 2004-10-22 2010-03-17 富士通株式会社 半導体装置の製造方法
JP4851794B2 (ja) 2006-01-10 2012-01-11 カシオ計算機株式会社 半導体装置
JP4844287B2 (ja) * 2006-04-26 2011-12-28 ソニー株式会社 半導体装置及びその製造方法
JP4874005B2 (ja) 2006-06-09 2012-02-08 富士通セミコンダクター株式会社 半導体装置、その製造方法及びその実装方法
JP4869991B2 (ja) * 2007-03-14 2012-02-08 富士通株式会社 キャパシタ内蔵ウェハレベルパッケージ及びその製造方法
JP2009289863A (ja) * 2008-05-28 2009-12-10 Casio Comput Co Ltd 半導体装置の製造方法
JP2010232230A (ja) 2009-03-25 2010-10-14 Casio Computer Co Ltd 半導体装置およびその製造方法
EP3843133A1 (en) * 2009-05-14 2021-06-30 QUALCOMM Incorporated System-in packages

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006310419A (ja) * 2005-04-27 2006-11-09 Casio Comput Co Ltd 半導体装置の製造方法
JP2008047734A (ja) * 2006-08-17 2008-02-28 Sony Corp 半導体装置及び半導体装置の製造方法

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