CN102446888A - 具有多层布线结构的半导体装置及其制造方法 - Google Patents

具有多层布线结构的半导体装置及其制造方法 Download PDF

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Publication number
CN102446888A
CN102446888A CN2011102794670A CN201110279467A CN102446888A CN 102446888 A CN102446888 A CN 102446888A CN 2011102794670 A CN2011102794670 A CN 2011102794670A CN 201110279467 A CN201110279467 A CN 201110279467A CN 102446888 A CN102446888 A CN 102446888A
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CN
China
Prior art keywords
semiconductor
semiconductor device
wiring structure
multilayer wiring
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN2011102794670A
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English (en)
Chinese (zh)
Inventor
新井一能
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
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Casio Computer Co Ltd
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Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Publication of CN102446888A publication Critical patent/CN102446888A/zh
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/08—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
    • H10W70/09—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/129—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed forming a chip-scale package [CSP]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/242—Dispositions, e.g. layouts relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/22—Configurations of stacked chips the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/291—Configurations of stacked chips characterised by containers, encapsulations, or other housings for the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
CN2011102794670A 2010-09-30 2011-09-20 具有多层布线结构的半导体装置及其制造方法 Pending CN102446888A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2010220481A JP5758605B2 (ja) 2010-09-30 2010-09-30 半導体装置及びその製造方法
JP220481/2010 2010-09-30

Publications (1)

Publication Number Publication Date
CN102446888A true CN102446888A (zh) 2012-05-09

Family

ID=45889091

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2011102794670A Pending CN102446888A (zh) 2010-09-30 2011-09-20 具有多层布线结构的半导体装置及其制造方法

Country Status (5)

Country Link
US (1) US9252099B2 (https=)
JP (1) JP5758605B2 (https=)
KR (1) KR101256321B1 (https=)
CN (1) CN102446888A (https=)
TW (1) TWI485831B (https=)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103327741A (zh) * 2013-07-04 2013-09-25 江俊逢 一种基于3d打印的封装基板及其制造方法
CN108701654A (zh) * 2016-12-28 2018-10-23 野田士克林股份有限公司 薄膜电容器和半导体器件
CN108780791A (zh) * 2016-03-01 2018-11-09 索尼公司 半导体装置、电子模块、电子设备和用于生产半导体装置的方法

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013047848A1 (ja) * 2011-09-30 2013-04-04 京セラ株式会社 配線基板、部品内蔵基板および実装構造体
US9613939B2 (en) 2013-01-10 2017-04-04 Heptagon Micro Optics Pte. Ltd. Opto-electronic modules including features to help reduce stray light and/or optical cross-talk
US9275925B2 (en) 2013-03-12 2016-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. System and method for an improved interconnect structure
US11227821B2 (en) 2020-04-21 2022-01-18 Toyota Motor Engineering & Manufacturing North America, Inc. Chip-on-chip power card with embedded thermal conductor

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001250836A (ja) * 2000-03-06 2001-09-14 Casio Comput Co Ltd 半導体装置およびその製造方法
JP2006310419A (ja) * 2005-04-27 2006-11-09 Casio Comput Co Ltd 半導体装置の製造方法
US20070158857A1 (en) * 2006-01-10 2007-07-12 Casio Computer Co., Ltd. Semiconductor device having a plurality of semiconductor constructs
JP2008047734A (ja) * 2006-08-17 2008-02-28 Sony Corp 半導体装置及び半導体装置の製造方法
CN101847610A (zh) * 2009-03-25 2010-09-29 卡西欧计算机株式会社 半导体装置及其制造方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002299496A (ja) * 2001-03-30 2002-10-11 Fujitsu Ltd 半導体装置及びその製造方法
JP2004140037A (ja) * 2002-10-15 2004-05-13 Oki Electric Ind Co Ltd 半導体装置、及びその製造方法
US8704359B2 (en) * 2003-04-01 2014-04-22 Ge Embedded Electronics Oy Method for manufacturing an electronic module and an electronic module
JP4161909B2 (ja) * 2004-01-16 2008-10-08 ソニー株式会社 半導体装置の製造方法
JP4654598B2 (ja) * 2004-04-30 2011-03-23 ソニー株式会社 半導体装置およびその製造方法
JP4431747B2 (ja) 2004-10-22 2010-03-17 富士通株式会社 半導体装置の製造方法
JP4844287B2 (ja) * 2006-04-26 2011-12-28 ソニー株式会社 半導体装置及びその製造方法
JP4874005B2 (ja) 2006-06-09 2012-02-08 富士通セミコンダクター株式会社 半導体装置、その製造方法及びその実装方法
JP4869991B2 (ja) * 2007-03-14 2012-02-08 富士通株式会社 キャパシタ内蔵ウェハレベルパッケージ及びその製造方法
JP2009289863A (ja) * 2008-05-28 2009-12-10 Casio Comput Co Ltd 半導体装置の製造方法
TWI521670B (zh) * 2009-05-14 2016-02-11 高通公司 系統級封裝

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001250836A (ja) * 2000-03-06 2001-09-14 Casio Comput Co Ltd 半導体装置およびその製造方法
JP2006310419A (ja) * 2005-04-27 2006-11-09 Casio Comput Co Ltd 半導体装置の製造方法
US20070158857A1 (en) * 2006-01-10 2007-07-12 Casio Computer Co., Ltd. Semiconductor device having a plurality of semiconductor constructs
JP2008047734A (ja) * 2006-08-17 2008-02-28 Sony Corp 半導体装置及び半導体装置の製造方法
CN101847610A (zh) * 2009-03-25 2010-09-29 卡西欧计算机株式会社 半导体装置及其制造方法

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103327741A (zh) * 2013-07-04 2013-09-25 江俊逢 一种基于3d打印的封装基板及其制造方法
CN103327741B (zh) * 2013-07-04 2016-03-02 江俊逢 一种基于3d打印的封装基板及其制造方法
CN108780791A (zh) * 2016-03-01 2018-11-09 索尼公司 半导体装置、电子模块、电子设备和用于生产半导体装置的方法
US11355444B2 (en) 2016-03-01 2022-06-07 Sony Corporation Semiconductor device, electronic module, electronic apparatus each having stacked embedded active components in multilayer wiring board and method for producing the semiconductor device having the same
CN108701654A (zh) * 2016-12-28 2018-10-23 野田士克林股份有限公司 薄膜电容器和半导体器件
TWI665693B (zh) * 2016-12-28 2019-07-11 Noda Screen Co., Ltd. 薄膜電容器及半導體裝置

Also Published As

Publication number Publication date
US9252099B2 (en) 2016-02-02
KR20120033977A (ko) 2012-04-09
JP5758605B2 (ja) 2015-08-05
US20120080788A1 (en) 2012-04-05
KR101256321B1 (ko) 2013-04-18
JP2012079725A (ja) 2012-04-19
TWI485831B (zh) 2015-05-21
TW201218350A (en) 2012-05-01

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Owner name: ZHAOTANJING CO., LTD.

Free format text: FORMER OWNER: ZHAOZHUANGWEI CO., LTD.

Effective date: 20131225

C41 Transfer of patent application or patent right or utility model
TA01 Transfer of patent application right

Effective date of registration: 20131225

Address after: Kanagawa

Applicant after: CASIO COMPUTER CO., LTD.

Address before: Tokyo, Japan, Japan

Applicant before: Casio Computer Co Ltd

C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20120509