TWI476882B - 半導體裝置及其製造方法 - Google Patents
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Description
本申請案係基於在2010年9月28日所申請之日本專利申請案2010-216881號案主張其優先權的利益,該日本專利申請案之全部揭示,包含說明、請求項、圖式及摘要,係以參照的方式全部合併於此。
本發明係關於半導體裝置及其製造方法。
一般所知的習知半導體裝置中,例如特開2008-218731號公報所記載,有所謂晶片尺寸封裝(CSP:Chip Size Package)的技術。該半導體裝置具備有半導體基板。於設置在半導體基板上之絕緣膜的上面設置有配線。配線的島部(land)上面設置有外部連接用電極。於包含配線之絕緣膜的上面且在外部連接用電極的周圍設置有密封膜。於外部連接用電極的上面設置有焊錫凸塊。
上述習知半導體裝置之製造方法上,形成配線及外部連接用電極之後,將由環氧樹脂所構成的密封膜以其厚度比外部連接用電極的高度稍微厚一些的方式形成於包含配線及外部連接用電極之絕緣膜的上面。所以,此狀態下,外部連接用電極的上面係被密封膜所被覆。其次,磨削密封膜的上面側及外部連接用電極的上部,以使外部連接用電極的上面露出。接著,於已露出的外部連接用電極的上面形成焊錫凸塊。
雖然特開2008-218731號公報中並無以下記載,但是,磨削密封膜的上面側及外部連接用電極的上部時,由於係使用研磨石進行磨削(一點一點少許地削去),所以,因磨削會在外部連接用電極的上面產生零碎的毛刺,而從外部連接用電極的上面起位於其周圍之密封膜的上面形成毛刺。因此,一般於處理後,大多會使用硫酸系的蝕刻液來進行濕式蝕刻,藉此去除從外部連接用電極的上面起其周圍之密封膜的上面所形成的毛刺。
但是,當去除從外部連接用電極的上面起其周圍之密封膜的上面所形成的毛刺時,伴隨著該毛刺的去除,會於外部連接用電極的周圍之密封膜的上面形成不必要的凹部,此外,由於過度蝕刻(over etching)而使外部連接用電極的高度不必要地變低,而且,一旦蝕刻液浸入外部連接用電極與密封膜之間,則外部連接用電極的上部外周部會被不必要地蝕刻而變細,因此有著成為外部連接用電極與密封膜之間的密接性降低之原因的問題。又,將晶圓級封裝(WLP:Wafer Level Package)直接埋入印刷配線板的技術,亦即,嵌入式晶圓級封裝(EWLP:Embedded Wafer Level Package)的技術,係於埋入WLP之後在外部連接用電極上的上層絕緣膜設置開口部以與上層配線電性連接。但是,由於外部連接用電極與周圍之密封膜及開口部周緣部之上層絕緣膜等二層接觸,所以,也存在有於層的交界附近密接性不良的問題。
於此,本發明的目的在於提供一種可使外部連接用電極的上面不會產生毛邊的半導體裝置及其製造方法。又,本發明的目的在於提供一種可使外部連接用電極的周側面與上面的交界附近密接性也良好的半導體裝置。
本發明之半導體裝置,具備有:半導體基板,係具有連接墊;外部連接用電極,係以連接於前述連接墊的方式設置在該半導體基板上;及密封膜,係以被覆該外部連接用電極的方式設置;於前述密封膜以露出前述外部連接用電極上面之中央部的方式設置有開口部,且,前述密封膜以被覆前述外部連接用電極上面之外周部的方式設置。
此外,本發明之半導體裝置之製造方法,包含:於半導體基板上以被覆外部連接用電極之周側面及上面的方式形成密封膜,而該外部連接用電極係以連接於該半導體基板之連接墊的方式而形成;及以露出前述外部連接用電極上面之中央部的方式,且,以前述密封膜被覆前述外部連接用電極上面之外周部的方式於前述密封膜形成開口部。
本發明之優點將於隨後的說明中闡述,且部分優點將自說明成為顯而易見,或是藉由實施本發明而得知。可藉由下文中特別指出的手段及組合而實現並獲得本發明之優點。
合併於此且構成說明書之一部分的附圖係例示本發明之實施例,且連同前文中的發明內容及後文中的實施方式用來說明本發明的原理。
將參照圖式說明本發明之實施例。
第1圖顯示作為本發明之一實施形態之半導體裝置的平面圖,第2圖顯示大致沿著第1圖之II-II線之部分的剖面圖。此半導體裝置係一般稱為CSP的裝置,具備有矽基板(半導體基板)1。於矽基板1的上面,雖然未以圖式顯示,形成有構成既定功能之積體電路的元件,例如電晶體、二極體、電阻、電容等元件。於矽基板1的上面周邊部設置有連接於上述積體電路之各元件之由鋁系金屬所構成的複數個連接墊(connection pad)2。
於除了矽基板1的周邊部及連接墊2的中央部以外之矽基板1的上面,設置由氧化矽、氮化矽等所構成的鈍化膜(passivation film)(絕緣膜)3,連接墊2的中央部藉由設置在鈍化膜3的開口部而露出。於鈍化膜3的上面設置有由聚醯亞胺系樹脂所構成的保護膜(絕緣膜)5。於與鈍化膜3的開口部4對應部分的保護膜5設置有開口部6。
保護膜5的上面設置有複數條配線7。配線7係設置在保護膜5的上面而由銅等構成的底層金屬層8與設置在底層金屬層8的上面而由銅構成之上部金屬層9的雙層構造。配線7的一端部7a介著鈍化膜3及保護膜5的開口部4、6而連接於連接墊2,另一端部為島部7b,其間為迂迴線部7c。於配線7的島部7b的上面設置有由銅構成之柱狀的外部連接用電極10。
於包含配線7之保護膜5的上面且於外部連接用電極10的周圍,由包含二氧化矽填充劑之環氧系樹脂等所構成之一片膜狀的密封膜11於其上面設成平坦狀。此情形下,外部連接用電極10的上面外周部被密封膜11被覆,於與外部連接用電極10的上面中央部對應的部分之密封膜11設置有開口部12。開口部12係以露出外部連接用電極10的上面中央部10a的方式設置,密封膜11係以被覆外部連接用電極10的上面外周部10b的方式設置。於密封膜11的開口部12內及其上方設有焊錫凸塊,該焊錫凸塊係連接於外部連接用電極10的上面中央部10a。外部連接用電極10的上面係由上面中央部10a與上面外周部10b所組成。上面中央部10a係包含外部連接用電極10的上面之中心的區域,上面外周部10b係包含外部連接用電極10之上面的外周緣全體的區域。密封膜11的開口部12及外部連接用電極10上面呈略圓形狀,密封膜11之開口部12的直徑係小於外部連接用電極10上面的直徑10μm以下的長度,例如,小數μm~10μm。又,密封膜11之中,位於被覆外部連接用電極10上面之剩餘的區域10b之密封膜11的厚度為10μm以下。
其次說明本半導體裝置之製造方法的一例。首先,如第3圖所示,製備於晶圓狀態的矽基板(以下稱半導體晶圓21)的上面形成有鋁輕金屬等所構成的連接墊2、氧化矽等所構成的鈍化膜3及聚醯亞胺系樹脂等所構成的保護膜5,且連接墊2的中央部藉由鈍化膜3及保護膜5的開口部4、6而露出的構造。
此情況下,半導體晶圓21的厚度比第2圖所示之矽基板1的厚度還厚。此外,於第3圖中,以符號22顯示的區域為切割道(dicing street)。又,去除切割道22及其兩側的鈍化膜3及保護膜5。
其次如第4圖所示,於包含藉由鈍化膜3及保護膜5的開口部4、6而露出之連接墊2的上面之保護膜5的上面、以及切割道22及與其兩側對應之部分之半導體晶圓21的上面形成底層金屬層8。此情況下,底層金屬層8可僅為藉由無電解鍍敷所形成的銅層,也可僅為藉由濺鍍法所形成的銅層,而且也可為在藉由濺鍍法所形成之鈦等薄膜上,藉由濺鍍法形成銅層的構造。
其次,將由正型液狀抗蝕劑所組成的抗鍍膜23形成圖案於底層金屬層8的上面。此情況下,於與上部金屬層9形成區域對應部分之抗鍍膜23形成開口部24。接著,一旦進行將底層金屬層8作為鍍敷電流路之銅的電解鍍敷時,抗鍍膜23的開口部24內之底層金屬層8的上面形成上部金屬層9。其次,將抗鍍膜23剝離。
接著如第5圖所示,將由負型乾膜抗蝕劑組成的抗鍍膜25形成圖案於包含上部金屬層9之底層金屬層8的上面。此情況下,於與上部金屬層9之的島部(外部連接用電極10形成區域)對應部分之抗鍍膜25形成開口部26。
接著,一旦進行將底層金屬層8作為鍍敷電流路之銅的電解鍍敷時,抗鍍膜25的開口部26內之上部金屬層9的島部上面形成外部連接用電極10。此情況下,外部連接用電極10的上部並非平坦而是呈圓頂(dome)狀。又,外部連接用電極10的高度比第2圖所示之外部連接用電極10的高度還高。
其次如第6圖所示,準備平刨機(surface planer)27。該平刨機27係配置成固定,且於旋轉圓盤28之周邊部下面設置有刀刃29,並藉由驅動手段(未以圖式顯示)的驅動而可一併旋轉圓盤28與刀刃29。
再者,使刀刃29的刀尖位於外部連接用電極10之最後的高度位置,並使旋轉圓盤28與刀刃29一同旋轉。於此狀態下,當使具有外部連接用電極10及抗鍍膜25等的半導體晶圓21朝水平方向移動時,藉著與旋轉圓盤28一同旋轉的刀刃29而能切割並去除全部外部連接用電極10的上部及與該部分對應的抗鍍膜25的上面側,如第7圖所示,外部連接用電極10的高度整齊一致為最後的高度位置,而且,外部連接用電極10及抗鍍膜25的上面係成一個面。以此方式,若是包含銅之外部連接用電極或金等柔軟的金屬、抗鍍膜25的話,就能以平刨機27切割而能將表面處理成平滑。
此情況下,全部的外部連接用電極10的上部及與該上部對應之抗鍍膜25的上面側可藉由刀刃29的刀尖一次乾脆地切割去除,因此,與使用研磨石的情況不同,不會於外部連接用電極10的上面產生毛刺。所以,不須要進行用以去除毛刺而使用濕式蝕刻所為的後處理,不會使外部連接用電極10的高度不必要地變低,也不會使外部連接用電極10的上部外周部不必要地變細。
接著,將抗鍍膜25剝離。又,也可建構成剝離抗鍍膜25之後,使用平刨機27切割去除外部連接用電極10的上部。但是,如以上所述,若在殘留著抗鍍膜25的狀態下切割去除外部連接用電極10的上部,則因存在有抗鍍膜25而能使外部連接用電極10完全不會倒下。又,外部連接用電極10的切割殘渣不會附著於上部金屬層9,於剝離抗鍍膜25時能一併去除切割殘渣。
接著,當將上部金屬層9作為遮罩而蝕刻並去除上部金屬層9下以外之區域的底層金屬層8時,如第8圖所示,僅在上部金屬層9之下殘留有底層金屬層8。以此狀態下,藉著上部金屬層9與殘留在其下的底層金屬層8而形成了雙層構造的配線7。
其次,如第9圖所示,藉著網版印刷法等將由包含二氧化矽填充劑之環氧系樹脂等所構成的密封膜11以其厚度比外部連接用電極10的高度稍微厚一點的方式,形成於切割道22及其兩側之半導體晶圓21的上面以及包含配線7及外部連接用電極10之保護膜5的上面。因此,以此狀態下,藉著一片膜狀的密封膜11被覆外部連接用電極10的上面。
其次,使用研磨石(未以圖式顯示)磨削密封膜11的上面側,如第10圖所示,於外部連接用電極10上,密封膜11僅剩餘10μm以下,例如厚度僅剩餘數μm~10μm,且將密封膜11的上面予以平坦化。因此,此狀態下外部連接用電極10的上面被薄的密封膜11被覆。又,由於不磨削外部連接用電極10的上部,所以外部連接用電極10的上面不會產生毛刺。
其次如第11圖所示,藉著對與外部連接用電極10之上面中央部對應的部分之密封膜11照射CO2、釔鋁石榴石(YAG)等雷射光束的雷射加工而形成開口部12。此時,係以開口部12將外部連接用電極10上面的一部分區域10a露出的方式,且以密封膜11被覆外部連接用電極10上面之剩餘區域10b的方式,於密封膜11形成開口部12。密封膜11的開口部12及外部連接用電極10上面為略圓形狀,開口部12的直徑係設成僅比外部連接用電極10的直徑小10μm以下的長度,例如僅小數μm~10μm。因此,以此狀態下,外部連接用電極10之上面外周部被密封膜11被覆,而能達到外部連接用電極10與密封膜11之間難以產生剝離。
接著如第12圖所示,適宜地削去半導體晶圓21的下面側,以使半導體晶圓21的厚度變薄。其次如第13圖所示,於密封膜11之開口部12內及其上方使焊錫凸塊13連接於外部連接用電極10的上面中央部而形成。接著如第14圖所示,沿著切割道22切斷密封膜11及半導體晶圓21,即可獲得複數個第2圖所示的半導體裝置。
此領域的技術人員將輕易想到額外的優點及變化例。因此,根據較廣義態樣的本發明並不限於在此所顯示並說明的具體詳細代表實施例。所以,在不背離隨附的請求項及其均等物所定義的發明一般概念的精神及範圍,可作各種修改。
1...矽基板
2...連接墊
3...鈍化膜
4...開口部
5...保護膜
6...開口部
7...配線
7a...端部
7b...島部
7c...迂迴線部
8...底層金屬層
9...上部金屬層
10...外部連接用電極
10a...上面中央部
10b...上面外周部
11...密封膜
12...開口部
13...焊錫凸塊
21...半導體晶圓
22...切割道
23...抗鍍膜
24...開口部
25...抗鍍膜
26...開口部
27...平刨機
28...旋轉圓盤
29...刀刃
第1圖係作為本發明之一實施形態之半導體裝置的平面圖。
第2圖係大致沿著第1圖之II-II線之部分的剖面圖。
第3圖係於第1圖及第2圖所示之半導體裝置之製造方法的一例,最初準備之構成的剖面圖。
第4圖係接續第3圖之步驟的剖面圖。
第5圖係接續第4圖之步驟的剖面圖。
第6圖係接續第5圖之步驟的剖面圖。
第7圖係接續第6圖之步驟的剖面圖。
第8圖係接續第7圖之步驟的剖面圖。
第9圖係接續第8圖之步驟的剖面圖。
第10圖係接續第9圖之步驟的剖面圖。
第11圖係接續第10圖之步驟的剖面圖。
第12圖係接續第11圖之步驟的剖面圖。
第13圖係接續第12圖之步驟的剖面圖。
第14圖係接續第13圖之步驟的剖面圖。
1...矽基板
2...連接墊
3...鈍化膜
4...開口部
5...保護膜
6...開口部
7...配線
7a...端部
7b...島部
7c...迂迴線部
8...底層金屬層
9...上部金屬層
10...外部連接用電極
10a...上面中央部
10b...上面外周部
11...密封膜
12...開口部
13...焊錫凸塊
Claims (18)
- 一種半導體裝置,包含:半導體基板,係具有連接墊;外部連接用電極,係以連接於前述連接墊的方式設置在該半導體基板上;及密封膜,係以被覆該外部連接用電極的方式設置;於前述密封膜以露出前述外部連接用電極上面之中央部的方式設置有開口部,且,在前述外部連接用電極上面之外周部形成該密封膜。
- 如申請專利範圍第1項之半導體裝置,其中,前述密封膜係一片膜狀。
- 如申請專利範圍第1項之半導體裝置,其中,於前述半導體基板上設置有絕緣膜,並於前述絕緣膜上以連接前述連接墊的方式設置有配線,且於前述配線的島部(land)上設置有前述外部連接用電極。
- 如申請專利範圍第1項之半導體裝置,其中,除了前述開口部以外之前述密封膜的上面係平坦狀。
- 如申請專利範圍第1項之半導體裝置,其中,前述密封膜之中,於前述外部連接用電極上面之前述外周部的前述密封膜之厚度係10μm以下。
- 如申請專利範圍第1項之半導體裝置,其中,前述密封膜的開口部及前述外部連接用電極上面係圓形狀,且前述密封膜之開口部的直徑係僅比前述外部連接用電極上面的直徑小10μm以下的長度。
- 如申請專利範圍第1項之半導體裝置,其中,於前述密封膜之開口部內及前述密封膜上,以至少連接前述外部連接用電極上面之中央部的方式設置有焊錫凸塊。
- 如申請專利範圍第1項之半導體裝置,其中,前述密封膜係直接形成在前述外部連接用電極上面之外周部。
- 一種半導體裝置之製造方法,包含:於半導體基板上以被覆外部連接用電極之周側面及上面的方式形成密封膜,而該外部連接用電極係以連接該半導體基板之連接墊的方式而形成,以露出前述外部連接用電極上面的中央部的方式,且以在前述外部連接用電極上面之外周部形成前述密封膜的方式於前述密封膜形成開口部。
- 如申請專利範圍第9項之半導體裝置之製造方法,其中,前述密封膜係一片膜狀。
- 如申請專利範圍第9項之半導體裝置之製造方法,其中,使用形成有圖案之抗鍍膜並藉由電解鍍敷而於前述半導體基板上形成前述外部連接用電極,剝離前述抗鍍膜,其中,於形成前述外部連接用電極之後,且於剝離前述抗鍍膜之前,係在前述抗鍍膜殘留於前述半導體基板上的狀態下,切割去除前述外部連接用電極的上部及前述抗鍍膜的上面側。
- 如申請專利範圍第11項之半導體裝置之製造方法,其中,以平刨機切割去除前述外部連接用電極的上部之後,以被覆前述外部連接用電極上面全體的方式形成 前述密封膜,於前述密封膜形成前述開口部之前,以於前述外部連接用電極上面全體殘留前述密封膜的方式形成前述密封膜。
- 如申請專利範圍第12項之半導體裝置之製造方法,其中,以前述平刨機切割且同時去除前述外部連接用電極的上部及前述抗鍍膜的上面側。
- 如申請專利範圍第9項之半導體裝置之製造方法,其中,形成前述密封膜之後,且於前述密封膜形成前述開口部之前,以於前述外部連接用電極上僅殘留厚度10μm以下的前述密封膜的方式磨削前述密封膜的上面側。
- 如申請專利範圍第9項之半導體裝置之製造方法,其中,藉由照射雷射束的雷射加工而於前述密封膜形成前述開口部。
- 如申請專利範圍第9項之半導體裝置之製造方法,其中,前述密封膜之前述開口部及前述外部連接用電極上面係圓形狀,且以前述密封膜之前述開口部的直徑僅比前述外部連接用電極的直徑小10μm以下的方式於前述密封膜形成前述開口部。
- 如申請專利範圍第9項之半導體裝置之製造方法,其中,於前述密封膜之前述開口部內及前述密封膜上,以至少連接前述外部連接用電極上面之中央部的方式形成焊錫凸塊。
- 如申請專利範圍第9項之半導體裝置之製造方法,其中 ,前述密封膜係直接形成在前述外部連接用電極上面之外周部。
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JP5466785B1 (ja) * | 2013-08-12 | 2014-04-09 | 太陽誘電株式会社 | 回路モジュール及びその製造方法 |
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CN1471161A (zh) * | 2002-06-14 | 2004-01-28 | ����ŷ�������ʽ���� | 半导体器件及其制造方法 |
CN1790686A (zh) * | 2004-09-17 | 2006-06-21 | 卡西欧计算机株式会社 | 具有密封膜的芯片尺寸的半导体装置及其制造方法 |
US7220657B2 (en) * | 1999-01-27 | 2007-05-22 | Shinko Electric Industries, Co., Ltd. | Semiconductor wafer and semiconductor device provided with columnar electrodes and methods of producing the wafer and device |
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JP4413240B2 (ja) | 2007-03-05 | 2010-02-10 | Okiセミコンダクタ株式会社 | 半導体装置の製造方法 |
JP2009289863A (ja) * | 2008-05-28 | 2009-12-10 | Casio Comput Co Ltd | 半導体装置の製造方法 |
JP5097792B2 (ja) * | 2009-08-17 | 2012-12-12 | サムソン エレクトロ−メカニックス カンパニーリミテッド. | 円筒型キャパシタを備えたウェーハレベルパッケージ及びその製造方法 |
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US7220657B2 (en) * | 1999-01-27 | 2007-05-22 | Shinko Electric Industries, Co., Ltd. | Semiconductor wafer and semiconductor device provided with columnar electrodes and methods of producing the wafer and device |
CN1471161A (zh) * | 2002-06-14 | 2004-01-28 | ����ŷ�������ʽ���� | 半导体器件及其制造方法 |
CN1790686A (zh) * | 2004-09-17 | 2006-06-21 | 卡西欧计算机株式会社 | 具有密封膜的芯片尺寸的半导体装置及其制造方法 |
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US8564128B2 (en) | 2013-10-22 |
CN102420197A (zh) | 2012-04-18 |
US20120074564A1 (en) | 2012-03-29 |
JP2012074461A (ja) | 2012-04-12 |
JP5603191B2 (ja) | 2014-10-08 |
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