TWI470843B - 在基板中安置元件之方法及其元件安置之基板結構 - Google Patents
在基板中安置元件之方法及其元件安置之基板結構 Download PDFInfo
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- TWI470843B TWI470843B TW100113577A TW100113577A TWI470843B TW I470843 B TWI470843 B TW I470843B TW 100113577 A TW100113577 A TW 100113577A TW 100113577 A TW100113577 A TW 100113577A TW I470843 B TWI470843 B TW I470843B
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- 239000000758 substrate Substances 0.000 title claims description 111
- 238000000034 method Methods 0.000 title description 60
- 229910052751 metal Inorganic materials 0.000 claims description 88
- 239000002184 metal Substances 0.000 claims description 88
- 239000011347 resin Substances 0.000 claims description 76
- 229920005989 resin Polymers 0.000 claims description 76
- 238000007747 plating Methods 0.000 claims description 51
- 229920001187 thermosetting polymer Polymers 0.000 claims description 32
- 239000004634 thermosetting polymer Substances 0.000 claims 2
- 239000010410 layer Substances 0.000 description 151
- 235000012431 wafers Nutrition 0.000 description 72
- 238000009713 electroplating Methods 0.000 description 34
- 239000004065 semiconductor Substances 0.000 description 15
- 238000012546 transfer Methods 0.000 description 15
- 230000008569 process Effects 0.000 description 12
- 239000000463 material Substances 0.000 description 9
- 229910002601 GaN Inorganic materials 0.000 description 7
- 239000013078 crystal Substances 0.000 description 7
- 238000000151 deposition Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 7
- 230000008021 deposition Effects 0.000 description 6
- 238000005253 cladding Methods 0.000 description 4
- 238000011161 development Methods 0.000 description 4
- 238000009826 distribution Methods 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- 238000013459 approach Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 239000003086 colorant Substances 0.000 description 3
- 238000010276 construction Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000009194 climbing Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 239000008151 electrolyte solution Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000009429 electrical wiring Methods 0.000 description 1
- 238000005868 electrolysis reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004299 exfoliation Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000004020 luminiscence type Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000000088 plastic resin Substances 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000003685 thermal hair damage Effects 0.000 description 1
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
- H05K3/305—Affixing by adhesive
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- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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Description
根據本發明之原理,本發明大體上係關於一種在一基板上安置元件之方法及其一種元件安置基板結構,其中藉由使用該基板之一佈線線路作為一晶種金屬使用電解電鍍來執行該等元件之端子連接。
本發明主張2010年4月28日向日本專利局申請之日本專利申請案JP 2010-103142之優先權,在法律所允許程度上該案之全文以引用方式併入本文中。
為了在由一半導體或樹脂所製成之一佈線基板中安置元件(諸如一半導體晶片或一分開組件),可在一單一佈線基板之一表面或兩表面中(如在一典型印刷佈線基板中)安置該元件,或在一多層佈線基板中安置該元件。
尤其,為了製造一多層佈線基板,已知一種方法(建置),其中在基底基板之一表面中形成之一導電層中安置該元件,及藉由以下步驟而在一單一側建置一多層基板:重複形成層間絕緣層;形成該佈線線路;及元件安置。此外,亦存在一種已知方法:對於核心基板之兩表面,形成該佈線線路;形成該層間絕緣層;及執行元件安置。
一種在一半導體基板(基底晶片)上堆疊其他裸晶片同時獲得介於端子之間的連接之方法亦可係該建置方法之一種類型。
在該佈線基板中安置該等元件之情況下,特定言之,在所安置之元件係微小的及複數個之情況下,一種在該佈線基板上以一高精確度統一配置(轉移)複數個元件之技術係重要的。
例如,在JP-A-2004-273596中揭示此一元件轉移技術。在本揭示內容中,在一第一基板上之樹脂層中固持一元件,該第一基板係自該樹脂層側接合至一第二佈線線路,同時固持該元件,及在介於該樹脂層與該第一基板之間的界面處執行剝落,使得統一轉移該等元件至一第二分開基板。
當基板區域相當大時,此一元件轉移方法尤其有效。此外,當以一高精確度規則配置相當大量的元件時,在該樹脂層中固持該等元件及統一轉移該等元件至一分開基板中之該方法係進一步有效的。
JP-A-2004-273596揭示一種製造一LED顯示器之方法,其中為此目的,自LED元件發射光。
然而,在不限於統一轉移此等元件之一情況下,期望繼在該佈線基板中配置該等元件之後提供介於該元件之電極墊與該佈線線路之間的機械上及電氣上兩者之穩固接合,而不管是否該等元件係安置在一單層基板或係安置一多層基板上。
在此點上,日本專利案第3956955號及JP-A-2005-311109揭示一種無電極電鍍方法,作為一種連接該等元件與該佈線基板之方法。
JP-A-2004-273596揭示一種在其之實例中使用無電極電鍍來連接介於該佈線基板與該等安置元件之間的端子之方法。
此外,根據JP-A-2005-311109,一材料(稱為一側填料)係使用一微量施配器或類似物而塗於該佈線基板上,及元件(半導體雷射)接合至該佈線基板上。使用能夠獲得對準之一裝置(諸如一覆晶接合器)來配置該等元件。在此情況下,介於該元件墊與該佈線線路之間的一間隙係形成為數微米或數十微米(μm),且在此狀態下執行無電極電鍍製程。
如在日本專利案第3956955號中所描述,當使用一無電極電鍍方法來連接該佈線基板與置於元件之上表面上之電極時,同時增長來自該佈線線路之電鍍沈積及來自電極墊之電鍍沈積。在此過程中,隨著電鍍層自兩側接近,產生難以引進一電鍍溶液之一所得結構。因此,隨後沈積增加了厚度。因此,在該等部分中產生一所謂的微間隙。若該電鍍層未增長為一厚度10微米至30微米以填充該間隙,則難以適當地連接兩個導電層(包含該佈線線路與該電極墊)。此外,甚至當暫時填充該間隙時,可產生具有一弱機械強度之一部分。
根據JP-A-2005-311109,兩個導電層(包含該佈線線路與該元件電極墊)係平面對平面的,且介於該兩個導電層之間的間隙係如數微米或數十微米一樣窄。因此,認為相對難以產生一間隙。甚至在此情況下,由於使用無電極電鍍而自兩個方向進行沈積,所以產生一斷續沈積界面,其中機械強度係不足夠的。
然而,在根據上文所描述之建置方法之連接結構中,需要繼安置元件之後形成一層間絕緣膜及形成一通孔或類似物。因此,需要在該元件中提供熱電阻。此外,該絕緣膜其本身之成本亦係高的。
此外,在該元件係微小的及在上表面及下表面兩者中形成電極墊之情況下,在典型建置連接中無需下文製程。
首先,在該基板中安置該元件,及在該元件之表面上形成該電極墊。其次,自該表面接合另一基板,其中藉由內插該元件而形成該電極墊。接著,移除最初已安置該元件之該基板,使得在面對形成該電極墊之該元件之該表面之另一表面上形成該電極墊。
在此一建置連接方法中,製程數目係大的,且相應地,產品良率劣化。
若該元件係一發光元件且係一頂部發射類型(其中光射發至該基板之前表面側),則在該建置中所使用之材料中需要耐光性。此外,在底部發射類型(其中光射發至背表面側)案例中,則在安置中所使用之材料中需要耐光性。因此,難以實施滿足兩者條件之一材料。特定言之,在光密度係其他顯示器之光密度的100倍或高於100倍之一微型LED顯示器中,僅少量有限材料滿足此等條件。
本文揭示提供一種在一基板中安置元件之方法(作為替代前文所提及之建置連接之一新穎連接方法)及一種元件安置基板結構,該方法及該結構能夠使用電解電鍍來獲得介於佈線基板與元件電極之間的穩固接合。
在一實施例中,存在一種總成,該總成包含:一基板;一金屬佈線層,其係在該基板上,在該金屬佈線層中具有一開孔;一熱固性樹脂層,其係在該基板之至少一部分上,該熱固性樹脂層覆蓋該金屬佈線層之該開孔;及一元件,其係在該樹脂層上,該元件係定位於該金屬佈線層之該開孔上及經由該樹脂層接合至該基板。
在另一實施例中,該元件進一步包含圍繞該元件之一可光固化區域。
在另一實施例中,該元件包含在該金屬佈線層上之一電鍍層,該電鍍層有效地電連接該佈線層與該元件。
在另一實施例中,存在一種方法,該方法包含:提供一基板,在該基板之一表面上具有一金屬佈線層,在該金屬佈線層中具有一開孔;在該基板之至少一部分上形成一熱固性樹脂層,該熱固性樹脂層覆蓋該金屬佈線層之該開孔;將一元件定位於該樹脂層上,使得該元件係在該金屬佈線層之該開孔上;及移除未曝光樹脂層。
在另一實施例中,該方法進一步包含加熱該樹脂層之步驟。
在另一實施例中,該方法進一步包含以下步驟:藉由使該樹脂層之至少一部分曝光於一固化能量而固化該樹脂,自背向具有該金屬佈線層之該表面之該基板之一表面起始該曝光。
在另一實施例中,該方法包含以下步驟:藉由使該熱固性樹脂層之至少一部分曝光於一固化能量而部分固化該樹脂層之一區域以形成圍繞該元件之一可光固化區域。
在另一實施例中,該方法包含以下步驟:藉由用一電流電解電鍍該金屬佈線層而在該金屬佈線層上形成一電鍍層,該電鍍層有效地電連接該佈線層與該元件。
在另一實施例中,存在一種包含一總成之電子裝置。該總成包含:一基板;一金屬佈線層,其係在該基板上,在該金屬佈線層中具有一開孔;一熱固性樹脂層,其係在該基板之至少一部分上,該熱固性樹脂層覆蓋該金屬佈線層之該開孔;及一元件,其係在該樹脂層上,該元件係定位於該金屬佈線層之該開孔上及經由該樹脂層接合至該基板。
在另一實施例中,該總成進一步包含圍繞該元件之一可光固化區域。
在另一實施例中,該總成進一步包含在該金屬佈線層上之一電鍍層,該電鍍層有效地電連接該佈線層與該元件。
後文將參考隨附圖式更詳細描述根據本發明之原理之目前較佳實施例。雖然下文將在具有各種技術較佳限制之情況下描述目前較佳實施例,但是如在申請專利範圍中所陳述之本發明之範疇不限於此,除非下文以其他方式描述。
本發明之目前較佳實施例係關於一種藉由使用在一佈線基板上之一晶種金屬作為一饋電層來執行電解電鍍之方法。在此案例中,目前較佳實施例揭示一種使用電解電鍍來獲得介於該晶種金屬與自該晶種金屬沿向上方向所定位之元件之電極墊之間的電連接之結構及方法。
由樹脂固持該元件,及移除樹脂(惟必要部分除外),使得該元件暫時固定於該佈線基板。後文藉由電解電鍍獲得連接。
下文目前較佳實施例包含:一種在電鍍期間固定該元件之方法,特定言之,介於電極與該晶種金屬之間的一位置關係;一種暫時固定方法;一種移除一非必需部分之方法;一種適合電鍍之元件結構或類似物。後文將自此等觀點而作出描述。
圖1A至圖1G係圖解說明根據本發明之原理之一種在一基板中安置元件之方法之橫截面圖。
首先,將參考圖1G描述一種元件安置基板結構。
在一LED顯示器中,在一面板基板(如色彩像素發光單元)中預先安置複數個LED晶片(例如,紅色、綠色及藍色(RGB)色彩之半導體LED晶片)。例如,在一完全HD規範中,安置近似2百萬個LED晶片。後文將此一色彩像素發光單元稱為「三重晶片」。根據本發明之實施例,該三重晶片對應於「色彩像素晶片」之一實例。
圖1G圖解說明當形成該三重晶片時在該三重晶片基板中所安置之一單一單色發光二極體(LED)半導體晶片之一外觀。在相似於所圖解說明之安置結構之一結構中,添加另兩種色彩之半導體晶片發光,使得並排配置三個半導體晶片。
雖然藉由在諸如石英玻璃之一透明基板(稱為三重基板2或一晶片配置基板)中安置一半導體晶片(一LED晶片3)而獲得圖1G中所展示之三重晶片1,但是在描述安置製程之前,後文將簡要描述三重晶片1之形成。
RGB之LED晶片3係根據一目前較佳實施例之一「元件」之一實例且係包含一基於氮化物半導體的材料(諸如氮化鎵)之一發光二極體元件。
例如,LED晶片3具有一雙異質結構,其中一作用層係內插於P包覆層與n包覆層之間。此外,本文所圖解說明之LED晶片3具有一近似平的面板形狀,及LED晶片3之該作用層及該包覆層係在平行於由藍寶石或類似物製成之該基板之主要表面之一平面上延伸以增長作用層及包覆層。藉由沈積一層氮化鎵晶體層或類似物而形成此一層。
在此一類型的半導體層中,需要至少部分變更發光波長,且因此難以同時在相同基板上形成紅色、綠色及藍色色彩之三種LED晶片3。在高度達到數微米,或一側或半徑達到數十微米之意義上說,晶片之大小非常小。透過一半導體製程在各色彩之晶磊增長晶圓上形成對應於此一晶片之部分以提供一非常薄的晶圓厚度,並接著轉移該部分至在一接收側中之另一基板,以使一配置間距大於在該晶圓上所形成之間距。在此轉移製程中,使用一種雷射衝壓方法。
藉由針對各色彩執行此晶片轉移而對準所謂的色彩配置。在此色彩配置中,並排地相鄰配置RGB之LED晶片。轉移及移除具有藉由重複透過此一色彩配置所並排配置之色彩像素單位所並排配置之LED晶片3之基板至另一基板/自另一基板轉移及移除該基板以形成另一電極,使得在兩表面上形成不同電極(對應於陽極之一P電極及對應於陰極之一N電極)。
以此方式,預先備製在三重基板2中待安置之元件側。
在圖1G中,在三重基板2之安置表面上(例如,自P電極3P側)放置此LED晶片3。同時,在LED晶片3之表面上形成N電極3N。
在三重基板2之安置表面上,預先形成在電鍍期間充當為一晶種金屬之佈線層4R及4L(若未指明,則後文稱為一金屬佈線層4)。雖然圖式中分開圖解說明金屬層4R及4L,但是其等至少具有相同電位。佈線層4R及4L被連接並建構為一平面圖案。
金屬佈線層4係由(例如)Ti/Au或類似物所製成之一佈線線路且係透過既有方法(包含沈積、微影蝕刻(包含曝光及顯影))而形成。
LED晶片3係藉由內插電解電鍍層5而接合至金屬佈線層4。自金屬佈線層4之曝光表面之整個區域增長電解電鍍層5,及電解電鍍層5之一部分攀升LED晶片3之側表面之裙部部分。作為一特性點,在面對金屬佈線層4與LED晶片3之P電極3P之間的間隙中填充或在對應間隙中緊密地填充電解電鍍層5。
此外,雖然電解電鍍層5攀升圖1G中之LED晶片3之側表面,但是取決於電鍍層之厚度或類似因素可無需攀升。
為了形成在圖1A中之此一結構,在三重基板2之一主表面上藉由循序執行(例如)濺鍍、抗蝕件形成、曝光、顯影及蝕刻而形成佈線層4R及4L。
參考圖1A之橫截面,在安置LED晶片3之部分中佈線層4R及4L係彼此分開的。例如,佈線層4R及4L係一單一金屬佈線層之一部分,及在該金屬佈線層中形成具有一大小近似為4x4微米之一開孔。
參考圖1B,塗佈樹脂(較佳係光敏性樹脂)以在已形成之金屬佈線層4(包含4R及4L)上具有(例如)一近似1.5微米之厚度。該樹脂係藉由外部因素(諸如加熱或光照)而固化之塑膠樹脂。在此,使用熱固性光敏性樹脂6。藉由以下步驟而形成熱固性光敏性樹脂6:接合具有一薄片形狀之樹脂;或透過旋塗或類似方法塗佈樹脂;及在一預先烘烤處理或類似處理中使一溶劑揮發。此外,雖然可利用一種自另一基板之轉移及移除方法,但是由於熱固性光敏性樹脂6具有一相對薄的厚度,及無需埋藏元件或凹凸部分,所以可透過薄片接合或旋塗而充分形成熱固性光敏性樹脂。
在此,透過在圍繞圖1C中所展示之LED晶片3之一部分的部分曝光而在此部分中而形成一可光固化區域6A。除可使用一遮罩之典型方法之外,亦可使用一離子束或類似物來執行該部分曝光。
參考圖1C,在熱固性光敏性樹脂6上放置預先備製之LED晶片3。在此情況下,抵靠金屬佈線層4之定位係尤其不受限的。
參考圖1D,例如,將此狀態之整個三重晶片加熱至一溫度50℃達近似30分鐘。可在適合樹脂特性之一範圍內判定加熱溫度或時間。透過該加熱,降低該樹脂之粘度,及該樹脂攀升LED晶片3之側壁,使得形成一圓角。由於該加熱樹脂之分子趨向於在一最低能量狀態下安定下來,所以該樹脂施加一力量以在該圓角中將整個LED晶片3按壓下去。若LED晶片3被按壓下去,則直接在P電極3P下面之該樹脂被擠壓至其之外側,且P電極3P接近金屬佈線層4。
借助於此一力量,當最初放置時在RGB晶片之間偏離了0.2微米至1.5微米之介於P電極3P與金屬佈線層4之間的間隙係減小至微米0至0.3微米以吸收偏差。
然而,隨著P電極3P接近金屬佈線層4附近之一特定點,由於需要大量能量以完全地移除該樹脂,所以難以接近越出此點。為此,P電極3P及金屬佈線層4係在具有一薄間隙之情況下安定下來。此外,甚至當P電極3P與金屬佈線層4彼此接觸時,仍難以鄰接整個表面,且P電極3P與金屬佈線層4最多僅係彼此部分靠近。
因此,雖然可實施元件對佈線線路之自對準,但是較佳係提供一可光固化區域6A以防止軟化樹脂逸出至外面並且改良效率。雖然可光固化區域6A較佳經形成以環繞LED晶片3之圓周,但是可光固化區域6A可斷續地分解成複數片。
此外,若可光固化區域6A係關於金屬佈線層4以一高精確度對準,則熱固性光敏性樹脂6亦可關於金屬佈線層4之連接沿一xy方向自對準。
參考圖1E,較佳自視覺上透明之三重基板2之後表面曝光熱固性光敏性樹脂6。在此情況下,金屬佈線層4係充當為一自對準遮罩層,使得在介於佈線層4R與佈線層4L之間的區域處固化樹脂部分。該固化樹脂部分係充當為一「暫時固定部分」。
此外,當由金屬佈線層4所獲得之自對準遮罩不充分時,可限制一遮罩路徑或一光束曝光區域(諸如EB)。特定言之,為了在如下文所描述之傳遞期間執行後表面曝光,較佳係僅使用金屬佈線層4作為一遮罩層。
參考圖1F,透過顯影移除未曝光部分。在此情況下,在介於P電極3P與金屬佈線層4之間的間隙中之該樹脂係由金屬佈線層4所封鎖且未曝光。因此,溶解顯影溶液,且移除在此地方中之未曝光樹脂部分。由於在具有一高強度之暫時固定部分中固持一元件,所以維持此一間隙。
此外,如圖1G中所展示般執行電解電鍍。在該電解電鍍期間,藉由將(例如)一0.5伏至1.0伏電壓施加至對應於負電極之金屬佈線層4及電解溶液而使一10 mA/cm2
電流流動通過具有正電極板之電解電鍍溶液。因此,如圖1G中所展示,起始一電鍍增長,且最終形成(例如)具有一0.5微米厚度之一電解電鍍層5。因此,機械上及電氣上穩固連接金屬佈線層4與P電極3P。
圖2係圖解說明藉由一真實樣本的SIM攝影所拍攝之介於金屬佈線層4與P電極3P之間的連接之一外觀之一示意圖。
參考圖2,認為在由一圓圈所環繞之部分中提供連續結晶種粒(grain)。因此,獲得强固接合。
根據此方法,最初未電連接金屬佈線層4與P電極3P(對應於藉由電鍍所接合之兩個物件)。此外,自金屬佈線層4沿為電鍍之一主方向之向上方向定位P電極3P。根據此實施例,自金屬佈線層4沿該向上方向定位P電極3P,使得金屬佈線層4與P電極3P緊密地面對彼此。
由於未電連接金屬佈線層4與P電極3P,所以最初自金屬佈線層4增長電鍍。然而,由於該電鍍之增長頂面通常係圓形的,所以最初與電極墊接觸之一部分係限於一點或一明顯限制區域。
繼電接觸之後,電鍍自金屬佈線層4及與金屬佈線層4接觸之P電極3P兩者增長,且接觸表面逐漸加寬。
以此方式,若該電鍍自一特定窄範圍逐漸加寬,則抑制空隙之產生,且容易獲得更多整合作為一合成物之結晶種粒。為此,相較於電解電鍍或無電極電鍍,其中當兩個接合目標彼此接觸時開始該電鍍,可能獲得機械上及電氣上兩者之穩固接合。
此外,熱損傷或機械損傷未施加於元件以透過在一室溫下電鍍而獲得接合亦係有利的。
除該電鍍之外,亦可獲得下文優點。
由於可在元件之上表面上形成一功能元件,及可在下表面上形成一端子,所以可能使元件小型化及降低成本。
在元件係在該元件之上表面發射光之情況下,由於未在該元件之該上表面上形成佈線線路(與建置連接不同),所以該發光元件之發光區域不受限於該元件之該端子及該佈線線路。此外,未劣化該發光元件之輸出功率或發光特性,諸如一視野。
由於在該元件之該下表面中產生連接,所以與建置連接不同的係,無需用於緩和元件厚度中之步階之一絕緣層。因此,可能降低絕緣膜形成製程所伴隨之一熱歷程或應力及降低成本,並且改良該元件之可靠度。此外,可降低在該元件中必需之一耐熱溫度。
特定言之,當使用一典型樹脂絕緣膜來固定具有一1至10W/cm2
高發光密度之一元件(諸如一LED)時,光使該樹脂絕緣膜劣化,及使該元件之可靠度劣化。在本實施例中,可能在無此樹脂之情況下以一足夠強度將該元件固定至佈線基板並且獲得電連接。
此外,由於沿該元件之z方向執行自對準,所以介於該基板與該元件之間的間隙變為恆定,及在實際意義上充分減小電鍍厚度。因此,可使用電解電鍍來統一連接數百萬個元件。
圖3係圖解說明根據本發明之原理之三重晶片1A之一結構圖。
圖3中所展示之三重晶片1A係相似於圖1G中所展示之三重晶片,此係因為在三重基板2上形成金屬佈線層4,及LED晶片3之電極係使用熱固性光敏性樹脂6而接合至金屬佈線層4。
此外,圖3中所展示之三重晶片1A係相似於圖1G中所展示之三重晶片,此係因為一暫時固定部分6B(如熱固性光敏性樹脂6之一剩餘部分)係存在於金屬佈線層4之開孔中。
在LED晶片3之結構及對應於LED晶片3之該結構之佈線線路之一組態中,本實施例與前文所描述的實施例不同。
圖3中所展示之LED晶片3包含在下表面中並排配置之一P電極3P及一N電極3P。在內部結構中,在該基板之主要部分之該下表面中形成一作用層31,及在作用層31中形成內部P電極32。同時,在與提供一高度差之一側相反之另一側中形成內部N電極33。內部P電極32及內部N電極33分別透過具有不同高度之插塞而連接至P電極3P及N電極3N。
具有此一結構之LED晶片3B係向上發射光之一頂部發射類型。在該頂部發射類型中,暫時固定部分6B無需具有透明度或耐光度。因此,可選擇種類繁多的材料係有利的。此一優點係常見於第一實施例。
此外,由於安置方法其本身係共同於前文所描述之實施例,所以將省略該安置方法之描述。在本實施例中,自金屬佈線層4沿向上方向定位P電極3P及N電極3N以緊密地面對金屬佈線層4,及P電極3P及N電極3N係分別單獨連接至對面佈線線路6P及6N。
因此,在此連接中,完成P側及N側兩者之電連接,及完成在三重晶片1A內之電連接。
根據本發明之原理之另一實施例係關於一種在面板基板中安置三重晶片(色彩像素組態之一基本單元)之方法,其中可使用第一實施例或第二實施例之方法而在三重基板2中安置內部LED晶片3。
圖4A及圖4B分別係圖解說明三重晶片10之一平面圖及圖解說明繼安置三重晶片10之後之面板結構之一橫截面結構圖。
圖4A中所展示之三重晶片10對應於根據本發明之實施例之該元件之一實例。此外,由圖1A中之參考數字「1」所表示之該元件及由圖4A中之參考數字「10」所表示之該元件係相似地稱為「三重晶片」。然而,例如,鑑於圖4B之內側透明地獲得之內部組態對應於圖1A至圖1G中所展示之內部組態。參考圖4B,由於在三重基板2上形成LED晶片3,及自三重基板2之兩側提取電解電鍍層5,作為實例,假定在圖3之下表面中提供兩個電極。
在本實施例中,在三重基板2之外表面上之電極墊係接合至顯示裝置之面板基板20。
本實例之三重晶片10係向上發射光之一頂部發射類型。在該頂部發射類型中,由於暫時固定部分6B無需具有透明度或耐光度,所以可選擇種類繁多之材料係有利的。
此外,由於安置方法其本身係共同於第一實施例,所以將省略安置方法之描述。
在此,三重晶片10不同於圖1A至圖1G中所展示之在透過電鍍連接之電極墊中之內部連接墊。
在三重晶片10中,主配線架部分11及在其之側壁下面之邊沿部分12係平行於基板表面而突出。在邊沿部分12之上表面上並排提供電極墊3Nr、3Nb及3Ng以用於RGB色彩之負電極。在此情況下,該墊經定位使得電極之側表面之位置與邊沿部分12之突出頂表面對準。較佳係需要對準此邊緣面之位置以容易使自邊緣部分12增長之電鍍層與電極墊接觸,且接著針對該電極墊之整個表面處理電解電鍍。
此外,並非意欲排除未完全對準情況,但是電極之邊緣面可定位為自該邊沿部分之突出邊緣面更接近於元件之主配線架,或相反地可進一步自邊沿部分12突出。
在該電極之該邊緣面係定位為自該邊沿部分之該突出邊緣面更接近該元件之該主配線架之情況下,電解電鍍層22之厚度較佳可設定為大於介於邊沿部分12之該邊緣面與各電極墊3N及3P之頂表面之間的距離。
此外,本實施例例示以下情況:P電極3P及N電極3N之各邊緣面係自金屬佈線層4沿向上方向定位並幾乎垂直於金屬佈線層4而分開。
隨著電鍍層係自金屬佈線層21之上表面增長,繼高度變為等於邊沿部分12之高度之後,可獲得介於電極墊與該電鍍層之間的電連接。為此,後文亦自該電極墊處理電鍍。
以此方式,甚至當在其他部分(而非該元件之後表面)中配置該電極時,若自晶種金屬(金屬佈線層4)沿向上方向定位該電極,則可能獲得極佳穩固電連接。
圖5A至圖5G係圖解說明根據本發明之原理之一實施例之一種在基板中安置元件之方法的截面圖。
本實例之該(等)安置方法基本上共同於在第一描述實施例中所描述之方法。然而,在圖5E中,在曝光熱固性光敏性樹脂6之一部分之製程中,透過在頂側中所提供之遮罩M之路徑自頂部進行該曝光。自遮罩M之開孔傳輸通過三重晶片10之內側之光(例如,UV光)到達在該元件下面之熱固性光敏性樹脂6處,並部分曝光熱固性光敏性樹脂6。因此,在圖5F中,繼顯影之後,在曝光部分中形成暫時固定樹脂6B。
此外,在本實例中,暫時固定部分6B具有小於圖5A至圖5G之區域之一區域,但是可基於暫時固定之需要而任意判定暫時固定部分6B之該區域。
在如第三描述實施例中所討論之圖5G之電鍍製程中,電極墊與在如電鍍增長路徑中所見之相同平面上之邊沿部分12之突出邊緣面對準。為此,隨著該電鍍與其之高度增長一樣多,提供電接觸,且該電鍍係自該電極墊增長。因此,容易在介於該電極墊與該電鍍層之間的界面處形成穩固接合。
圖6係圖解說明藉由SIM攝影所拍攝之由圖5A至圖5G之一長方形所環繞之區域之一照片之一圖。
認為由在圖6中之一圓圈所環繞以獲得穩固接合之區域中呈現連續結晶種粒。
具有此一結構之三重晶片10係向上發射光之一頂部發射類型。在該頂部發射類型中,由於暫時固定部分6B無需具有透明度或耐光度,所以可選擇種類繁多之材料係有利的。此一優點係相似於該第一實施例。
此外,由於該安置方法其本身係共同於該第一實施例,所以將省略該安置方法之描述。
本實施例係關於第三描述實施例及第四描述實施例之修改。
在暫時固定部分6B之固定力量係強大的及甚至可在一更小區域中充分獲得該暫時固定之情況下,可能應用底部發射類型。
例如,如圖7A及圖7B中所展示,在如自平面圖所見之三重晶片10之四個隅角中配置光敏性樹脂6M。因此,可能獲得具有自三重晶片10之下表面之發光表面至面板基板20之一空氣層(空氣間隙)之一空隙結構。
相應地,相較於填充樹脂之情況,在介於該元件與該空氣間隙之間的一界面處及在介於該空氣間隙與玻璃基板(面板基板20)之間的界面處產生一光折射差。因此,在面板基板20內產生一光發射角度差。
具體言之,該光係在玻璃內以一40至45度角度自該玻璃突然出現至空氣,且如在圖8中所展示般完全反射具有低於一範圍之一角度之該光而致使容易產生損失。圖8圖解說明一比較實例,其中在面板基板20中直接安置三重晶片10,且不提供空氣間隙。在此一安置結構中,在該元件上形成電極作為一通孔及一佈線線路。
若不提供該空氣間隙,或內插樹脂或空氣以外之類似物,則經過面板基板20之內側之光之角度總體上變得低。相反地,若如在本實施例中提供該空氣間隙,則降低總反射光量(比率)。為此,可能實現具有一高光輸出比率及低電力消耗之一LED顯示器。
此外,在發光元件之情況下,可能提供固定該元件之一功能及耐光度兩者。為此,若繼固定該元件之後顯影及移除光照地方處之樹脂,則在該固定樹脂中無需耐光度,且可進行電連接,同時維持該空隙。在建置類型中,由於由相對絕緣膜埋藏空隙結構,所以難以獲得此一結構。
甚至在此情況下,P電極3P及N電極3N之各邊緣面係自金屬佈線層21沿向上方向定位且幾乎垂直於金屬佈線層21而分開。
若在形成三重晶片1過程中,如在第一實施例中所描述,僅在三重基板2中安置LED晶片3及增長電解電鍍層5,則該電鍍經增長以攀升如圖1G中所展示之LED晶片3之邊緣面。此係因為在此一部分中有效電場增加。
在圖9A至圖9E中,更詳細展示此事實。
若針對如圖9A中所展示之一GaAs基板執行台面蝕刻或分裂,則取決於一晶體結構,該GaAs基板之邊緣面可具有一顛倒台面結構。此事實其本身係不真實的,但是亦在垂直半導體表面中產生一加速電鍍增長(攀升)。
圖9B至圖9E圖示圖解說明一增長銅進程與一晶磊基板結構之間的一關係。
在該晶磊結構中,例如,介於n-GaN層與p-GaN層之間內插用於形成多個量子井之一未摻雜多層晶磊結構,以最多具有約為200奈米之一厚度,如在對應於在圖式中之二極體之PN接面之部分中所展示。在對應於此二極體之該PN接面之該部分中存在一內建電位差(電位障壁),電解電鍍層之接觸不受影響,除非在該障壁上產生一電位差。然而,若施加超過該內建電位差之一電壓,則亦可在該n-GaN層中處理電鍍增長,如圖9E中所展示。接著,劣化二極體特性,且最終該二極體變為一實質短路電阻。
除此之外,若甚至當不施加超過該內建電位差之一電壓時如圖9C至圖9D中所展示般使該電鍍加厚,則可透過電鍍膜使p-GaN及n-GaN短路。
在本修改實例中,為了防止此一現象,較佳形成半導體LED晶片,使得該PN接面之內建電位等於或高於在電解電鍍期間施加於金屬佈線層4及電解溶液之該電壓(例如,0.5伏至1伏)。
替代地,為了避免接觸,較佳藉由使用一種在雷射二極體之分裂表面中塗邊緣面之方法而預先在該邊緣面中形成一薄絕緣膜。
可能藉由選擇前文所提及之方法之至少一者而防止二極體特性之劣化。此外,由於藉由應用本發明可如上文所描述般減小該電解電鍍之厚度,所以電鍍該邊緣面之該溶液並非係必要的。
將描述適合在各種前文所提及之實施例中之後曝光之一曝光系統。此一曝光系統係依根據前文所提及之實施例之方法而應用於該後曝光。
典型地,圖10中所展示之曝光系統100係與面板傳遞裝置整合。參考圖10,在大規模LED顯示器之傳遞路徑中間中提供線狀曝光裝置102。該傳遞裝置包含藉由控制速度而軸向旋轉之一傳遞輥101,及使用與LED顯示面板P之後表面接觸之傳遞輥101來傳遞該LED顯示面板P。
為此,當LED顯示面板P在傳遞當中經過線狀曝光裝置102時,使用一線掃描方法而自該後表面曝光LED顯示面板P。
此外,可在線狀曝光裝置102上提供一控制輥以允許以較精細間隙進行饋送。
當該曝光之解析度無需高時或當一分開遮罩並非必需時,此曝光係適當的,此係因為使用佈線線路或類似物作為一自對準遮罩。
此外,在元件係在LED顯示面板P之表面側中發射光之情況下,可僅在該元件之後表面中固持該元件。因此,可能防止當洩漏光入射至固持樹脂時所導致之光劣化。
此外,藉由執行後曝光,無需一大規模昂貴曝光裝置。
此外,若此一曝光裝置具有一視覺上透明的基板,則該曝光裝置可應用於裝置(而非顯示器)。
熟習此項技術者應瞭解取決於設計需求及其他因素,可發生各種修改、組合、子組合及替代,只要該等修改、組合、子組合及替代係在隨附申請專利範圍或其等之等效物之範疇之內。
1...三重晶片
1A...三重晶片
2...三重基板
3...液晶顯示器(LED)晶片
3N...N電極
3P...P電極
3Nb...電極墊
3Ng...電極墊
3Nr...電極墊
4...金屬佈線層
4L...金屬佈線層
4R...金屬佈線層
5...電解電鍍層
6...熱固性光敏性樹脂
6A...可光固化區域
6B...暫時固定部分
10...三重晶片
11...主配線架部分
12...邊沿部分
20...面板基板
21...金屬佈線層
22...電解電鍍層
31...作用層
32...內部P電極
33...內部N電極
100...曝光系統
101...傳遞輥
102...線狀曝光裝置
圖1A至圖1G係圖解說明根據本發明之原理之一種在一基板中安置元件之方法之橫截面圖;
圖2係圖解說明根據本發明之原理之介於金屬佈線層與P電極之間的一連接之一外觀之一圖;
圖3係圖解說明根據本發明之原理之三重晶片之一結構圖;
圖4A及圖4B分別係圖解說明根據本發明之原理之三重晶片之一平面圖及圖解說明繼安置該三重晶片之後之一面板基板之一橫截面結構圖;
圖5A至圖5G係圖解說明根據本發明之原理之一種在一基板中安置元件之方法之橫截面圖;
圖6係圖解說明根據本發明之原理之藉由SIM攝影所拍攝之由圖5A至圖5G之一長方形所環繞之區域之一照片之一圖;
圖7A及圖7B分別係圖解說明根據本發明之原理之該三重晶片之一平面圖及圖解說明繼安置該三重晶片之後之一面板基板之一橫截面結構圖;
圖8係圖解說明比較實例之一橫截面圖,其中在無任何空氣間隙之三重基板上直接安置三重晶片;
圖9A至圖9E係圖解說明根據本發明之原理之在半導體之晶片邊緣面上之晶磊結構與攀升電鍍增長之一關係之圖;及
圖10係圖解說明根據本發明之原理之一傳遞曝光系統之一示意圖。
1...三重晶片
2...三重基板
3...液晶顯示器(LED)晶片
3N...N電極
3P...P電極
4...金屬佈線層
4L...金屬佈線層
4R...金屬佈線層
5...電解電鍍層
6...熱固性光敏性樹脂
6A...可光固化區域
6B...暫時固定部分
Claims (8)
- 一種總成,其包括:一基板;一金屬佈線層,其係在該基板上,在該金屬佈線層中具有一開孔;一熱固性樹脂層部分,其係在該基板之至少一部分上,該熱固性樹脂層覆蓋該金屬佈線層之該開孔;一元件,其(i)係在該熱固性樹脂層部分上,(ii)係定位於該金屬佈線層之該開孔上及(iii)經由該熱固性樹脂層部分而固定於該基板;及一電鍍層,其在該金屬佈線上且圍繞該元件及部分地嵌入該元件於該電鍍層之一部分中,該電鍍層之該部分自該電鍍層之一平面的上表面向上延伸,該電鍍層之該平面的上表面係藉由該向上延伸之該電鍍層之該部分而與該元件分開,該電鍍層有效地電互連該佈線層與該元件。
- 如請求項1之總成,其中該熱固性樹脂層部分係經固化。
- 如請求項2之總成,其進一步包含一第二經固化熱固性樹脂層部分,其未由該元件所覆蓋。
- 如請求項3之總成,其中該第二經固化熱固性樹脂層部分圍繞該元件而延伸。
- 一種電子裝置總成,該總成包括:一基板; 一金屬佈線層,其係在該基板上,在該金屬佈線層中具有一開孔;一熱固性樹脂層部分,其係在該基板之至少一部分上,該熱固性樹脂層部分覆蓋該金屬佈線層之該開孔;及一元件,其(i)係在該熱固性樹脂層部分上,(ii)係定位於該金屬佈線層之該開孔上及(iii)經由該熱固性樹脂層部分而固定於該基板;及一電鍍層,其在該金屬佈線上且圍繞該元件及部分地嵌入該元件於該電鍍層之一部分中,該電鍍層之該部分自該電鍍層之一平面的上表面向上延伸,該電鍍層之該平面的上表面係藉由該向上延伸之該電鍍層之該部分而與該元件分開。
- 如請求項5之總成,其中該熱固性樹脂層部分係經固化。
- 如請求項6之總成,其進一步包含一第二經固化熱固性樹脂部分,其未由該元件所覆蓋。
- 如請求項7之總成,其中該第二經固化熱固性樹脂部分圍繞該元件而延伸。
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Families Citing this family (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014013818A (ja) * | 2012-07-04 | 2014-01-23 | Sony Corp | デバイスおよび電子装置 |
WO2015053356A1 (ja) * | 2013-10-09 | 2015-04-16 | 学校法人早稲田大学 | 電極接続方法及び電極接続構造 |
JP6152816B2 (ja) * | 2014-03-26 | 2017-06-28 | ソニー株式会社 | 半導体デバイス、表示パネル、表示装置、電子装置、および、半導体デバイスの製造方法 |
GB2524791B (en) | 2014-04-02 | 2018-10-03 | At & S Austria Tech & Systemtechnik Ag | Placement of component in circuit board intermediate product by flowable adhesive layer on carrier substrate |
JP6328497B2 (ja) | 2014-06-17 | 2018-05-23 | ソニーセミコンダクタソリューションズ株式会社 | 半導体発光素子、パッケージ素子、および発光パネル装置 |
US9437782B2 (en) * | 2014-06-18 | 2016-09-06 | X-Celeprint Limited | Micro assembled LED displays and lighting elements |
US10446728B2 (en) | 2014-10-31 | 2019-10-15 | eLux, Inc. | Pick-and remove system and method for emissive display repair |
US10381332B2 (en) | 2014-10-31 | 2019-08-13 | eLux Inc. | Fabrication method for emissive display with light management system |
US10535640B2 (en) | 2014-10-31 | 2020-01-14 | eLux Inc. | System and method for the fluidic assembly of micro-LEDs utilizing negative pressure |
US10319878B2 (en) | 2014-10-31 | 2019-06-11 | eLux, Inc. | Stratified quantum dot phosphor structure |
US10381335B2 (en) | 2014-10-31 | 2019-08-13 | ehux, Inc. | Hybrid display using inorganic micro light emitting diodes (uLEDs) and organic LEDs (OLEDs) |
US10543486B2 (en) | 2014-10-31 | 2020-01-28 | eLux Inc. | Microperturbation assembly system and method |
US10520769B2 (en) | 2014-10-31 | 2019-12-31 | eLux, Inc. | Emissive display with printed light modification structures |
US10418527B2 (en) | 2014-10-31 | 2019-09-17 | eLux, Inc. | System and method for the fluidic assembly of emissive displays |
US10236279B2 (en) | 2014-10-31 | 2019-03-19 | eLux, Inc. | Emissive display with light management system |
US9825202B2 (en) | 2014-10-31 | 2017-11-21 | eLux, Inc. | Display with surface mount emissive elements |
US10242977B2 (en) | 2014-10-31 | 2019-03-26 | eLux, Inc. | Fluid-suspended microcomponent harvest, distribution, and reclamation |
JP6786781B2 (ja) * | 2015-09-25 | 2020-11-18 | 日亜化学工業株式会社 | 発光装置の製造方法 |
JP2017183458A (ja) | 2016-03-30 | 2017-10-05 | ソニー株式会社 | 発光素子組立体及びその製造方法、並びに、表示装置 |
CN108307591A (zh) * | 2017-01-13 | 2018-07-20 | 奥特斯奥地利科技与系统技术有限公司 | 通过在安装于部件承载件材料之前用附着物覆盖部件制造的部件承载件 |
KR102605339B1 (ko) * | 2018-07-18 | 2023-11-27 | 삼성디스플레이 주식회사 | 표시 장치 및 표시 장치 제조 방법 |
KR102116393B1 (ko) * | 2019-02-27 | 2020-05-28 | (주) 글로우원 | 양면 전극을 구비한 투명 led 디스플레이 |
WO2021111279A1 (en) * | 2019-12-04 | 2021-06-10 | 3M Innovative Properties Company | Circuits including micropatterns and using partial curing to adhere dies |
DE112020006322T5 (de) * | 2019-12-24 | 2022-10-06 | Nichia Corporation | Verfahren zur herstellung einer lichtemittierenden vorrichtung undlichtemittierende vorrichtung |
TWI738433B (zh) * | 2020-01-09 | 2021-09-01 | 致伸科技股份有限公司 | 光源模組以及具有光源模組的電子裝置 |
JP7007607B2 (ja) * | 2020-04-16 | 2022-01-24 | 日亜化学工業株式会社 | 発光装置の製造方法 |
JPWO2022054943A1 (zh) | 2020-09-14 | 2022-03-17 | ||
JP7398036B2 (ja) | 2021-06-23 | 2023-12-14 | 日亜化学工業株式会社 | 発光モジュール及びその製造方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5071787A (en) * | 1989-03-14 | 1991-12-10 | Kabushiki Kaisha Toshiba | Semiconductor device utilizing a face-down bonding and a method for manufacturing the same |
JPH07183304A (ja) * | 1993-12-22 | 1995-07-21 | Toshiba Corp | 半導体装置の製造方法 |
US6981317B1 (en) * | 1996-12-27 | 2006-01-03 | Matsushita Electric Industrial Co., Ltd. | Method and device for mounting electronic component on circuit board |
US20080038855A1 (en) * | 2003-03-14 | 2008-02-14 | Sony Corporation | Light-emitting device, light-emitting apparatus, image display apparatus, method of manufacturing light-emitting device, and method of manufacturing image display apparatus |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55156482U (zh) * | 1979-04-26 | 1980-11-11 | ||
US5151776A (en) * | 1989-03-28 | 1992-09-29 | General Electric Company | Die attachment method for use in high density interconnected assemblies |
US5089440A (en) * | 1990-03-14 | 1992-02-18 | International Business Machines Corporation | Solder interconnection structure and process for making |
DE4126913A1 (de) * | 1991-08-14 | 1993-02-18 | Siemens Ag | Verfahren zum beloten und montieren von leiterplatten mit bauelementen |
DE69325065T2 (de) * | 1992-10-02 | 1999-10-28 | Matsushita Electric Ind Co Ltd | Halbleitervorrichtung, Bildabtastvorrichtung und Verfahren zu ihrer Herstellung |
JP2561039B2 (ja) * | 1994-11-22 | 1996-12-04 | 日本電気株式会社 | 半導体チップおよび回路基板の接続方法 |
JPH0917913A (ja) * | 1995-06-29 | 1997-01-17 | Toshiba Corp | 電子回路装置 |
JP2806348B2 (ja) * | 1996-03-08 | 1998-09-30 | 日本電気株式会社 | 半導体素子の実装構造及びその製造方法 |
JP3685585B2 (ja) * | 1996-08-20 | 2005-08-17 | 三星電子株式会社 | 半導体のパッケージ構造 |
WO2000002243A1 (fr) * | 1998-07-01 | 2000-01-13 | Seiko Epson Corporation | Dispositif a semi-conducteur, procede de fabrication associe, carte imprimee et dispositif electronique |
US6445589B2 (en) * | 1999-07-29 | 2002-09-03 | Delphi Technologies, Inc. | Method of extending life expectancy of surface mount components |
DE10164494B9 (de) * | 2001-12-28 | 2014-08-21 | Epcos Ag | Verkapseltes Bauelement mit geringer Bauhöhe sowie Verfahren zur Herstellung |
US6873529B2 (en) * | 2002-02-26 | 2005-03-29 | Kyocera Corporation | High frequency module |
TWI245597B (en) * | 2003-06-30 | 2005-12-11 | Siliconware Precision Industries Co Ltd | Printed circuit boards and method for fabricating the same |
JP2005311109A (ja) * | 2004-04-22 | 2005-11-04 | Seiko Epson Corp | 光デバイスの実装方法及び光モジュール |
TWI243462B (en) * | 2004-05-14 | 2005-11-11 | Advanced Semiconductor Eng | Semiconductor package including passive component |
TWI243440B (en) * | 2004-09-07 | 2005-11-11 | Siliconware Precision Industries Co Ltd | Nickel/gold pad structure of semiconductor package and fabrication method thereof |
JP4356581B2 (ja) * | 2004-10-12 | 2009-11-04 | パナソニック株式会社 | 電子部品実装方法 |
JP2008124376A (ja) * | 2006-11-15 | 2008-05-29 | Canon Inc | 素子基板の接続方法 |
US8318595B2 (en) * | 2009-11-24 | 2012-11-27 | The United States Of America As Represented By The Secretary Of The Army | Self-assembled electrical contacts |
-
2010
- 2010-04-28 JP JP2010103142A patent/JP5533199B2/ja active Active
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Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5071787A (en) * | 1989-03-14 | 1991-12-10 | Kabushiki Kaisha Toshiba | Semiconductor device utilizing a face-down bonding and a method for manufacturing the same |
JPH07183304A (ja) * | 1993-12-22 | 1995-07-21 | Toshiba Corp | 半導体装置の製造方法 |
US6981317B1 (en) * | 1996-12-27 | 2006-01-03 | Matsushita Electric Industrial Co., Ltd. | Method and device for mounting electronic component on circuit board |
US20080038855A1 (en) * | 2003-03-14 | 2008-02-14 | Sony Corporation | Light-emitting device, light-emitting apparatus, image display apparatus, method of manufacturing light-emitting device, and method of manufacturing image display apparatus |
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JP2011233733A (ja) | 2011-11-17 |
CN102237478A (zh) | 2011-11-09 |
CN102237478B (zh) | 2016-08-03 |
US20110266039A1 (en) | 2011-11-03 |
KR101839144B1 (ko) | 2018-03-15 |
KR20110120218A (ko) | 2011-11-03 |
CN105977232A (zh) | 2016-09-28 |
US9119332B2 (en) | 2015-08-25 |
TW201212304A (en) | 2012-03-16 |
CN105977232B (zh) | 2019-05-10 |
JP5533199B2 (ja) | 2014-06-25 |
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