WO2021196008A1 - 无机发光二极管芯片及其制造方法 - Google Patents

无机发光二极管芯片及其制造方法 Download PDF

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Publication number
WO2021196008A1
WO2021196008A1 PCT/CN2020/082558 CN2020082558W WO2021196008A1 WO 2021196008 A1 WO2021196008 A1 WO 2021196008A1 CN 2020082558 W CN2020082558 W CN 2020082558W WO 2021196008 A1 WO2021196008 A1 WO 2021196008A1
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Prior art keywords
layer
emitting diode
diode chip
inorganic light
epitaxial layer
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PCT/CN2020/082558
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English (en)
French (fr)
Inventor
马俊杰
卢元达
杨山伟
岂林霞
熊志军
翟明
孙海威
Original Assignee
京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202080000439.8A priority Critical patent/CN113767480A/zh
Priority to PCT/CN2020/082558 priority patent/WO2021196008A1/zh
Publication of WO2021196008A1 publication Critical patent/WO2021196008A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Definitions

  • the present disclosure relates to the field of display technology, and in particular to an inorganic light-emitting diode chip mother chip, an inorganic light-emitting diode chip and a manufacturing method thereof, and a light-emitting diode light-emitting device.
  • Mini LED mini Organic Light-Emitting Diode, sub-millimeter light-emitting diode
  • micro LED micro Organic Light-Emitting Diode
  • a mother chip of an inorganic light emitting diode chip which includes an epitaxial layer, a plurality of spacers, and a supporting and reinforcing layer.
  • the two opposite sides of the epitaxial layer are respectively a first side and a second side; a plurality of pads are arranged on the first side of the epitaxial layer; the supporting and reinforcing layer is filled in among the plurality of pads The gap between.
  • the ratio of the thickness of the epitaxial layer to the thickness of the liner ranges from 1:6 to 1:2.
  • the thickness of at least one liner is 20 ⁇ m to 30 ⁇ m.
  • the material of each liner includes at least one of copper, aluminum, and copper-aluminum alloy.
  • each liner includes a liner main body, and a protective layer covering the sidewall of the liner main body and the surface away from the epitaxial layer; the protective layer is conductive.
  • the material of the liner body includes at least one of copper, aluminum, and copper-aluminum alloy, and the material of the protective layer includes nickel and gold.
  • the thickness of the supporting and reinforcing layer is 20 ⁇ m to 30 ⁇ m.
  • the surface of the support and reinforcement layer away from the epitaxial layer is flush with the surface of the plurality of pads away from the epitaxial layer.
  • the surface of the support and reinforcement layer away from the epitaxial layer is lower than the surface of the plurality of pads away from the epitaxial layer.
  • the material of the support and reinforcement layer includes a cured glue-like material.
  • the material of the supporting and reinforcing layer includes silica gel, epoxy resin, or photoresist.
  • the supporting and reinforcing layer is white or black.
  • the material of the support and reinforcement layer when the support and reinforcement layer is white, the material of the support and reinforcement layer includes titanium dioxide. When the supporting and reinforcing layer is black, the material of the supporting and reinforcing layer includes carbon powder.
  • the surface of the first side of the epitaxial layer has a plurality of protrusions, and the plurality of protrusions are embedded in the supporting and reinforcing layer.
  • the thickness of the epitaxial layer is 5 ⁇ m-10 ⁇ m.
  • the inorganic light emitting diode chip mother sheet has a plurality of inorganic light emitting diode chip regions; the plurality of pads includes a plurality of first pads and a plurality of second pads.
  • the epitaxial layer includes a plurality of epitaxial layer units, and each inorganic light emitting diode chip area is provided with an epitaxial layer unit, a first liner, and a second liner.
  • the epitaxial layer unit includes: a first semiconductor layer, a light emitting layer, a second semiconductor layer, and a flat layer.
  • the first semiconductor layer includes a first part and a second part
  • the light-emitting layer is arranged on the side of the first part of the first semiconductor layer
  • the second semiconductor layer is arranged on the side of the light-emitting layer away from the first semiconductor layer
  • the flat layer covers the side of the second semiconductor layer away from the light emitting layer.
  • the flat layer has a first through hole and a second through hole, and in each region of the inorganic light emitting diode chip, the first pad is coupled to the first semiconductor layer through the first through hole, The second pad is coupled to the second semiconductor layer through the second through hole.
  • the epitaxial layer unit further includes: a first contact electrode, an insulating layer, a conductive layer, and a second contact electrode.
  • the first contact electrode is arranged between the second part of the first semiconductor layer and the flat layer; the first contact electrode is in electrical contact with the second part of the first semiconductor layer, and the first The gasket is coupled to the first contact electrode through the first through hole.
  • the insulating layer is disposed between the second semiconductor layer and the flat layer.
  • the conductive layer is disposed between the insulating layer and the flat layer, and the conductive layer is in electrical contact with the second semiconductor layer.
  • the second contact electrode is disposed between the conductive layer and the flat layer; the second contact electrode is in electrical contact with the conductive layer, and the second pad is connected to the second through hole through the second through hole.
  • the contact electrode is coupled; and, the orthographic projection of the second contact electrode on the first semiconductor layer and the orthographic projection of the insulating layer on the first semiconductor layer at least partially overlap.
  • an inorganic light-emitting diode chip which is obtained from the above-mentioned inorganic light-emitting diode chip mother chip through a slicing process, and the inorganic light-emitting diode chip includes: an epitaxial layer unit, and The first liner and the second liner on one side of the epitaxial layer unit, and a support reinforcement unit, the support reinforcement unit fills the periphery of the first liner and the periphery of the second liner.
  • the thickness of the first liner and the second liner is 20 ⁇ m-30 ⁇ m; the thickness of the supporting and reinforcing unit is 20 ⁇ m-30 ⁇ m.
  • a method for manufacturing an inorganic light-emitting diode chip includes: providing a substrate, and forming an epitaxial layer on one side of the substrate; Pad; forming a supporting and reinforcing layer in the gap between the plurality of pads; peeling the substrate from the epitaxial layer to obtain an inorganic light-emitting diode chip mother sheet.
  • the forming a supporting and reinforcing layer in the gaps between the plurality of liners includes: forming a support and reinforcement layer on the side of the epitaxial layer where the plurality of liners are formed by using an injection molding process or a lamination process. Supporting and reinforcing film; using a grinding process to remove the part of the supporting and reinforcing film covering the surface of the plurality of pads away from the epitaxial layer, so that the surface of the plurality of pads away from the epitaxial layer is exposed.
  • the forming a supporting and reinforcing layer in the gaps between the plurality of pads includes: using a photoresist material, forming a supporting and reinforcing film on the side of the epitaxial layer where the plurality of pads are formed ; Pattern the support and reinforcement film, remove the part of the support and reinforcement film that covers the surface of the plurality of pads away from the epitaxial layer, so that the surface of the plurality of pads away from the epitaxial layer is exposed.
  • the method for manufacturing an inorganic light-emitting diode chip further includes: after the substrate is peeled from the epitaxial layer to obtain an inorganic light-emitting diode chip mother sheet, the inorganic light-emitting diode chip mother sheet Dividing into a plurality of inorganic light emitting diode chips; performing spot measurement on the plurality of inorganic light emitting diode chips respectively, and sorting the plurality of inorganic light emitting diode chips according to the spot measurement results.
  • a light-emitting diode light-emitting device which includes: an array substrate and a plurality of inorganic light-emitting diode chips as described above arranged on the array substrate.
  • FIG. 1 is a structural diagram of an inorganic light emitting diode chip according to some embodiments in the related art
  • FIG. 2 is another structural diagram of an inorganic light emitting diode chip according to some embodiments in the related art
  • 3A is a structural diagram of a light-emitting diode light-emitting device according to some embodiments of the present disclosure
  • 3B is a comparison diagram of light emission patterns of inorganic light emitting diode chips according to some embodiments.
  • Fig. 4 is a cross-sectional view taken according to the section line AA' in Fig. 3A.
  • 5A is a structural diagram of an inorganic light-emitting diode chip mother chip according to some embodiments of the present disclosure
  • 5B is another structural diagram of an inorganic light emitting diode chip mother chip according to some embodiments of the present disclosure.
  • 6A is a structural diagram of a first semiconductor layer of an epitaxial layer unit in an inorganic light emitting diode chip according to some embodiments of the present disclosure
  • 6B is a structural diagram of an epitaxial layer unit in an inorganic light emitting diode chip according to some embodiments of the present disclosure
  • FIG. 7 is a structural diagram of an inorganic light emitting diode chip according to some embodiments of the present disclosure.
  • FIGS. 8A to 8G are diagrams showing steps of a method for manufacturing an inorganic light emitting diode chip according to some embodiments of the present disclosure
  • FIGS. 9A to 9G are diagrams of another step of a method for manufacturing an inorganic light emitting diode chip according to some embodiments of the present disclosure.
  • FIG. 10 is a flowchart of a method for manufacturing an inorganic light emitting diode chip according to some embodiments of the present disclosure
  • FIG. 11A is another flowchart of a method for manufacturing an inorganic light emitting diode chip according to some embodiments of the present disclosure
  • FIG. 11B is another flow chart of the method for manufacturing an inorganic light emitting diode chip according to some embodiments of the present disclosure.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, “plurality” means two or more.
  • the expressions “coupled” and “connected” and their extensions may be used.
  • the term “connected” may be used when describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other.
  • the term “coupled” may be used when describing some embodiments to indicate that two or more components have direct physical or electrical contact.
  • At least one of A, B, and C has the same meaning as “at least one of A, B, or C", and both include the following combinations of A, B, and C: only A, only B, only C, A and B The combination of A and C, the combination of B and C, and the combination of A, B and C.
  • the light-emitting diode light-emitting device includes an array substrate and a plurality of inorganic light-emitting diode chips arranged on the array substrate. A plurality of inorganic light-emitting diode chips are coupled with a signal source on the array substrate, and emit light under the action of the signal source.
  • the light-emitting diode light-emitting device is a light-emitting diode display device, such as a mini LED display device or a micro LED display device, including a plurality of inorganic light-emitting diode chips, which may specifically be secondary Millimeter inorganic light emitting diode chip (mini LED chip) or micro inorganic light emitting diode chip (micro LED chip).
  • the light-emitting diode display device 30 includes an array substrate 20 and a plurality of inorganic light-emitting diode chips 10 arranged on one side of the array substrate 20.
  • the plurality of inorganic light-emitting diode chips 10 have high density, large number, and small spacing, which can reduce the display size.
  • the pixel pitch of the device improves the resolution, so that the display device has a better display effect.
  • a fence 5 surrounding the inorganic light emitting diode chip 10 and having a certain height is prepared around each inorganic light emitting diode chip 10, such as the fence 5 It is a square shape, and the light type of the light emitted by the inorganic light emitting diode chip 10 can be adjusted by controlling the height of the wall 5, the distance between the wall 5 and the inorganic light emitting diode chip 10, and the inclination angle of each side wall of the wall.
  • the inventors simulated the light pattern of a single inorganic light-emitting diode chip.
  • the inorganic light-emitting diode chip used is the inorganic light-emitting diode chip 10' shown in Figure 1), on the positive side of the light-emitting side of the inorganic light-emitting diode chip In the viewing angle direction, the intensity of the light emitted by the inorganic light-emitting diode chip is low, and the brightness of the light measured at various angles on the light-emitting side of the inorganic light-emitting diode chip is generally low, and the emitted light is relatively scattered.
  • the inorganic light-emitting diode chip used is the inorganic light-emitting diode chip 10 shown in FIG. 7
  • the light emitted by the inorganic light-emitting diode chip is relatively concentrated, and the light-emitting side of the inorganic light-emitting diode chip In the direction of the front viewing angle, the intensity of the light emitted by the inorganic light-emitting diode chip is the highest. It can be seen that if the optical structure is provided in the mini LED display device, the front viewing angle direction of the mini LED display device has the highest brightness during display, so that the display effect of the display device is good.
  • forward viewing angle directions mentioned in the present disclosure all refer to the position on the normal line of the plane where the inorganic light emitting diode chip (or display device) is located, and the normal line passes through the inorganic light emitting diode chip (or display device). Geometric center.
  • the optical structure can achieve the effect of adjusting the light type and improving the viewing angle of the display.
  • the height of the above-mentioned optical structure is not greater than 50 ⁇ m; in order to achieve a better dimming effect and to facilitate the production of the optical structure, the thickness of the inorganic light emitting diode chip 10 should be less than the height of the optical structure.
  • the inorganic light emitting diode chip 10' includes an epitaxial layer 2, and a first pad 31 and a second pad 32 disposed on one side of the epitaxial layer 2, wherein the epitaxial layer 2 Including multiple thin film layers such as a light-emitting layer, an N-type semiconductor layer, and a P-type semiconductor layer.
  • the first pad 31 and the second pad 32 are respectively coupled to the N-type semiconductor layer and the P-type semiconductor layer in the epitaxial layer 2.
  • the first pad 31 and the second pad 32 are used for coupling with an external signal source. By applying a voltage to the first pad 31 and the second pad 32, the inorganic light emitting diode chip 10' can emit light.
  • a method for preparing an inorganic light-emitting diode chip is as follows: an epitaxial layer and a plurality of pads are sequentially prepared on a substrate, and the substrate is thinned to a desired thickness through a grinding process to obtain an inorganic light-emitting diode chip mother. Then, the mother chip of the inorganic light-emitting diode chip is divided to obtain a plurality of inorganic light-emitting diode chips, and the structure of the obtained inorganic light-emitting diode chip 10' is shown in FIG.
  • the inorganic light-emitting diode chip mother wafer can be reduced from 700 ⁇ m to 800 ⁇ m to 80 ⁇ m. If the substrate continues to be ground, the entire substrate may be broken, resulting in Severe yield loss.
  • the substrate such as the sapphire substrate
  • the substrate has a lattice structure
  • the inorganic light-emitting diode chip mother chip is divided into a plurality of inorganic light-emitting diode chips by the split process, the substrate will crack along a specific direction in its lattice structure As a result, the obtained inorganic light-emitting diode chip 10' is irregular and has oblique edges.
  • the light-emitting type of the inorganic light-emitting diode chip 10' will be asymmetrical with respect to the front viewing angle direction of the chip (as shown in Figure 4).
  • the thickness d1 of the inorganic light-emitting diode chip 10' with the substrate 1 is at least 80 ⁇ m, which is greater than the maximum height (50 ⁇ m) of the above-mentioned optical structure, the optical structure is difficult to fabricate, and the inorganic light-emitting diode cannot be effectively improved.
  • the light-emitting type of the chip since the thickness d1 of the inorganic light-emitting diode chip 10' with the substrate 1 is at least 80 ⁇ m, which is greater than the maximum height (50 ⁇ m) of the above-mentioned optical structure, the optical structure is difficult to fabricate, and the inorganic light-emitting diode cannot be effectively improved.
  • the light-emitting type of the chip since the thickness d1
  • Another method for preparing the inorganic light-emitting diode chip is: after the epitaxial layer and a plurality of spacers are sequentially prepared on the substrate, the substrate is peeled from the epitaxial layer to obtain an inorganic light-emitting diode chip mother chip, and then the inorganic light-emitting diode chip The mother chip is divided to obtain a plurality of inorganic light-emitting diode chips, and the structure of the obtained inorganic light-emitting diode chip 10 ′ is shown in FIG. 2.
  • the inorganic light-emitting diode chip prepared by this method only includes an epitaxial layer and a liner, and because the epitaxial layer has poor toughness, it is easy to break under stress.
  • the epitaxial layer of the inorganic light-emitting diode chip cannot withstand the force exerted by the positive and negative probes during the spot measurement. Fracture occurs during spot measurement, and the epitaxial layer of the inorganic light-emitting diode chip is also difficult to withstand the force during transfer (for example, the inorganic light-emitting diode chip is transferred to the array substrate), which increases the difficulty of transferring the inorganic light-emitting diode chip.
  • the preparation method of the inorganic light-emitting diode chip in the related art and the prepared inorganic light-emitting diode chip 10' have the following problems.
  • the prepared inorganic light-emitting diode chip 10' has the substrate 1
  • the inorganic light-emitting diode chip 10' The thickness of the light-emitting diode chip 10' is relatively thick, which is not conducive to the manufacture of the optical structure, and the light-emitting type is asymmetrical.
  • the prepared inorganic light emitting diode chip 10' does not have a substrate, the inorganic light emitting diode chip 10' is too fragile to be spot-measured and transferred, and is difficult to be applied to display products.
  • some embodiments of the present disclosure provide an inorganic light emitting diode chip mother substrate 20, including: an epitaxial layer 2, a plurality of spacers 3, and a supporting and reinforcing layer 4.
  • the two opposite sides of the epitaxial layer 2 are the first side B1 and the second side B2, respectively, a plurality of spacers 3 are arranged on the first side B1 of the epitaxial layer 2, and the supporting and reinforcing layer 4 is filled in the plurality of spacers.
  • the above-mentioned inorganic light emitting diode chip mother substrate 20 is divided to obtain a plurality of inorganic light emitting diode chips 10.
  • the inorganic light emitting diode chip mother substrate 20 is divided into a plurality of inorganic light emitting diode chip regions Q, and the plurality of pads 3 include a plurality of first pads 31 and a plurality of The second liner 32.
  • the epitaxial layer 2 includes a plurality of epitaxial layer units 2a, and the support and reinforcement layer 4 includes a plurality of support and reinforcement units 4a.
  • Each inorganic light emitting diode chip area Q is provided with an epitaxial layer unit 2 a, a supporting and reinforcing unit 4 a, a first pad 31 and a second pad 32.
  • some embodiments of the present disclosure also provide an inorganic light-emitting diode chip 10, which is obtained by dividing the above-mentioned inorganic light-emitting diode chip mother substrate 20, and the inorganic light-emitting diode chip 10 includes: The layer unit 2a, the first pad 31, the second pad 32, and the support reinforcement unit 4a. Among them, the first pad 31 and the second pad 32 are arranged on one side of the epitaxial layer unit 2 a, and the supporting and reinforcing unit 4 a is filled around the first pad 31 and the second pad 32.
  • the inorganic light emitting diode chip mother sheet 20 provided by some embodiments of the present disclosure does not include a substrate.
  • the strength of the inorganic light emitting diode chip mother sheet 20 can be enhanced.
  • the epitaxial layer 2 is not prone to fracture or damage due to stress, and compared with the inorganic light emitting diode chip mother chip including the substrate in the related art, the thickness of the inorganic light emitting diode chip mother chip 20 provided in the present disclosure is thinner.
  • the inorganic light-emitting diode chip 10 obtained by dividing the inorganic light-emitting diode chip mother 20 will not have the problem of irregular surroundings, and has the advantages of thinner thickness and higher strength, and can withstand the process of spot measurement.
  • the thickness of the inorganic light-emitting diode chip 10 is thin, which reduces the difficulty of manufacturing the optical structure, and can make the optical structure
  • the height of is greater than the thickness of the inorganic light-emitting diode chip 10, so that the dimming effect of the light emitted by the inorganic light-emitting diode chip 10 is better.
  • the inorganic light-emitting diode chip mother sheet 20 provided by the embodiments of the present disclosure does not include a substrate, the strength of the inorganic light-emitting diode chip mother sheet 20 is enhanced to make it It is not easy to break, and the supporting and reinforcing layer 4 filling the gaps between the plurality of pads 3 needs to have a certain thickness, so that the inorganic light emitting diode chip mother sheet 20 is not too thin or too fragile.
  • the plurality of pads The pad 3 also needs to have a certain thickness to ensure that the surface of the plurality of pads 3 away from the epitaxial layer 2 can be exposed, and the plurality of pads 3 cannot be too thick to make the total thickness of the inorganic light emitting diode chip mother 20 too thick.
  • the thickness d2 of the at least one spacer 3 is 20 ⁇ m to 30 ⁇ m.
  • the thickness of the spacer 3 can be matched with the thickness of the support and reinforcement layer 4, so that the total thickness of the inorganic light-emitting diode chip mother 20 can be controlled within Within a reasonable range, an inorganic light-emitting diode chip 10 with a moderate thickness and a certain strength can be obtained.
  • the thickness of all the spacers 3 included in the inorganic light emitting diode chip mother sheet 20 is 20 ⁇ m-30 ⁇ m, or the thickness of at least one spacer 3 is 20 ⁇ m, 25 ⁇ m, 30 ⁇ m, or the like.
  • the material of the liner 3 is selected from a material with lower cost and better conductivity, which is not limited in the present disclosure.
  • the material of each liner 3 includes at least one of copper, aluminum, and copper-aluminum alloy.
  • the material of each pad 3 is copper.
  • the material of a part of each gasket 3 is copper, and the material of the other part of the gasket 3 is copper-aluminum alloy.
  • each liner 3 includes a liner main body, and a protective layer covering the sidewall of the liner main body and the surface away from the epitaxial layer 2, and the protective layer is conductive.
  • the protective layer is coated on the surface of the main body of the liner, which can protect the main body of the liner from being oxidized or corroded by water, extending the service life of the liner 3, and the protective layer can conduct electricity, which can also play the role of electrical coupling. .
  • the material of the liner body includes at least one of copper, aluminum, and copper-aluminum alloy
  • the material of the protective layer is a conductive material with high corrosion resistance.
  • the material of the protective layer includes nickel and gold.
  • the support and reinforcement layer 4 filling the gaps between the plurality of spacers 3 needs to have a certain thickness, so that the inorganic The mother chip 20 of the light-emitting diode chip is not too thin or too fragile, and at the same time, the thickness of the support and reinforcement layer 4 cannot be too thick so that the total thickness of the mother chip 20 of the inorganic light-emitting diode chip is too thick.
  • the thickness d3 of the supporting and reinforcing layer 4 is 20 ⁇ m to 30 ⁇ m.
  • the thickness d3 of the supporting and reinforcing layer 4 is 20 ⁇ m, 25 ⁇ m, or 30 ⁇ m.
  • the surface of the supporting and reinforcing layer 4 away from the epitaxial layer 2 is flush with the surface of the plurality of pads 3 away from the epitaxial layer 2. That is to say, the thickness of the support and reinforcement layer 4 is consistent with the thickness of the liner 3.
  • the thickness of the support thick layer and the thickness of the liner 3 are both 25 ⁇ m, so that the plurality of liners 3 are far away from the epitaxial layer 2.
  • the surface of the light emitting diode chip 10 can be exposed to realize the spot measurement and sorting of the inorganic light emitting diode chip 10 or to be coupled to the signal source on the display substrate.
  • the surface of the support and reinforcement layer 4 away from the epitaxial layer 2 is lower than the surface of the plurality of pads 3 away from the epitaxial layer 2. That is to say, the thickness of the support and reinforcement layer 4 is less than the thickness of the liner 3.
  • the thickness of the support thickened layer is 25 ⁇ m, and the thickness of the liner 3 is both 30 ⁇ m.
  • the surface of the layer 2 and a part of the sidewalls can be exposed to realize the point measurement and sorting of the inorganic light emitting diode chip 10 or to be coupled to a signal source on the display substrate.
  • the material of the support and reinforcement layer 4 includes a cured glue-like material.
  • the cured adhesive material has good fluidity before curing, and can be easily filled in the gaps between the multiple gaskets 3. After filling, the cured adhesive material can be cured into a solid with higher strength, which can play a role.
  • the present disclosure does not limit the material of the support and reinforcement layer 4 as long as the material has the above-mentioned characteristics.
  • the material of the support and reinforcement layer 4 includes silica gel, epoxy resin or photoresist.
  • the support and reinforcement layer 4 is transparent, so that the light emitted by the inorganic light emitting diode chip 10 can penetrate the support and reinforcement layer 4 and can emit light on both sides of the inorganic light emitting diode chip 10.
  • the support and reinforcement layer 4 has a color, for example, the support and reinforcement layer 4 is white or black, so as to adjust the brightness of the emitted light as required.
  • the material of the supporting and reinforcing layer 4 includes titanium dioxide.
  • the material of the supporting and reinforcing layer 4 includes silica gel and titanium dioxide, and the titanium dioxide and the silica gel are mixed in a certain ratio to form a cured adhesive material.
  • the support and reinforcement layer 4 When the support and reinforcement layer 4 is white, the support and reinforcement layer 4 can play a role in reflecting light.
  • the light emitted by the epitaxial layer 2 of the inorganic light emitting diode chip 10 is reflected by the white support and reinforcement layer 4, and the brightness is enhanced.
  • the inorganic light-emitting diode chip 10 can be used in light-emitting products that need to provide high-brightness light.
  • the material of the supporting and reinforcing layer 4 when the supporting and reinforcing layer 4 is black, the material of the supporting and reinforcing layer 4 further includes carbon powder.
  • the material of the supporting and reinforcing layer 4 includes silica gel and carbon powder, and the carbon powder and the silica gel are mixed in a certain ratio to form a cured adhesive material.
  • the support and reinforcement layer 4 When the support and reinforcement layer 4 is black, the support and reinforcement layer 4 can absorb light.
  • the light emitted by the epitaxial layer unit 2a of the inorganic light emitting diode chip 10 is absorbed by the black support and reinforcement layer 4, and the brightness is reduced, thereby
  • the inorganic light emitting diode chip 10 can be used in display products that need to provide low-brightness light to increase the contrast of the display products.
  • the surface of the first side B1 of the epitaxial layer 2 has a plurality of protrusions c, and the plurality of protrusions c are embedded in the supporting and reinforcing layer 4.
  • the bonding force between the epitaxial layer 2 and the supporting and reinforcing layer 4 can be increased.
  • the epitaxial layer 2 and the supporting and reinforcing layer 4 are not easily separated.
  • the thickness d4 of the epitaxial layer 2 is 5 ⁇ m-10 ⁇ m.
  • the aforementioned epitaxial layer unit 2 a includes: a first semiconductor layer 21, a light emitting layer 22, a second semiconductor layer 23 and a flat layer 28.
  • FIG. 6B shows a top view of the epitaxial layer unit 2a without the flat layer 28, and the cross-sectional view of the epitaxial layer unit 2a in FIG. 5A and FIG. 5B and FIG. 7 is along the cross-sectional line in FIG. 6B. BB' got it.
  • the first semiconductor layer 21 includes a first portion 21a and a second portion 21b. Illustratively, as shown in FIG. 6A, the first portion 21a of the first semiconductor layer 21 surrounds the second portion 21b.
  • the light-emitting layer 22 is disposed on the side of the first portion 21 a of the first semiconductor layer 21.
  • the light-emitting layer 22 includes a quantum well superlattice layer.
  • the light-emitting layer 22 includes different materials to enable the inorganic light-emitting diode chip 10 to emit blue, green or red light.
  • the material of the light-emitting layer 22 includes aluminum indium gallium phosphide (AlGaInP), so that the inorganic light-emitting diode chip 10 can Glows red light.
  • the material of the light emitting layer 22 includes indium gallium nitride (InGaN), so that the inorganic light emitting diode chip 10 can emit blue light.
  • the material of the light-emitting layer 22 includes aluminum gallium phosphide (AlGaP), so that the inorganic light-emitting diode chip 10 can emit green light.
  • the second semiconductor layer 23 is disposed on the side of the light emitting layer 22 away from the first semiconductor layer 21.
  • the flat layer 28 covers the side of the second semiconductor layer 23 away from the light emitting layer 22.
  • the flat layer has a first through hole b1 and a second through hole b2.
  • the first pad 31 passes The first through hole b1 is coupled to the first semiconductor layer 21, and the second pad 32 is coupled to the second semiconductor layer 23 through the second through hole b2.
  • the first pad 31 is in contact with the second portion 21 b of the first semiconductor layer 21 through the first through hole b1 to achieve coupling with the first semiconductor layer 21.
  • the first semiconductor layer 21 is an N-type semiconductor layer, for example, the material of the first semiconductor layer 21 is N-type gallium nitride, and the second semiconductor layer 23 is a P-type semiconductor layer, for example, the first semiconductor layer 21 The material is P-type gallium nitride.
  • the first spacer 31 is coupled to the cathode on the array substrate
  • the second spacer 32 is coupled to the anode on the array substrate, so that the first semiconductor A current path is formed between the layer 21, the light-emitting layer 22, and the second semiconductor layer 23, so that the light-emitting layer 22 emits light under the action of current, so that the inorganic light-emitting diode chip 10 emits light.
  • the thickness of the first semiconductor layer 21 can be increased to make the thickness of the first semiconductor layer 21 Is greater than the thickness of the second semiconductor layer 23, for example, the thickness of the first semiconductor layer 21 is 2 to 5 times the thickness of the second semiconductor layer 23, for example 4 times, so that the thickness from the first pad 31 can be enhanced
  • the first semiconductor layer 21 is a P-type semiconductor layer, for example, the material of the first semiconductor layer 21 is P-type gallium nitride, and the second semiconductor layer 23 is an N-type semiconductor layer, for example, the first semiconductor layer The material of 21 is N-type gallium nitride.
  • the first spacer 31 is coupled to the anode on the array substrate
  • the second spacer 32 is coupled to the cathode on the array substrate, so that the first semiconductor A current path is formed between the layer 21, the light-emitting layer 22, and the second semiconductor layer 23, so that the light-emitting layer 22 emits light under the action of current, so that the inorganic light-emitting diode chip 10 emits light.
  • the epitaxial layer unit 2a further includes an insulating layer 24, a conductive layer 25, a first contact electrode 26, and a second contact electrode 27.
  • the first contact electrode 26 is disposed on the first semiconductor layer 21, and the first pad 31 is coupled to the first contact electrode 26 through the first through hole.
  • the first pad 31 can be better coupled to the first semiconductor layer 21, and the carrier transmission rate can be improved.
  • the insulating layer 24 is disposed between the second semiconductor layer 23 and the flat layer 28.
  • the conductive layer 25 is provided between the insulating layer 24 and the flat layer 28.
  • the conductive layer 25 is in electrical contact with the second semiconductor layer 23, that is, the conductive layer 25 covers the side of the insulating layer 24 away from the first semiconductor layer 21, and the orthographic projection of the conductive layer 25 on the first semiconductor layer 21 is larger than that of the insulating layer.
  • the orthographic projection of 24 on the first semiconductor layer 21 enables the conductive layer 25 to be coupled with the second semiconductor layer 23 to realize current transmission.
  • the conductive layer 25 is made of a material with good conductivity and strong bonding force with the second semiconductor layer 23, so that the conductive layer 25 can more effectively transmit current to the second semiconductor layer 23 .
  • the material of the conductive layer 25 is indium tin oxide (ITO).
  • the second contact electrode 27 is disposed between the conductive layer 25 and the flat layer 28; the second contact electrode 27 is in electrical contact with the conductive layer 25, and the second pad 32 is coupled to the second contact electrode 27 through the second through hole b2. Moreover, the orthographic projection of the second contact electrode 27 on the first semiconductor layer 21 and the orthographic projection of the insulating layer 24 on the first semiconductor layer 21 at least partially overlap.
  • the second contact electrode 27 includes a first portion 27a, a second portion 27b, a third portion 27c, and a fourth portion 27d, and a second portion 27b, a third portion 27c, and a fourth portion 27d.
  • the second pad 32 is connected to the second part 27b of the second contact electrode 27 through the second through hole b2. In this way, the contact area between the second contact electrode 27 and the conductive layer 25 is increased, and the contact resistance is reduced. Under the same voltage condition, a higher current density can be obtained, and the current expansion ability in the conductive layer 25 is enhanced.
  • the insulating layer 24 and the second contact electrode 17 have the same shape, and the orthographic projection of the insulating layer 24 on the first semiconductor layer 21 and the orthographic projection of the second contact electrode 17 on the first semiconductor layer 21 roughly coincide (FIG. 6B The middle insulating layer 24 is shielded by the conductive layer 25).
  • the insulating layer 24 and the conductive layer 25 are provided in a direction perpendicular to the plane where the first semiconductor layer 21 is located. , The insulating layer 24 and the second contact electrode 27 are at least partially opposite, so that the current from the second pad 32 received by the second contact electrode 27 can be prevented from being injected into the second semiconductor layer 23 vertically, and the current is passing through the conductive layer.
  • the current transfer direction is changed, so that the current can expand laterally in the conductive layer 25.
  • the current is transmitted to the second semiconductor layer 23 through the portion where the conductive layer 25 is coupled with the second semiconductor layer 23, thereby expanding the transmission range of the current in the second semiconductor layer 23, and making the current distribution in the second semiconductor layer 23 more effective. Uniformity, so that the combined light emission area of electrons and holes in the light-emitting layer 22 is more uniform, and the light-emitting efficiency of the light-emitting layer 22 is improved.
  • the thickness d2 of the first pad 31 and the second pad 32 is 20 ⁇ m-30 ⁇ m, and the supporting and reinforcing unit
  • the thickness d3 of 4a is 20 ⁇ m to 30 ⁇ m.
  • the thickness of the first liner 31 and the second liner 32 is 30 ⁇ m
  • the thickness of the support reinforcement unit 4a is 30 ⁇ m
  • the surface of the support reinforcement unit 4a away from the epitaxial layer unit 2a is in contact with the first liner 31 and the second liner.
  • the surface of the pad 32 away from the epitaxial layer unit 2a is flush.
  • the thickness of the first pad 31 and the second pad 32 is 30 ⁇ m
  • the thickness of the supporting and reinforcing unit 4a is 25 ⁇ m
  • the surface of the supporting and reinforcing unit 4a away from the epitaxial layer unit 2a is lower than the first pad 31 and the second pad 32 is away from the surface of the epitaxial layer unit 2a.
  • the inorganic light-emitting diode chip 10 provided by some embodiments of the present disclosure has the advantages of thinner thickness and higher strength, and can withstand the force applied during spot measurement and the force applied during transfer. After 10 is transferred to the array substrate, since the thickness of the inorganic light-emitting diode chip 10 is relatively thin, the manufacturing difficulty of the optical structure is reduced, and the height of the optical structure can be made larger than the thickness of the inorganic light-emitting diode chip 10, so that the The dimming effect of light is better.
  • some embodiments of the present disclosure also provide a method for manufacturing an inorganic light emitting diode chip 10, the method including:
  • a substrate 1 is provided, and an epitaxial layer 2 is formed on one side of the substrate 1.
  • the substrate 1 is a sapphire substrate or a silicon substrate.
  • a metal organic compound vapor phase epitaxy process is used to form a multilayer film included in the epitaxial layer 2 on one side of the substrate 1.
  • the epitaxial layer 2 includes a plurality of epitaxial layer units 2a. Illustratively, as shown in FIG. 8A, there is a certain interval between adjacent epitaxial layer units 2a.
  • the surface of each epitaxial layer unit 2a can be covered with a protective layer, which has strong corrosion resistance. In this way, the chip mother wafer is cut into independent chips along the interval in the subsequent steps.
  • a protective layer is provided on the surface to protect the film covered by the protective layer in the epitaxial layer unit 2a from corrosion, and prevent the film covered by the protective layer in the epitaxial layer unit 2a from being directly exposed and easily oxidized and corroded.
  • a plurality of spacers 3 are prepared on the side of the epitaxial layer 2 away from the substrate 1.
  • an electrochemical deposition process or an evaporation process is used to prepare a plurality of pads 3 on the side of the epitaxial layer 2 away from the substrate 1.
  • the plurality of spacers 3 includes a plurality of first spacers 31 and a plurality of second spacers 32.
  • a first spacer is prepared on the side of each epitaxial layer unit 2a away from the substrate 1.
  • the liner 31 and the second liner 32 are examples of each epitaxial layer unit 2a away from the substrate 1.
  • the material of the liner 3 includes at least one of copper, aluminum, and copper-aluminum alloy.
  • the thickness of at least one spacer 3 is 20 ⁇ m to 30 ⁇ m.
  • the liner 3 includes a liner body, and a protective layer covering the sidewalls of the liner body and the surface away from the epitaxial layer 2.
  • the material of the liner body includes copper, aluminum, and copper-aluminum alloy.
  • the material of the protective layer includes nickel and gold.
  • the specific step of S2 is to adopt an electrochemical deposition process or an evaporation process, using at least one of copper, aluminum, and copper-aluminum alloy. This material forms the pad main body of the plurality of pads 3, and then the nickel-gold material is coated on the sidewall and surface of the pad main body of the plurality of pads 3 by electroless plating to form a protective layer.
  • a supporting and reinforcing layer 4 is formed in the gaps between the plurality of pads 3.
  • the thickness of the supporting and reinforcing layer 4 is 20 ⁇ m to 30 ⁇ m.
  • the material of the support and reinforcement layer 4 is a cured adhesive material.
  • the material of the support and reinforcement layer 4 includes silica gel, epoxy resin, or photoresist.
  • forming S3 supporting the reinforcement layer 4 in the gaps between the plurality of pads 3 includes:
  • a supporting and reinforcing film 4' is formed on the side of the epitaxial layer 2 where a plurality of spacers 3 are formed.
  • the laminated structure formed by the substrate 1, the epitaxial layer 2 and the plurality of spacers 3 is fixed in the mold 6, and the material supporting the reinforcement layer is injected into the mold 6 to make The material supporting the reinforcement layer covers a plurality of pads 3, and the material supporting the reinforcement layer is cured.
  • heat curing or ultraviolet lamp curing may be used for curing, so that a plurality of pads 3 are formed on the substrate 1.
  • a supporting and reinforcing film 4' is formed on one side.
  • the material of the support and reinforcement layer is silica gel or epoxy resin, and the thickness of the formed support and reinforcement film 4'is greater than the thickness of the plurality of pads 3.
  • a grinding machine is used to grind the support and reinforcement film 4'until the surface of the plurality of spacers 3 away from the epitaxial layer 2 is exposed.
  • the support and reinforcement film 4'shown in FIG. 8D is removed.
  • the part of the support and reinforcement film 4'below the dotted line is left, and the support and reinforcement layer 4 shown in FIG. 8E is obtained.
  • "removing the part of the support and reinforcement film 4'that covers the surface of the plurality of spacers 3 away from the epitaxial layer” means that the part of the support and reinforcement film 4'that is higher than the plurality of spacers 3 is equalized. Remove.
  • the surface of the support and reinforcement layer 4 away from the epitaxial layer 2 is flush with the surfaces of the plurality of pads 3 away from the epitaxial layer 2, for example, the thickness of the support and reinforcement layer 4 and the thickness of the pad 3 are both 30 ⁇ m.
  • forming S3 supporting the reinforcement layer 4 in the gaps between the plurality of pads 3 includes:
  • a photoresist is spin-coated on the side of the epitaxial layer 2 where a plurality of spacers 3 are formed to form a supporting and reinforcing film 4'.
  • the patterned support and reinforcement film 4' remove the part of the support and reinforcement film 4'that covers the surface of the plurality of pads 3 away from the epitaxial layer 2, so that the surface of the plurality of pads 3 away from the epitaxial layer 2 is exposed.
  • the supporting and reinforcing film 4' is patterned by an exposure and development process, and the specific steps are as follows:
  • the support and reinforcement film 4' After exposing the support and reinforcement film 4', apply developer on the surface of the support and reinforcement film 4', so that the exposed part of the developer and the support and reinforcement film 4'will be dissolved in the developer, for example, Figure 9D Support and reinforcement film 4
  • the part above the dotted line in ' is dissolved in the developing solution, thereby removing this part, leaving the part below the dotted line in the supporting and reinforcing film 4'in FIG. 9D to obtain a supporting solidified layer 4 (as shown in FIG. 9E).
  • the surface of the support and reinforcement layer 4 away from the epitaxial layer 2 is lower than the surface of the plurality of spacers 3 away from the epitaxial layer 2.
  • the thickness of the support and reinforcement layer 4 is 25 ⁇ m
  • the thickness of the spacer 3 is 30 ⁇ m.
  • the thickness of the supporting and reinforcing layer can be controlled more accurately through the exposure and development process, and the preparation accuracy is high.
  • the substrate 1 is peeled off from the epitaxial layer 2 to obtain an inorganic light-emitting diode chip mother wafer 20.
  • the method of stripping the substrate 1 from the epitaxial layer 2 in S4 is to use laser lift-off technology.
  • the substrate 1 in S1 is Before the epitaxial layer 2 is formed on the side of the substrate 1, the step of forming a buffer layer on the side of the substrate 1 is further included.
  • the material of the buffer layer is gallium nitride. In this way, in S4, a laser is used to vaporize the buffer layer between the substrate 1 and the epitaxial layer 2 to realize the peeling of the substrate 1 from the epitaxial layer 2.
  • the method of peeling the substrate 1 from the epitaxial layer 2 in S4 is to use an acid etching technique, for example, the substrate 1 is immersed in a strong acid. In the etching solution, the substrate 1 is etched, so that the substrate 1 is separated from the epitaxial layer 2.
  • the inorganic light-emitting diode chip mother substrate 20 is divided into a plurality of inorganic light-emitting diode chips 10.
  • each inorganic light emitting diode chip 10 includes an epitaxial layer unit 2a, a first liner 31 and a second liner 32 arranged on one side of the epitaxial layer unit 2a, filled around the first liner 31 and the second liner 32 around the support reinforcement unit 4a.
  • S6 Perform spot measurement on the plurality of inorganic light emitting diode chips 10 respectively, and sort the plurality of inorganic light emitting diode chips 10 according to the spot measurement results.
  • a probe method is used to perform spot measurement on a plurality of inorganic light emitting diode chips 10, for example, two probes are respectively contacted with the surfaces of the first pad 31 and the second pad 32 away from the epitaxial layer 2, The optical performance of each inorganic light-emitting diode chip 10 is measured, and the plurality of inorganic light-emitting diode chips 10 are sorted according to the spot measurement results.
  • the support and reinforcement layer 4 is formed in the gaps between the plurality of spacers 3, thereby increasing the strength of the inorganic light-emitting diode chip mother substrate 20, and thus is peeled off.
  • the inorganic light emitting diode chip mother 20 can withstand the stress during peeling without breaking or damage.
  • the resulting inorganic light emitting diode chip mother 20 is compared with the inorganic light emitting diode chip mother having the substrate 1. The thickness of the sheet is reduced, so that the obtained inorganic light emitting diode chip 10 has a thinner thickness and a higher strength.
  • the inorganic light-emitting diode chip 10 prepared by the preparation method provided in the present disclosure includes supporting and reinforcing units 4a filled around the first gasket 31 and the second gasket 32, so that the inorganic light-emitting diode chip 10 is The strength is improved, so the inorganic light-emitting diode chip 10 can withstand the force of the probe during spot measurement, and can withstand the example of transfer, and is not prone to breakage.
  • the light-emitting diode light-emitting device provided by the present disclosure is a light-emitting diode display device, as shown in FIGS. 3A and 4, the array substrate in the light-emitting diode display device is an array substrate, and a plurality of inorganic light-emitting diode chips 10 It is packaged on the array substrate 20.
  • the inorganic light emitting diode chip 10 may be packaged on the array substrate in a flip-chip or pasting manner. In FIG. 4, the flip-chip is taken as an example.
  • the array substrate 20 includes a plurality of thin film transistors TFT, a plurality of anodes 81 and a plurality of cathodes 82.
  • Each anode 81 is coupled to the drain of a thin film transistor TFT.
  • Each inorganic light emitting diode chip 10 includes The two spacers 3 are respectively coupled with an anode 81 and a cathode 82.
  • the first semiconductor layer is an N-type semiconductor layer
  • the second semiconductor layer is a P-type semiconductor layer.
  • each inorganic light-emitting diode chip 10 is bonded and connected to the cathode 82 through a conductive material 9 (for example, solder), and the second pad 32 of each inorganic light-emitting diode chip 10 is connected to one through solder 9
  • the anode 81 is coupled to control whether the corresponding inorganic light emitting diode chip 10 emits light by turning on and off the thin film transistor TFT, thereby realizing display.
  • the plurality of inorganic light-emitting diode chips 10 includes a plurality of blue inorganic light-emitting diode chips, a plurality of red-light inorganic light-emitting diode chips, and a plurality of green-light inorganic light-emitting diode chips.
  • the LED chips 10 are arranged in an array according to a certain rule.
  • An optical structure 5 is provided around each inorganic light-emitting diode chip 10, such as a square wall with a certain height. Since the thickness of the inorganic light-emitting diode chip 10 provided by some embodiments of the present disclosure is relatively thin, the optical structure can be reduced.
  • the manufacturing process is difficult, and the height of the optical structure can be greater than the thickness of the inorganic light-emitting diode chip 10, so that the light emitted by the inorganic light-emitting diode chip 10 can be light-type controlled, and the display viewing angle of the display device can be improved.
  • the light-emitting diode light-emitting device provided by the present disclosure is a light-emitting diode light panel, such as a mini LED light panel.
  • the light-emitting diode light panel can be used as a surface light source.
  • the light-emitting diode light panel can be used as a backlight module.
  • the backlight source in the group provides light for the liquid crystal display device.

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Abstract

提供一种无机发光二极管芯片母片，包括：外延层、多个衬垫和支撑加固层。其中，所述外延层的相对的两侧分别为第一侧和第二侧；多个衬垫设置于所述外延层的第一侧；所述支撑加固层填充于所述多个衬垫之间的间隙。

Description

无机发光二极管芯片母片、无机发光二极管芯片 技术领域
本公开涉及显示技术领域，尤其涉及一种无机发光二极管芯片母片、无机发光二极管芯片及其制作方法、发光二极管发光装置。
背景技术
mini LED(mini Organic Light-Emitting Diode，次毫米发光二极管)显示装置或micro LED(micro Organic Light-Emitting Diode，微型发光二极管)显示装置是由数量众多的小尺寸LED阵列组成的显示装置，具有亮度高、显示画面清晰和功耗低等优点，应用前景较好。
发明内容
一方面，提供一种无机发光二极管芯片母片，包括：外延层、多个衬垫和支撑加固层。其中，所述外延层的相对的两侧分别为第一侧和第二侧；多个衬垫设置于所述外延层的第一侧；所述支撑加固层填充于所述多个衬垫之间的间隙。
在一些实施例中，所述外延层的厚度与衬垫的厚度的比例范围为1:6～1:2。
在一些实施例中，至少一个衬垫的厚度为20μm～30μm。
在一些实施例中，每个衬垫的材料包括铜、铝和铜铝合金中的至少一种。
在一些实施例中，每个衬垫包括衬垫主体，及覆盖在所述衬垫主体的侧壁和远离所述外延层的表面上的保护层；所述保护层导电。
在一些实施例中，所述衬垫主体的材料包括铜、铝和铜铝合金中的至少一种，所述保护层的材料包括镍金。
在一些实施例中，所述支撑加固层的厚度为20μm～30μm。
在一些实施例中，所述支撑加固层的远离所述外延层的表面与所述多个衬垫的远离所述外延层的表面齐平。或者，所述支撑加固层的远离所述外延层的表面低于所述多个衬垫的远离所述外延层的表面。
在一些实施例中，所述支撑加固层的材料包括固化胶类材料。
在一些实施例中，所述支撑加固层的材料包括硅胶、环氧树脂或光刻胶。
在一些实施例中，所述支撑加固层呈白色或黑色。
在一些实施例中，在所述支撑加固层呈白色的情况下，所述支撑加 固层的材料包括钛白粉。在所述支撑加固层呈黑色的情况下，所述支撑加固层的材料包括碳粉。
在一些实施例中，所述外延层的第一侧的表面具有多个凸起，所述多个凸起嵌入所述支撑加固层中。
在一些实施例中，所述外延层的厚度为5μm～10μm。
在一些实施例中，所述无机发光二极管芯片母片具有多个无机发光二极管芯片区域；所述多个衬垫包括多个第一衬垫和多个第二衬垫。所述外延层包括多个外延层单元，每个无机发光二极管芯片区域内设置有外延层单元、第一衬垫和第二衬垫。
所述外延层单元包括：第一半导体层、发光层、第二半导体层和平坦层。其中，第一半导体层包括第一部分和第二部分，发光层设置于所述第一半导体层的第一部分一侧，第二半导体层设置于所述发光层远离所述第一半导体层一侧，平坦层覆盖于所述第二半导体层远离所述发光层一侧。所述平坦层具有第一通孔和第二通孔，在每个所述无机发光二极管芯片区域内，所述第一衬垫通过所述第一通孔与所述第一半导体层耦接，所述第二衬垫通过所述第二通孔与所述第二半导体层耦接。
在一些实施例中，所述外延层单元还包括：第一接触电极、绝缘层、导电层和第二接触电极。其中，第一接触电极设置于所述第一半导体层的第二部分与所述平坦层之间；所述第一接触电极与所述第一半导体层的第二部分电接触，所述第一衬垫通过所述第一通孔与所述第一接触电极耦接。
绝缘层设置于所述第二半导体层与所述平坦层之间。导电层设置于所述绝缘层与所述平坦层之间，所述导电层与所述第二半导体层电接触。第二接触电极设置于所述导电层与所述平坦层之间；所述第二接触电极与所述导电层电接触，所述第二衬垫通过所述第二通孔与所述第二接触电极耦接；且，所述第二接触电极在所述第一半导体层上的正投影与所述绝缘层在所述第一半导体层上的正投影至少部分重叠。
另一方面，提供一种无机发光二极管芯片，所述无机发光二极管芯片由如上所述的无机发光二极管芯片母片经裂片工艺得到，所述无机发光二极管芯片包括：外延层单元、设置于所述外延层单元一侧的第一衬垫和第二衬垫、及支撑加固单元，所述支撑加固单元填充于所述第一衬垫的周围和所述第二衬垫的周围。
在一些实施例中，所述第一衬垫和所述第二衬垫的厚度为20μm～30 μm；所述支撑加固单元的厚度为20μm～30μm。
再一方面，提供一种无机发光二极管芯片的制作方法，包括：提供衬底，在所述衬底的一侧形成外延层；在所述外延层远离所述衬底的一侧制备多个衬垫；在所述多个衬垫之间的间隙形成支撑加固层；将所述衬底从所述外延层上剥离，得到无机发光二极管芯片母片。
在一些实施例中，所述在所述多个衬垫之间的间隙形成支撑加固层，包括：采用注塑成型工艺或压膜工艺，在所述外延层形成有多个衬垫的一侧形成支撑加固薄膜；采用研磨工艺，去除所述支撑加固薄膜中覆盖在所述多个衬垫远离所述外延层的表面上的部分，使所述多个衬垫远离所述外延层的表面暴露。
在一些实施例中，所述在所述多个衬垫之间的间隙形成支撑加固层，包括：采用光刻胶材料，在所述外延层形成有多个衬垫的一侧形成支撑加固薄膜；图案化所述支撑加固薄膜，去除所述支撑加固薄膜中覆盖于所述多个衬垫远离所述外延层的表面的部分，使所述多个衬垫远离所述外延层的表面暴露。
在一些实施例中，无机发光二极管芯片的制作方法还包括：在所述将所述衬底从所述外延层上剥离，得到无机发光二极管芯片母片之后，将所述无机发光二极管芯片母片分割成多个无机发光二极管芯片；对所述多个无机发光二极管芯片分别进行点测，并根据点测结果对所述多个无机发光二极管芯片进行分选。
又一方面，提供一种发光二极管发光装置，包括：阵列基板和设置于所述阵列基板上的多个如上所述的无机发光二极管芯片。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据相关技术中的一些实施例的无机发光二极管芯片的一种结构图；
图2为根据相关技术中的一些实施例的无机发光二极管芯片的另一种结构图；
图3A为根据本公开的一些实施例的发光二极管发光装置的结构图；
图3B为根据一些实施例的无机发光二极管芯片的发光光型对比图；
图4为根据图3A中截面线AA’得到的剖面图。
图5A为根据本公开的一些实施例的无机发光二极管芯片母片的一种结构图；
图5B为根据本公开的一些实施例的无机发光二极管芯片母片的另一种结构图；
图6A为根据本公开的一些实施例的无机发光二极管芯片中外延层单元第一半导体层的结构图；
图6B为根据本公开的一些实施例的无机发光二极管芯片中外延层单元的结构图；
图7为根据本公开的一些实施例的无机发光二极管芯片的结构图；
图8A～图8G为根据本公开的一些实施例的无机发光二极管芯片的制作方法的一种步骤图；
图9A～图9G为根据本公开的一些实施例的无机发光二极管芯片的制作方法的另一种步骤图；
图10为根据本公开的一些实施例的无机发光二极管芯片的制作方法的一种流程图；
图11A为根据本公开的一些实施例的无机发光二极管芯片的制作方法的另一种流程图；
图11B为根据本公开的一些实施例的无机发光二极管芯片的制作方法的又一种流程图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)” 或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
本公开的一些实施例提供一种发光二极管发光装置，该发光二极管发光装置包括阵列基板和设置于该阵列基板上的多个无机发光二极管芯片。多个无机发光二极管芯片与阵列基板上的信号源耦接，在信号源的作用下实现发光。
在一些示例中，如图3A所示，本公开所提供的发光二极管发光装置为发光二极管显示装置，例如为mini LED显示装置或者micro LED显示装置，包括多个无机发光二极管芯片，具体可以为次毫米无机发光二极管芯片(mini LED芯片)或者微型无机发光二极管芯片(micro LED芯片)。示例性地，发光二极管显示装置30包括阵列基板20和设置于阵列基板20一侧的多个无机发光二极管芯片10，多个无机发光二极管芯片10密度高、数量多、间距小，能够减小显示装置的像素点间距，提高分辨率，使该显示装置具有较好的显示效果。
以mini LED显示装置为例，为了对次毫米无机发光二极管芯片所发出光线的光型进行调控，需要在阵列基板上多个次毫米无机发光二极管芯片的间隙处制备光学结构。示例性地，如图3A所示，在该mini LED显示装置30中，在每个无机发光二极管芯片10的周围制备有环绕该无机发光二极管芯片10且具有一定高度的围墙5，例如该围墙5为口字形，可通过控制围墙5的高度、围墙5与无机发光二极管芯片10的距离、围墙的各个侧壁的倾斜角度等参数， 对无机发光二极管芯片10所发出光线的光型进行调控。
如图3B所示，发明人对单颗无机发光二极管芯片发光的光型进行了模拟。如图4所示，在不设置围墙的情况下(参见曲线B，所采用的无机发光二极管芯片为图1所示的无机发光二极管芯片10’)，在该无机发光二极管芯片的出光侧的正视角方向，无机发光二极管芯片所发出的光线的强度较低，并且，在该无机发光二极管芯片的出光侧的各个角度所测得的光线亮度普遍较低，所发出的光线比较分散。在设置围墙的情况下(参见曲线A，所采用的无机发光二极管芯片为图7所示的无机发光二极管芯片10)，无机发光二极管芯片所发出的光线比较集中，该无机发光二极管芯片的出光侧的正视角方向，无机发光二极管芯片所发出的光线的强度最高。可见，若在mini LED显示装置中设置光学结构，在显示时，mini LED显示装置的正视角方向亮度最高，使得该显示装置的显示效果好。需要说明的是，本公开中所提到的正视角方向均指位于无机发光二极管芯片(或显示装置)所在平面的法线上的位置，且该法线经过无机发光二极管芯片(或显示装置)的几何中心。
可见，设置光学结构能够达到调控光型、改善显示视角的效果。根据当前的工艺极限，上述光学结构的高度不大于50μm；为实现较好的调光效果，且为便于光学结构的制作，无机发光二极管芯片10的厚度应该小于光学结构的高度。
如图1和图2所示，相关技术中，无机发光二极管芯片10’包括外延层2，及设置于外延层2的一侧的第一衬垫31和第二衬垫32，其中，外延层2包括发光层、N型半导体层和P型半导体层等多层薄膜层，第一衬垫31和第二衬垫32分别与外延层2中的N型半导体层和P型半导体层耦接，第一衬垫31和第二衬垫32用于与外部信号源耦接，通过对第一衬垫31和第二衬垫32施加电压，无机发光二极管芯片10’能够发光。
相关技术中，无机发光二极管芯片的一种制备方法如下：在衬底上依次制备外延层和多个衬垫，通过研磨工艺将衬底减薄至所需厚度，得到无机发光二极管芯片母片，再将无机发光二极管芯片母片进行分割得到多个无机发光二极管芯片，所得到的无机发光二极管芯片10’的结构如图1所示。在上述制备方法中，通过研磨衬底，可以将无机发光二极管芯片母片从700μm～800μm最小减薄至80μm，若继续对衬底进行研磨，则可能会出现衬底整片破裂的问题，导致严重的良率损失。并且，由于衬底(例如蓝宝石衬底)具有晶格结构，在采用裂片工艺将无机发光二极管芯片母片分割成多个无机发光二极管芯片时，衬底会沿其晶格结构中特定方向裂开，从而导致得到的 无机发光二极管芯片10’的四周不规整，出现斜边，这样，就会使无机发光二极管芯片10’的发光光型相对于该芯片的正视角方向不对称(如图4中的曲线B)。如图1所示，由于带有衬底1的无机发光二极管芯片10’的厚度d1最小为80μm，大于上述光学结构的最大高度(50μm)，使得光学结构难以制作，而无法有效改善无机发光二极管芯片的发光光型。
无机发光二极管芯片的另一种制备方法为：在衬底上依次制备外延层和多个衬垫之后，将衬底从外延层上剥离，得到无机发光二极管芯片母片，再将无机发光二极管芯片母片分割得到多个无机发光二极管芯片，所得到的无机发光二极管芯片10’的结构如图2所示。这种方法制备得到的无机发光二极管芯片仅包括外延层和衬垫，而由于外延层的韧性较差，受力时易断裂。故需要对所制备得到的各无机发光二极管芯片进行点测，以按需进行分选，而该无机发光二极管芯片的外延层无法承受进行点测时正负极探针所施加的力，在进行点测时会发生断裂，并且，该无机发光二极管芯片的外延层也难以承受转移时的施力(例如将无机发光二极管芯片转移至阵列基板上)，造成无机发光二极管芯片转移的难度增大。
综上，相关技术中的无机发光二极管芯片的制备方法以及所制备得到的无机发光二极管芯片10’存在下述问题，在所制备得到的无机发光二极管芯片10’具有衬底1的情况下，无机发光二极管芯片10’的厚度较厚，不利于光学结构的制作，且发光光型不对称。在所制备得到的无机发光二极管芯片10’不具有衬底的情况下，无机发光二极管芯片10’太脆弱，难以进行点测以及转移，难以应用到显示产品中。
基于此，如图5A和图5B所示，本公开的一些实施例提供了一种无机发光二极管芯片母片20，包括：外延层2、多个衬垫3和支撑加固层4。
其中，外延层2的相对的两侧分别为第一侧B1和第二侧B2，多个衬垫3设置于外延层2的第一侧B1，支撑加固层4填充于所述多个衬垫3之间的间隙。
将上述无机发光二极管芯片母片20进行分割，得到多个无机发光二极管芯片10。为了方便说明，如图5A和图5B所示，将无机发光二极管芯片母片20分为多个无机发光二极管芯片区域Q，所述多个衬垫3包括多个第一衬垫31和多个第二衬垫32。外延层2包括多个外延层单元2a，支撑加固层4包括多个支撑加固单元4a。每个无机发光二极管芯片区域Q内设置有外延层单元2a、支撑加固单元4a、第一衬垫31和第二衬垫32。
如图7所示，本公开的一些实施例还提供了一种无机发光二极管芯片10， 该无机发光二极管芯片10由上述无机发光二极管芯片母片20经分割得到，无机发光二极管芯片10包括：外延层单元2a、第一衬垫31、第二衬垫32和支撑加固单元4a。其中，第一衬垫31和第二衬垫32设置于外延层单元2a的一侧，支撑加固单元4a填充于第一衬垫31的周围和第二衬垫32的周围。
本公开的一些实施例提供的无机发光二极管芯片母片20不包括衬底，通过在多个衬垫3之间的间隙填充支撑加固层4，使得无机发光二极管芯片母片20的强度得以增强，不易发生外延层2受力发生断裂或损伤的情况，且相比相关技术中包含衬底的无机发光二极管芯片母片，本公开所提供的无机发光二极管芯片母片20的厚度较薄。从而，将该无机发光二极管芯片母片20进行分割所得到的无机发光二极管芯片10不会出现四周不规整的问题，且具有厚度较薄、强度较高的优点，能够承受进行点测时的施力以及进行转移时的施力，并且，在将无机发光二极管芯片10转移至阵列基板上之后，由于无机发光二极管芯片10的厚度较薄，降低了光学结构的制作难度，且能够使该光学结构的高度大于无机发光二极管芯片10的厚度，从而对无机发光二极管芯片10发出的光线的调光效果较好。
如图5A和图5B所示，在一些实施例中，由于本公开实施例所提供的无机发光二极管芯片母片20不包括衬底，因此为增强无机发光二极管芯片母片20的强度，使其不易断裂，填充于所述多个衬垫3之间的间隙的支撑加固层4需要具有一定的厚度，以使无机发光二极管芯片母片20不至于太薄、太脆弱，同样的，多个衬垫3也需要具有一定的厚度，以保证多个衬垫3远离外延层2的表面能够暴露出来，且多个衬垫3不能过厚而使得无机发光二极管芯片母片20的总厚度过厚。
在一些示例中，至少一个衬垫3的厚度d2为20μm～30μm，这样，衬垫3的厚度能与支撑加固层4的厚度相配合，使得无机发光二极管芯片母片20的总厚度能够控制在合理的范围内，进而能够得到厚薄适中且具有一定强度的无机发光二极管芯片10。示例性地，无机发光二极管芯片母片20所包括的所有衬垫3的厚度均为20μm～30μm，或者，至少一个衬垫3的厚度为20μm、25μm或者30μm等。
在一些实施例中，衬垫3的材料选用成本较低且导电性能较好的材料，本公开对此并不设限。示例性地，每个衬垫3的材料包括铜、铝和铜铝合金中的至少一种。例如，每个衬垫3的材料为铜。或者，每个衬垫3的一部分的材料为铜，该衬垫3的另一部分的材料为铜铝合金。
在一些实施例中，每个衬垫3包括衬垫主体，及覆盖在衬垫主体的侧壁 和远离外延层2的表面上的保护层，该保护层导电。
保护层包覆在衬垫主体表面，能够保护衬垫主体，防止衬垫主体被氧化或者被水腐蚀，延长衬垫3的使用寿命，并且保护层能够导电，同样能起到电气耦接的作用。
在一些示例中，衬垫主体的材料包括铜、铝和铜铝合金中的至少一种，保护层的材料为耐腐蚀性能较高的导电材料，示例性地，保护层的材料包括镍金。
在一些实施例中，为增强无机发光二极管芯片母片20的强度，使其不易断裂，填充于所述多个衬垫3之间的间隙的支撑加固层4需要具有一定的厚度，以使无机发光二极管芯片母片20不至于太薄、太脆弱，同时，支撑加固层4的厚度也不能过厚而使得无机发光二极管芯片母片20的总厚度过厚。示例性地，如图5A和图5B所示，支撑加固层4的厚度d3为20μm～30μm。例如，支撑加固层4的厚度d3为20μm、25μm或30μm。
在一些实施例中，如图5B所示，支撑加固层4的远离外延层2的表面与多个衬垫3的远离外延层2的表面齐平。也就是说，支撑加固层4的厚度与衬垫3的厚度一致，示例性地，支撑加厚层的厚度和衬垫3的厚度均为25μm，这样，多个衬垫3的远离外延层2的表面能够暴露出来，以实现无机发光二极管芯片10的点测分选或者与显示基板上的信号源耦接。
在另一些实施例中，如图5A所示，支撑加固层4的远离所述外延层2的表面低于所述多个衬垫3的远离所述外延层2的表面。也就是说，支撑加固层4的厚度小于衬垫3的厚度一致，示例性地，支撑加厚层的厚度为25μm，衬垫3的厚度均为30μm，这样，多个衬垫3的远离外延层2的表面和一部分侧壁能够暴露出来，以实现无机发光二极管芯片10的点测分选或者与显示基板上的信号源耦接。
在一些实施例中，如图5A和图5B所示，支撑加固层4的材料包括固化胶类材料。固化胶类材料在没有固化之前流动性较好，能够较容易地填充于多个衬垫3之间的间隙，在填充好之后，固化胶类材料可以固化成强度较高的固体，能够起到增强无机发光二极管芯片母片20的强度的作用。本公开对支撑加固层4的材料不做限定，只要该材料具有上述特性即可，示例性地，支撑加固层4的材料包括硅胶、环氧树脂或光刻胶。
在一些实施例中，支撑加固层4是透明的，这样，无机发光二极管芯片10所发出的光线能够穿透支撑加固层4，在无机发光二极管芯片10的两侧均能出射光线。
在另一些实施例中，支撑加固层4具有颜色，例如支撑加固层4呈白色或黑色，以根据需要调整所发出的光线的亮度。
示例性地，在支撑加固层4呈白色的情况下，支撑加固层4的材料包括钛白粉。例如，支撑加固层4的材料包括硅胶和钛白粉，钛白粉和硅胶按一定的比例混合形成固化胶类材料。
在支撑加固层4呈白色的情况下，支撑加固层4能够起到反射光线的作用，无机发光二极管芯片10的外延层2发出的光线经白色的支撑加固层4的反射，亮度增强，从而该无机发光二极管芯片10可以用在需要提供高亮度的光线的发光产品中。
示例性地，在支撑加固层4呈黑色的情况下，支撑加固层4的材料还包括碳粉。例如，支撑加固层4的材料包括硅胶和碳粉，碳粉和硅胶按一定的比例混合形成固化胶类材料。
在支撑加固层4呈黑色的情况下，支撑加固层4能够起到吸收光线作用，无机发光二极管芯片10的外延层单元2a发出的光线经黑色的支撑加固层4的吸光作用，亮度减弱，从而该无机发光二极管芯片10可以用在需要提供低亮度的光线的显示产品中，增加显示产品的对比度。
作为一种可能的设计，如图5A所示，外延层2的第一侧B1的表面具有多个凸起c，多个凸起c嵌入支撑加固层4中。通过在外延层2的第一侧B1的表面设置多个凸起c，并使多个凸起c嵌入支撑加固层4中，能够增大外延层2与支撑加固层4之间的结合力，使外延层2与支撑加固层4不易分离。
在一些实施例中，如图5A和图5B所示，外延层2的厚度d4为5μm～10μm。
在一些实施例中，如图6A、图6B和图7所示，上述提到的外延层单元2a包括：第一半导体层21、发光层22、第二半导体层23和平坦层28。其中，图6B所示出的是外延层单元2a在不包含平坦层28的情况下的俯视图，图5A和图5B、图7中的外延层单元2a的截面图为沿图6B中的截面线BB’得到的。
第一半导体层21包括第一部分21a和第二部分21b，示例性地，如图6A所示，第一半导体层21的第一部分21a环绕第二部分21b。
发光层22设置于第一半导体层21的第一部分21a一侧。示例性地，发光层22包括量子阱超晶格层。
发光层22包括不同的材料，以使无机发光二极管芯片10能够发出蓝色、绿色或红色的光线，例如，发光层22的材料包括磷化铝铟镓(AlGaInP)， 从而无机发光二极管芯片10能够发出红色光线。或者，发光层22的材料包括铟氮化镓(InGaN)，从而无机发光二极管芯片10能够发出蓝色光线。或者，发光层22的材料包括铝磷化镓(AlGaP)，从而无机发光二极管芯片10能够发出绿色光线。
第二半导体层23设置于发光层22远离第一半导体层21的一侧。
平坦层28覆盖于第二半导体层23远离发光层22的一侧，平坦层具有第一通孔b1和第二通孔b2，在每个无机发光二极管芯片区域Q内，第一衬垫31通过第一通孔b1与第一半导体层21耦接，第二衬垫32通过第二通孔b2与第二半导体层23耦接。具体的，第一衬垫31通过第一通孔b1与第一半导体层21的第二部分21b接触，实现与第一半导体层21耦接。
在一些示例中，第一半导体层21为N型半导体层，例如，第一半导体层21的材料为N型氮化镓，第二半导体层23为P型半导体层，例如，第一半导体层21的材料为P型氮化镓。对应的，在将无机发光二极管芯片10转移至阵列基板上后，第一衬垫31与阵列基板上的阴极耦接，第二衬垫32与阵列基板上的阳极耦接，从而使得第一半导体层21、发光层22和第二半导体层23之间形成电流通路，从而发光层22在电流作用下发光，实现使无机发光二极管芯片10发光。
在上述示例中，在第一半导体层21为N型半导体层，第二半导体层23为P型半导体层的情况下，可以增大第一半导体层21的厚度，使第一半导体层21的厚度大于第二半导体层23的厚度，示例性地，第一半导体层21的厚度为第二半导体层23的厚度的2～5倍，例如为4倍，这样，可以增强来自第一衬垫31的电子在第一半导体层21中的扩展能力，且在N型半导体层中，电子浓度较高，载流子传输速率较大，可以保证来自第一衬垫31的电子在第一半导体层21中具有较大的传输范围，从而提高无机发光二极管10的发光效率。这样，就无需在外延层单元2a中设置对应第一半导体层21的用于扩展载流子传输范围的结构，此处所述的用于扩展载流子传输范围的结构可参见后续出现的绝缘层24和导电层25。
在另一些示例中，第一半导体层21为P型半导体层，例如，第一半导体层21的材料为P型氮化镓，第二半导体层23为N型半导体层，例如，第一半导体层21的材料为N型氮化镓。对应的，在将无机发光二极管芯片10转移至阵列基板上后，第一衬垫31与阵列基板上的阳极耦接，第二衬垫32与阵列基板上的阴极耦接，从而使得第一半导体层21、发光层22和第二半导体层23之间形成电流通路，从而发光层22在电流作用下发光，实现使无机发 光二极管芯片10发光。
在一些实施例中，外延层单元2a还包括：绝缘层24、导电层25、第一接触电极26和第二接触电极27。
第一接触电极26设置于第一半导体层21，第一衬垫31通过第一通孔与第一接触电极26耦接。通过设置第一接触电极26，能够使第一衬垫31更好地与第一半导体层21耦接，提升载流子的传输速率。
绝缘层24设置于第二半导体层23与平坦层28之间。
导电层25设置于绝缘层24与平坦层28之间。导电层25与第二半导体层23电接触，也就是说，导电层25覆盖在绝缘层24远离第一半导体层21的一侧，导电层25在第一半导体层21上的正投影大于绝缘层24在第一半导体层21上的正投影，使得导电层25能够与第二半导体层23耦接，实现电流传输。
示例性地，导电层25的材料采用导电性能较好，且和第二半导体层23之间具有较强的结合力的材料，从而导电层25能够将电流更有效地传输给第二半导体层23。例如导电层25的材料为氧化铟锡(ITO)。
第二接触电极27设置于导电层25与平坦层28之间；第二接触电极27与导电层25电接触，第二衬垫32通过第二通孔b2与第二接触电极27耦接。且，第二接触电极27在第一半导体层21上的正投影与绝缘层24在所述第一半导体层21上的正投影至少部分重叠。
例如，如图6B和图7所示，第二接触电极27包括第一部分27a、第二部分27b、第三部分27c和第四部分27d，第二部分27b、第三部分27c和第四部分27d通过第一部分27a相连，第二衬垫32通过第二通孔b2与第二接触电极27的第二部分27b耦接。这样，第二接触电极27与导电层25之间的接触面积增大，降低了接触电阻，在相同电压条件下，能够得到更高的电流密度，并且电流在导电层25中的扩展能力增强。绝缘层24与第二接触电极17具有相同的形状，绝缘层24在第一半导体层21上的正投影与第二接触电极17在所述第一半导体层21上的正投影大致重合(图6B中绝缘层24被导电层25遮挡)。
在第一半导体层21为P型半导体层，第二半导体层23为N型半导体层的情况下，通过设置绝缘层24与导电层25，且在垂直于第一半导体层21所在平面的方向上，绝缘层24与第二接触电极27至少有一部分正对，这样，可以防止使第二接触电极27所接收的来自第二衬垫32的电流垂直注入第二半导体层23，电流在经过导电层25向第二半导体层23传输的过程中，电流 传输方向得以改变，使得电流在导电层25中能够横向拓展。电流通过导电层25与第二半导体层23耦接的部分传输至第二半导体层23，从而扩展了电流在第二半导体层23中的传输范围，使得电流在第二半导体层23中的分布更加均匀，从而使得发光层22中电子和空穴的复合发光的区域更加均匀，提升了发光层22的发光效率。
在一些实施例中，如图7所示，本公开的一些实施例所提供的无机发光二极管芯片10中，第一衬垫31和第二衬垫32的厚度d2为20μm～30μm，支撑加固单元4a的厚度d3为20μm～30μm。
示例性地，第一衬垫31和第二衬垫32的厚度为30μm，支撑加固单元4a的厚度为30μm，支撑加固单元4a远离外延层单元2a的表面与第一衬垫31和第二衬垫32远离外延层单元2a的表面齐平。
或者，第一衬垫31和第二衬垫32的厚度为30μm，支撑加固单元4a的厚度为25μm，支撑加固单元4a远离外延层单元2a的表面低于第一衬垫31和第二衬垫32远离外延层单元2a的表面。
本公开的一些实施例所提供的无机发光二极管芯片10具有厚度较薄、强度较高的优点，能够承受进行点测时的施力以及进行转移时的施力，并且，在将无机发光二极管芯片10转移至阵列基板上之后，由于无机发光二极管芯片10的厚度较薄，降低了光学结构的制作难度，且能够使该光学结构的高度大于无机发光二极管芯片10的厚度，从而对显示基板发出的光线的调光效果较好。
如图10、图8A～图8G，图9A～图9G所示，本公开的一些实施例还提供了一种无机发光二极管芯片10的制作方法，该方法包括：
S1、如图8A所示，提供衬底1，在衬底1的一侧形成外延层2。
在一些示例中，衬底1为蓝宝石衬底或者硅衬底。采用金属有机化合物气相外延工艺，在衬底1的一侧形成外延层2所包括的多层薄膜。外延层2包括多个外延层单元2a。示例性地，如图8A所示，相邻外延层单元2a之间有一定间隔。每个外延层单元2a的表面可以覆盖有保护层，该保护层具有较强的抗腐蚀性能，这样，在后续步骤中沿间隔将芯片母片切割成独立芯片，由于每个外延层单元2a的表面设置有保护层，可以保护外延层单元2a中被保护层所包覆的膜层免受腐蚀，避免外延层单元2a中被保护层所包覆的膜层直接暴露而易被氧化和腐蚀。
S2、如图8B所示，在外延层2远离衬底1的一侧制备多个衬垫3。
示例性地，采用电化学沉积工艺或者蒸镀工艺，在外延层2远离衬底1 的一侧制备多个衬垫3。其中，多个衬垫3包括多个第一衬垫31和多个第二衬垫32，例如，如图8B所示，在每个外延层单元2a远离衬底1的一侧制备一个第一衬垫31和的第二衬垫32。
在一些示例中，衬垫3的材料为包括铜、铝和铜铝合金中的至少一种。至少一个衬垫3的厚度为20μm～30μm。
在一些示例中，衬垫3包括衬垫主体，及覆盖在衬垫主体的侧壁和远离所述外延层2的表面上的保护层，衬垫主体的材料包括铜、铝和铜铝合金中的至少一种，保护层的材料包括镍金，在这种情况下，示例性地，S2的具体步骤为采用电化学沉积工艺或者蒸镀工艺，利用铜、铝和铜铝合金中的至少一种材料形成多个衬垫3的衬垫主体，接着采用化学镀的方式，将镍金材料包覆在多个衬垫3的衬垫主体的侧壁和表面上，形成保护层。
S3、如图8C～图8E所示，在多个衬垫3之间的间隙形成支撑加固层4。
示例性地，支撑加固层4的厚度为20μm～30μm。支撑加固层4的材料为固化胶类材料，例如，支撑加固层4的材料包括硅胶、环氧树脂或光刻胶。
在一些实施例中，如图11A，图8C～图8E所示，在所述多个衬垫3之间的间隙形成支撑加固层4的S3，包括：
S31、采用注塑成型工艺或压膜工艺，在外延层2形成有多个衬垫3的一侧形成支撑加固薄膜4’。
在一些示例中，如图8C所示，将衬底1、外延层2和多个衬垫3所形成的叠层结构固定于模具6内，将支撑加固层的材料注入该模具6内，使支撑加固层的材料覆盖多个衬垫3，将支撑加固层的材料固化，示例性地，可采用热固化或紫外灯固化的方式进行固化，从而在衬底1形成有多个衬垫3的一侧形成支撑加固薄膜4’。
示例性地，支撑加固层的材料为硅胶或环氧树脂，所形成的支撑加固薄膜4’的厚度大于多个衬垫3的厚度。
S32、采用研磨工艺，去除支撑加固薄膜4’中覆盖在所述多个衬垫3远离所述外延层的表面上的部分，使所述多个衬垫3远离所述外延层2的表面暴露。
示例性地，利用研磨机，将支撑加固薄膜4’研磨至暴露出多个衬垫3远离外延层2的表面为止，例如，去除图8D中所示出的支撑加固薄膜4’中位于虚线以上的部分，留下支撑加固薄膜4’中位于虚线以下的部分，得到图8E中所示的支撑加固层4。此处的“去除支撑加固薄膜4’中覆盖在所述多个衬垫3远离所述外延层的表面上的部分”是指将支撑加固薄膜4’的高于多个 衬垫3的部分均去除。此时，支撑加固层4的远离外延层2的表面与所述多个衬垫3的远离所述外延层2的表面齐平，例如，支撑加固层4的厚度与衬垫3的厚度均为30μm。
在另一些实施例中，如图11B、图9C～图9E所示，在所述多个衬垫3之间的间隙形成支撑加固层4的S3，包括：
S31’、采用光刻胶材料，在外延层2形成有多个衬垫3的一侧形成支撑加固薄膜4’。
示例性地，如图9C所示，在外延层2形成有多个衬垫3的一侧旋涂光刻胶，形成支撑加固薄膜4’。
S32’、图案化支撑加固薄膜4’，去除支撑加固薄膜4’中覆盖于多个衬垫3远离外延层2的表面的部分，使所述多个衬垫3远离外延层2的表面暴露。
示例性的，采用曝光显影工艺对支撑加固薄膜4’进行图案化，具体提步骤如下：
对支撑加固薄膜4’进行曝光，通过控制曝光参数，例如控制曝光时长、曝光强度等，控制对支撑加固薄膜4’的曝光深度。例如，如图9D所示，使得支撑加固薄膜4’中的曝光深度为h。
对支撑加固薄膜4’进行曝光之后，在支撑加固薄膜4’表面涂覆显影液，使显影液与支撑加固薄膜4’中经过曝光的部分会溶解于显影液中，例如图9D支撑加固薄膜4’中位于虚线以上的部分溶于显影液中，从而将这部分去除，保留图9D中支撑加固薄膜4’中位于虚线以下的部分，得到支撑固化层4(如图9E所示)。此时，支撑加固层4的远离外延层2的表面低于所述多个衬垫3的远离外延层2的表面，例如，支撑加固层4的厚度为25μm，衬垫3的厚度为30μm。
采用上述方法，通过曝光显影工艺能够较为准确地控制支撑加固层的厚度，制备精度较高。
S4、如图8F所示，将衬底1从外延层2上剥离，得到无机发光二极管芯片母片20。
在一些示例中，在衬底1为蓝宝石衬底的情况下，S4中将衬底1从所述外延层2上剥离的方式为采用激光剥离技术，在这种情况下，S1中在衬底1的一侧形成外延层2之前，还包括在在衬底1的一侧形成缓冲层的步骤，示例性地，缓冲层的材料为氮化镓。这样，在S4中，用激光将衬底1与外延层2之间的缓冲层气化，实现将衬底1从外延层2上剥离。
在另一些示例中，在衬底1的材料为硅衬底的情况下，S4中将衬底1从所述外延层2上剥离的方式为采用酸腐蚀技术，例如，将衬底1浸入强酸腐蚀液中，将衬底1腐蚀，实现衬底1从外延层2上脱落。
S5、如图8G所示，将无机发光二极管芯片母片20分割成多个无机发光二极管芯片10。
示例性地，采用切割工艺，按照所划分的多个无机发光二极管芯片区域，将无机发光二极管芯片母片20切割为多个无机发光二极管芯片10，本公开对切割工艺不做限定，例如可采用机械切割或者激光切割。其中，每个无机发光二极管芯片10包括外延层单元2a、设置于外延层单元2a一侧的第一衬垫31和第二衬垫32，填充于第一衬垫31的周围和第二衬垫32的周围的支撑加固单元4a。
S6、将所述多个无机发光二极管芯片10分别进行点测，并根据点测结果对所述多个无机发光二极管芯片10进行分选。
示例性地，采用探针法分别对多个无机发光二极管芯片10进行点测，例如，将两个探针分别与第一衬垫31和第二衬垫32的远离外延层2的表面接触，测定各无机发光二极管芯片10的光学性能，根据点测结果对所述多个无机发光二极管芯片10进行分选。
本公开的一些实施例提供的无机发光二极管芯片10的制备方法，通过在多个衬垫3之间的间隙形成支撑加固层4，增大了无机发光二极管芯片母片20的强度，从而在剥离衬底1的过程中，无机发光二极管芯片母片20能够承受剥离时的应力，不会断裂或损伤，所得到的无机发光二极管芯片母片20相较于具有衬底1的无机发光二极管芯片母片，厚度得以减薄，从而所得到的无机发光二极管芯片10的厚度较薄，且强度较高。
并且，采用本公开所提供的制备方法所制备得到的无机发光二极管芯片10包括填充于第一衬垫31的周围和第二衬垫32的周围的支撑加固单元4a，使得无机发光二极管芯片10的强度提升，因此该无机发光二极管芯片10可以承受进行点测时探针的施力，以及能够承受转移时的示例，不易发生断裂。
在一些实施例中，本公开所提供的发光二极管发光装置为发光二极管显示装置，如图3A和图4所示，该发光二极管显示装置中的阵列基板为阵列基板，多个无机发光二极管芯片10封装在阵列基板20上，示例性地，无机发光二极管芯片10可以采用倒装或者贴装的方式封装在阵列基板上，图4中以倒装方式为例。
如图4所示，阵列基板20包括多个薄膜晶体管TFT、多个阳极81和多 个阴极82，每个阳极81与一个薄膜晶体管TFT的漏极耦接，每个无机发光二极管芯片10所包括的两个衬垫3分别与一个阳极81和一个阴极82耦接，例如，在无机发光二极管芯片10的发光层中第一半导体层为N型半导体层，第二半导体层为P型半导体层的情况下，每个无机发光二极管芯片10的第一衬垫31通过导电材料9(例如，焊锡)与阴极82绑定连接，每个无机发光二极管芯片10的第二衬垫32通过焊锡9与一个阳极81耦接，通过薄膜晶体管TFT的导通与截断，控制其所对应的无机发光二极管芯片10是否发光，从而实现显示。
在一些示例中，如图3A所示，多个无机发光二极管芯片10包括多个蓝光无机发光二极管芯片、多个红光无机发光二极管芯片和多个绿光无机发光二极管芯片，三种颜色的无机发光二极管芯片10按照一定规律呈阵列式排布。在每个无机发光二极管芯片10周围设置有光学结构5，例如为具有一定高度的口字形围墙，由于本公开的一些实施例所提供的无机发光二极管芯片10的厚度较薄，因此可以降低光学结构的制备工艺难度，且能够使光学结构的高度大于无机发光二极管芯片10的厚度，从而可以对无机发光二极管芯片10发出的光线进行光型调控，改善显示装置的显示视角。
在另一些示例中，本公开所提供的发光二极管发光装置为发光二极管灯板，例如为mini LED灯板，该发光二极管灯板可以作为面光源，示例性地，发光二极管灯板可以作为背光模组中的背光源，为液晶显示装置提供光线。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (22)

  1. 一种无机发光二极管芯片母片，包括：
    外延层，所述外延层的相对的两侧分别为第一侧和第二侧；
    设置于所述外延层的第一侧的多个衬垫；
    支撑加固层，所述支撑加固层填充于所述多个衬垫之间的间隙。
  2. 根据权利要求1所述的无机发光二极管芯片母片，其中，所述外延层的厚度与衬垫的厚度的比例范围为1:6～1:2。
  3. 根据权利要求1或2所述的无机发光二极管芯片母片，其中，至少一个衬垫的厚度为20μm～30μm。
  4. 根据权利要求1～3中任一项所述的无机发光二极管芯片母片，其中，每个衬垫的材料包括铜、铝和铜铝合金中的至少一种。
  5. 根据权利要求1～4中任一项所述的无机发光二极管芯片母片，其中，每个衬垫包括衬垫主体，及覆盖在所述衬垫主体的侧壁和远离所述外延层的表面上的保护层；所述保护层导电。
  6. 根据权利要求5所述的无机发光二极管芯片母片，其中，所述衬垫主体的材料包括铜、铝和铜铝合金中的至少一种，所述保护层的材料包括镍金。
  7. 根据权利要求1～6中任一项所述的无机发光二极管芯片母片，其中，所述支撑加固层的厚度为20μm～30μm。
  8. 根据权利要求7中任一项所述的无机发光二极管芯片母片，其中，所述支撑加固层的远离所述外延层的表面与所述多个衬垫的远离所述外延层的表面齐平；或者，
    所述支撑加固层的远离所述外延层的表面低于所述多个衬垫的远离所述外延层的表面。
  9. 根据权利要求1～8中任一项所述的无机发光二极管芯片母片，其中，所述支撑加固层的材料包括固化胶类材料。
  10. 根据权利要求9所述的无机发光二极管芯片母片，其中，所述支撑加固层的材料包括硅胶、环氧树脂或光刻胶。
  11. 根据权利要求1～10中任一项所述的无机发光二极管芯片母片，其中，所述支撑加固层呈白色或黑色。
  12. 根据权利要求11所述的无机发光二极管芯片母片，其中，
    在所述支撑加固层呈白色的情况下，所述支撑加固层的材料包括钛白粉；
    在所述支撑加固层呈黑色的情况下，所述支撑加固层的材料包括碳粉。
  13. 根据权利要求1～12中任一项所述的无机发光二极管芯片母片，其中，所述外延层的第一侧的表面具有多个凸起，所述多个凸起嵌入所述支撑加固 层中。
  14. 根据权利要求1～13中任一项所述的无机发光二极管芯片母片，其中，所述外延层的厚度为5μm～10μm。
  15. 根据权利要求1～14中任一项所述的无机发光二极管芯片母片，其中，所述无机发光二极管芯片母片具有多个无机发光二极管芯片区域；所述多个衬垫包括多个第一衬垫和多个第二衬垫；
    所述外延层包括多个外延层单元，每个无机发光二极管芯片区域内设置有外延层单元、第一衬垫和第二衬垫；
    所述外延层单元包括：
    第一半导体层；所述第一半导体层包括第一部分和第二部分；
    设置于所述第一半导体层的第一部分一侧的发光层；
    设置于所述发光层远离所述第一半导体层一侧的第二半导体层；
    覆盖于所述第二半导体层远离所述发光层一侧的平坦层；所述平坦层具有第一通孔和第二通孔，在每个所述无机发光二极管芯片区域内，所述第一衬垫通过所述第一通孔与所述第一半导体层耦接，所述第二衬垫通过所述第二通孔与所述第二半导体层耦接。
  16. 根据权利要求15所述的无机发光二极管芯片母片，其中，所述外延层单元还包括：
    设置于所述第一半导体层的第二部分与所述平坦层之间的第一接触电极；所述第一接触电极与所述第一半导体层的第二部分电接触，所述第一衬垫通过所述第一通孔与所述第一接触电极耦接；
    设置于所述第二半导体层与所述平坦层之间的绝缘层；
    设置于所述绝缘层与所述平坦层之间的导电层；所述导电层与所述第二半导体层电接触；
    设置于所述导电层与所述平坦层之间的第二接触电极；所述第二接触电极与所述导电层电接触，所述第二衬垫通过所述第二通孔与所述第二接触电极耦接；且，所述第二接触电极在所述第一半导体层上的正投影与所述绝缘层在所述第一半导体层上的正投影至少部分重叠。
  17. 一种无机发光二极管芯片，所述无机发光二极管芯片由权利要求1～16中任一项所述的无机发光二极管芯片母片经分割得到，所述无机发光二极管芯片包括：
    外延层单元；
    设置于所述外延层单元一侧的第一衬垫和第二衬垫；
    支撑加固单元，所述支撑加固单元填充于所述第一衬垫的周围和所述第二衬垫的周围。
  18. 根据权利要求17所述的无机发光二极管芯片，其中，
    所述第一衬垫和所述第二衬垫的厚度为20μm～30μm；
    所述支撑加固单元的厚度为20μm～30μm。
  19. 一种无机发光二极管芯片的制作方法，包括：
    提供衬底，在所述衬底的一侧形成外延层；
    在所述外延层远离所述衬底的一侧制备多个衬垫；
    在所述多个衬垫之间的间隙形成支撑加固层；
    将所述衬底从所述外延层上剥离，得到无机发光二极管芯片母片。
  20. 根据权利要求19所述的无机发光二极管芯片的制作方法，其中，所述在所述多个衬垫之间的间隙形成支撑加固层，包括：
    采用注塑成型工艺或压膜工艺，在所述外延层形成有多个衬垫的一侧形成支撑加固薄膜；
    采用研磨工艺，去除所述支撑加固薄膜中覆盖在所述多个衬垫远离所述外延层的表面上的部分，使所述多个衬垫远离所述外延层的表面暴露。
  21. 根据权利要求19所述的无机发光二极管芯片的制作方法，其中，所述在所述多个衬垫之间的间隙形成支撑加固层，包括：
    采用光刻胶材料，在所述外延层形成有多个衬垫的一侧形成支撑加固薄膜；
    图案化所述支撑加固薄膜，去除所述支撑加固薄膜中覆盖于所述多个衬垫远离所述外延层的表面的部分，使所述多个衬垫远离所述外延层的表面暴露。
  22. 一种发光二极管发光装置，包括：
    阵列基板；
    设置于所述阵列基板上的多个如权利要求17或18所述的无机发光二极管芯片。
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