201032349 六、發明說明： 【發明所屬之技術領域】 ，本發明是有關於-種發光二極體晶片'其製法及封裝 方法，特別是指-種封裝體積小且製程速度快的發光 體晶片、其製法及封裝方法。 【先前技術】 如圖1所示’習知發光二極體晶片91通常藉由打線方 式與載板92上的外部電極93電連接^於打線製程需要 佔用載板92較大㈣間，而且打線過程是㈣器—條—條 的連接，製程效率極低，不利於系統封裝（咖咖^ package)或晶圓級封裝（waferlevel 為了改善打線製程的缺點，目前常見的方式是利用覆 晶的方式作電性連結，以省去打線製程。但是 覆晶製程需在單顆晶片上植大量金球，過程耗時，也影響 封裝效率。除了覆晶方式之外，另有一些不需打線的封裝 方式例如翻轉晶片將位於晶片表面的電極直接與載板上 的電極黏著而不使用金球，如此方式戦使晶片表面的電 極等高’且具有極佳的平整度，製作精度要求較高，相對 使製程難度較高。另―種方式是調整晶片結構使晶片電 極由晶片纟面延伸至晶片底面，例如曰本專利公開案 請⑽仍所揭示的晶片製造方法，如圖2及圖3所示 ’是在晶片94上開孔94卜鑛上導電層％，使導電層％ 通過開孔941將晶片94表面的電極％與晶片％底面的$ 極97連接，而使晶片94電極97可位於其底面處。㈣ 201032349 JP2008-130875案中，其界定開孔941的壁面為垂直的壁面 ，在鍍製導電層時’會有階梯覆蓋性不良的缺點，容易導 致導電層不均勻而影響導電性。 【發明内容】201032349 VI. Description of the Invention: [Technical Field] The present invention relates to a method and a method for fabricating a light-emitting diode wafer, and more particularly to an illuminant wafer having a small package size and a high process speed. Its method of preparation and packaging methods. [Prior Art] As shown in FIG. 1 , the conventional light-emitting diode chip 91 is usually electrically connected to the external electrode 93 on the carrier 92 by wire bonding. The wire bonding process requires occupying a large (four) carrier plate 92, and the wire is wired. The process is (4) device-strip-bar connection, the process efficiency is extremely low, which is not conducive to system packaging (cafe package) or wafer level package (waferlevel) In order to improve the shortcomings of the wire bonding process, the common way is to use flip chip Electrical connection to save the wire-making process. But the flip-chip process requires a large number of gold balls on a single wafer, which is time consuming and affects the packaging efficiency. In addition to the flip chip method, there are some packages that do not need to be wired. In a manner such as flipping the wafer, the electrode on the surface of the wafer is directly adhered to the electrode on the carrier without using a gold ball. In this way, the electrode on the surface of the wafer is made to be "high" and has excellent flatness, and the manufacturing precision is relatively high. The process is more difficult. Another way is to adjust the structure of the wafer so that the wafer electrode extends from the wafer surface to the bottom surface of the wafer. For example, the crystal disclosed in the patent publication (10) is still disclosed. The manufacturing method, as shown in FIG. 2 and FIG. 3, is to open the hole 94 on the wafer 94 to make the conductive layer %, so that the conductive layer % passes the opening 941 to the electrode % of the surface of the wafer 94 and the bottom of the wafer %. The connection is such that the electrode 94 of the wafer 94 can be located at the bottom surface thereof. (4) In the case of 201032349 JP2008-130875, the wall surface defining the opening 941 is a vertical wall surface, and there is a disadvantage of poor step coverage when plating the conductive layer. It is easy to cause the conductive layer to be uneven and affect the conductivity.
為了解決前述的問題，本發明利用在發光二極體晶片 兩側形成傾斜侧壁’藉由傾斜側壁產生的斜面，可使導電 層容易在斜面上均勻沉積，以避免階梯覆蓋性不良的缺點 ，並藉由斜面上的導電層，將發光二極體晶片表面的電極 延伸至晶片的基板兩側或是基板的底面，有利於後續的封 裝製程’更甚者’ +需使用到打線’可減小封装結構的體 積0 進一步地，本發明亦提供利用半導體製程技術的反射 杯的製法及發光二極體的封農方法，可應用於系統封裝或 晶圓級封裝《本發明反射杯的製法僅需利用—次光罩製程 即可完成具有反射層的凹槽結構’相較於f知製程需要兩 道光罩製程’能夠減少製程時間及製作成本。而本發明提 供的封裝方法不需要打線製料可與封裝載板的導線形成 電連接’不僅能夠節省製程時間’增進生產效率，還能縮 小封裝結構的體積。 更進一步地，本發明還提供一種能夠將發光二極體晶 片的電極延伸至封裝載板的底面之封裝方法，且不需在反 射杯中開孔’以避免破壞密封晶片的效果，可解決-般由 反射杯底部開孔以將電極 ^ B r 延伸至封裝載板底部所導致晶片 又朝以及封裝結構的結構脆弱的問題而其所製成的 201032349 封裝結構可直接設置於一應用產品的電路板，不需使用打 線製程，除可減少因斷線造成的不良率，提升封裴可靠度 ’還可使下游應用端的組裝程序更加簡便。 本發明所提供的發光二極體晶片’藉由斜面單元使連 接電極之導電層延伸至基板傾斜壁或底面，可將發光二極 體晶片固設於封裝載板中直接形成電連接，或利用金屬化 製程製作延伸導電層形成電連接，由於不需要打線製程， 有助於晶圓級封裝或系統封裝，而能節省一 一打線的封裝 時間，以及節省打線所佔用的空間以縮小體積，對於整合 其他光電兀件具有小型化優勢，且與其他LED技術整合， 例如奈米晶體製程的整合，也較為彈性。此外’本發明所 提供的發光二極體晶片的製法，藉由形成傾斜侧壁及基板 傾斜壁，以在其斜面上利用金屬化製程沉積導電層，相較 於在垂直面上沉積導電層容易控制，故能提昇製程良率， 降低製造成本。 本發明所提供的用於發光二極體封裝之反射杯的製法 ’藉由部分凸伸於凹槽巾之保護層的屏蔽，使被覆於凹槽 的金層層未超出凹槽開口’而能省去一道光罩製程以降 低製程時間及成本。 本發明提供之發光二極體的封裝方法，可在同 、 ^你I 口J 一河j 載板上完成多數個發光二極體晶片的封裝，亦可不需要: 線製程，故更能適用於晶BJ級封裝或系統封裝，依^不丨 的發光二極體晶片結構可選擇適用的方法步驟將連接, 片電極的導電層延伸出反射杯外’進—步地，還能由反: 201032349 杯外延伸至封裝載板底面，以維持晶片密封的完整性，使 本發明之封裝方法不僅能夠節省封裝製程時間及縮小封裝 結構的體積，還能方便下游應用端的組裝程序。 【實施方式】 有關本發明之前述及其他技術内容、特點與功效，在 以下配合參考圖式之五個較佳實施例的詳細說明中，將可 清楚的呈現。 在本發明被詳細描述之前，要注意的是，在以下的說 〇 明内容中，類似的元件是以相同的編號來表示。 資施例1 發光二極體晶片的智柞 參閱圖4(a)〜圖4(f)，說明本發明發光二極體晶片的製 法之實施例1的實施步驟流程圖。其實施步驟包含： 如圖4(a)所示’取一已完成磊晶結構的母片1〇,母片 1〇包括一基板11及一形成於基板u上的磊晶層單元12。 磊晶層單元12包括一形成於基板u上的第一型半導體層 ® 121、一形成於第一型半導體層121上的發光層122及一形 成於發光層122上的第二型半導體層123。在本實施例中， 基板11為藍寶石（sapphire)材質，厚度約35〇 μιη ;第一 型半導體層121為η型氮化鎵（n_GaN)，第二型半導體層 123為p型氮化鎵（p_GaN)。 利用半導體製程技術的圖案化製程在母片1〇上定義出 複數個預定形成一晶片的位置及預定形成兩晶片之間的凹 槽的位置（圖未示出）。以下步驟要說明如何利用蝕刻及金 201032349 屬匕製程形成各晶片的側壁及電極單元為方便說明起見 ’圖式中僅不出兩個相鄰晶片之間的實施過程。如圖4⑻所 不’在預定形成凹槽21的位置利用蝕刻製程由第二型半導 體層123#刻至部分第—型半導體層⑵，使第—型半導體 層12曰1裸露’而形成一開口往外擴張的凹槽2卜也就是說 在各晶片1之—側形成由第二型半導體層123侧往下延伸 至部分第一型半導體層121侧的一第一斜面η卜如圖4⑷ 所不’再於介於兩晶片1中間之凹槽底部，即第一型半 導體層121的部分裸露表面，定義一第二凹槽^的位置， 然後姓刻第-型半導體層121至基板u表面形成一開口往 外擴張的第二凹槽22’而使基板u的部分表面裸露藉此 在各晶片1之一侧形成位於第一型半導體層側邊並相 鄰基板11的-第二斜面132及—連接於第—斜面131與第 二：面132的平台133，而第-斜面131、第二斜面132及 平台133即形成蟲晶層單元12之—往下並往外傾斜的傾斜 側壁13。各晶片1之磊晶層單元12的另一側亦由另一組凹 槽21及第二凹槽22形成一往下並往外傾斜的傾斜侧壁13 。前述蚀刻製程可利用乾式姓刻或濕式㈣，可依據蟲晶 ^單元，12的材質選用適#祕刻方式，此為本發明領域的 公知技術’於此不再贅述。值得注意的是，前述形成凹槽 21與第二凹槽22的實施步驟僅為實施方式的一種，其亦可 利用不同光阻厚度或半色調網點（halft〇ne)製程同時定義 出凹槽21與第二凹槽22的位置’並可利用一次蝕刻步驟 或兩次钮刻步驟形成凹槽21與第二凹槽22，不以本實施例 201032349 為限。 如圖4(d)所示，在第二凹槽22底部即裸露的基板u &面㈣$成—開口往外擴張的基板凹槽23，藉此於基 板凹槽23兩侧的晶片！分別形成一與其相鄰的傾斜侧壁13 同向傾斜的基板傾斜壁14。同樣地，各晶片i的基板η之 另：側同時形成另一基板凹肖23，並形成另_與其相鄰的 ^斜側壁13同向傾斜的基板傾斜壁14。此處蚀刻製程同樣 可利用乾式蝕刻或濕式蝕刻，在本實施例中是利用濕式 J方式以磷酸與水混合並加熱作為钮刻液蚀刻基板j j ，使基板傾斜壁14的傾斜角約介於40〜60度。 如圖4(e)所不，利用金屬化製程於各晶片丨上形成二 電極單几分別為一與第一型半導體$⑵形成電連接之 第電極單疋151，及一與第二型半導體層123形成電連接 之第一電極單元152。第一電極單元151包括一設於其中一 傾斜側壁13之平台133表面之電極15U，及一由電極1511 沿相鄰的第二斜面132延伸至基板傾斜壁Μ上的導電層 1512。第二電極單元152包括一設於第二型半導體層I。 表面之電極152卜及-由電極1521沿另一傾斜側壁13延 伸至基板傾斜壁14上的導電層1522。而且第二電極單元 152的導電層1522與對應的傾斜侧壁13之間先形成有一絕 緣層153，以避免第一電極單元151與第二電極單元152短 路。第一電極單元151與第二電極單元152在晶片i上的 分佈可配合參閱圖5的俯視圖。在形成電極1521前，亦可 在第二型半導體層123表面被覆透明電極，如氧化銦錫 201032349 (ITO)膜（圖未示出）以増加導電均勻性。 如圖4(f)所示，研磨位於磊晶層單元12相反側的基板 11之底面111，將各基板凹槽23磨穿，使各基板傾斜壁14 上的導電層1512、1522露出底面1U。在本實施中，研磨 後的基板11厚度約為50〜1〇〇 。之後，切割母片1〇以形 成多數個獨立的晶片1。 發光二極艚晶Η 如圖6所示，前述步驟製得之晶片丨為本發明發光二 極體晶片之實施例1 ’包含：一基板U、一磊晶層單元12 ◎ 、二斜面單元16及二電極單元151、152。基板u具有一 表面112及一底面ill。磊晶層單元12位於基板u的表面 112，並包括一第一型半導體層121、一發光層122及一第 二型半導體層123，第一型半導體層121位於基板u表面 112,且發光層122位於第一型半導體層121與第二型半導 體層123之間。二斜面單元16分別位於兩對側邊各斜面 單凡16係由磊晶層單元12朝基板u的底面Ul方向往下 並在外傾斜，各包括位於蟲晶層單元丨2之一傾斜侧壁13，❹ 及位於基板11之一基板傾斜壁14。各傾斜側壁13還包括 一由第二型半導髏層123側往下延伸至部分第一型半導體 層121側的第一斜面131及一相鄰基板n的第二斜面Η] ，而第一斜面131與第二斜面132之間由一平台133相連 接。二電極單元151、152分別為一與第一型半導體層121 電性連接之第一電極單元151，以及一與第二型半導體層 123電性連接之第二電極單元152。第一電極單元ΐ5ι包括 10 201032349 一設於其中一傾斜侧壁13之平台133表面的電極1511及及 一由電極1511沿相鄰的第二斜面132延伸至基板傾斜壁14 上的導電層1512。第二電極單元152包括一設於第二型半 導體層123表面之電極1521，及一由電極1521沿另一傾斜 側壁13延伸至基板傾斜壁14上的導電層1522。而且第二 電極單元152的導電層1522與對應的傾斜側壁13之間還 财-絕緣層153。此外，基板U亦可為具導電性之基板In order to solve the foregoing problems, the present invention utilizes a beveled surface formed by tilting sidewalls on both sides of a light-emitting diode wafer, so that the conductive layer can be easily deposited uniformly on the inclined surface to avoid the disadvantage of poor step coverage. And the electrode on the surface of the light-emitting diode wafer is extended to the sides of the substrate of the wafer or the bottom surface of the substrate by the conductive layer on the inclined surface, which is beneficial to the subsequent packaging process 'more even' + need to use the wire to be reduced Volume 0 of the small package structure Further, the present invention also provides a method for manufacturing a reflective cup using a semiconductor process technology and a method for sealing a light-emitting diode, which can be applied to a system package or a wafer level package. It is necessary to use the secondary mask process to complete the groove structure with the reflective layer, which requires two mask processes to reduce the process time and manufacturing cost. The packaging method provided by the present invention does not require wire bonding to form an electrical connection with the wires of the package carrier. This not only saves process time, but also increases production efficiency and reduces the size of the package structure. Furthermore, the present invention also provides a packaging method capable of extending the electrodes of the light-emitting diode wafer to the bottom surface of the package carrier, without opening the hole in the reflective cup to avoid damage to the sealing wafer, and can be solved - The 201032349 package structure can be directly disposed on the circuit of an application product by opening the bottom of the reflector cup to extend the electrode to the bottom of the package carrier, causing the wafer to be facing again and the structure of the package structure is fragile. The board does not need to use the wire-bonding process, in addition to reducing the defect rate caused by wire breakage and improving the reliability of the package, it can also make the assembly process of the downstream application end easier. The light-emitting diode chip provided by the present invention extends the conductive layer of the connection electrode to the inclined wall or the bottom surface of the substrate by the bevel unit, and the light-emitting diode chip can be fixed in the package carrier to directly form an electrical connection, or can be utilized. The metallization process produces an extended conductive layer to form an electrical connection. Since the wire bonding process is not required, it facilitates wafer level packaging or system packaging, thereby saving one-to-one wire packaging time and saving space occupied by wire bonding to reduce volume. Integrating other optoelectronic components has the advantage of miniaturization, and integration with other LED technologies, such as the integration of nano crystal processes, is also more flexible. In addition, the method for manufacturing a light-emitting diode wafer provided by the present invention is to form a conductive layer by a metallization process on the inclined surface thereof by forming the inclined sidewall and the inclined wall of the substrate, which is easier to deposit the conductive layer on the vertical surface. Control, so it can improve process yield and reduce manufacturing costs. The method for manufacturing a reflective cup for a light-emitting diode package provided by the present invention can partially shield the protective layer of the grooved towel so that the gold layer covering the groove does not exceed the groove opening' Eliminate a mask process to reduce process time and cost. The method for packaging the light-emitting diode provided by the invention can complete the packaging of a plurality of light-emitting diode chips on the same board, and does not need: the line process, so it is more suitable for the method. Crystal BJ-level package or system package, according to the illuminating diode structure, the applicable method steps can be connected, the conductive layer of the chip electrode extends out of the reflective cup, and can also be reversed: 201032349 The cup extends outside the bottom surface of the package carrier to maintain the integrity of the wafer seal, so that the packaging method of the present invention can not only save the packaging process time and reduce the volume of the package structure, but also facilitate the assembly process of the downstream application end. The above and other technical contents, features and effects of the present invention will be apparent from the following detailed description of the preferred embodiments of the invention. Before the present invention is described in detail, it is noted that in the following description, similar elements are denoted by the same reference numerals. EMBODIMENT 1 Illumination of a light-emitting diode wafer Referring to Figs. 4(a) to 4(f), a flow chart showing the steps of the first embodiment of the method for fabricating a light-emitting diode wafer of the present invention will be described. The implementation step includes: taking a master piece 1 of the completed epitaxial structure as shown in FIG. 4( a ), the mother piece 1 〇 includes a substrate 11 and an epitaxial layer unit 12 formed on the substrate u. The epitaxial layer unit 12 includes a first type semiconductor layer 121 formed on the substrate u, a light emitting layer 122 formed on the first type semiconductor layer 121, and a second type semiconductor layer 123 formed on the light emitting layer 122. . In this embodiment, the substrate 11 is made of sapphire and has a thickness of about 35 μm; the first semiconductor layer 121 is n-type gallium nitride (n-GaN), and the second semiconductor layer 123 is p-type gallium nitride ( p_GaN). A patterning process using semiconductor process technology defines a plurality of locations on the master wafer 1 that are intended to form a wafer and a location that is intended to form a recess between the wafers (not shown). The following steps will explain how to use the etching and gold 201032349 to form the sidewalls and electrode cells of each wafer. For the sake of convenience, there is only one implementation between the two adjacent wafers. As shown in FIG. 4 (8), an opening is formed by the second type semiconductor layer 123# to a portion of the first type semiconductor layer (2) by an etching process at a position where the groove 21 is formed, and the first type semiconductor layer 12曰1 is exposed to form an opening. The groove 2 extending outwardly means that a first slope η on the side of each wafer 1 extending from the side of the second-type semiconductor layer 123 to the side of the portion of the first-type semiconductor layer 121 is formed as shown in FIG. 4(4). 'At the bottom of the groove between the two wafers 1, that is, a portion of the exposed surface of the first type semiconductor layer 121, defining a position of the second groove ^, and then forming a surface of the first-type semiconductor layer 121 to the surface of the substrate u a second recess 22' that is expanded outwardly to expose a portion of the surface of the substrate u to thereby form a second slope 132 on the side of each of the wafers 1 adjacent to the first semiconductor layer and adjacent to the substrate 11. The platform 133 is connected to the first inclined surface 131 and the second surface 132, and the first inclined surface 131, the second inclined surface 132 and the platform 133 form the inclined side wall 13 which is inclined downward and outward. The other side of the epitaxial layer unit 12 of each wafer 1 is also formed by a further set of recesses 21 and second recesses 22 into a sloping side wall 13 which is inclined downward and outward. The etching process may be performed by a dry type or a wet type (4), and may be selected according to the material of the insect crystal unit 12, which is a well-known technique in the field of the invention, and will not be described herein. It should be noted that the foregoing steps of forming the recess 21 and the second recess 22 are only one of the embodiments, and the recess 21 can also be defined by using different photoresist thickness or halftone dot process. The position of the second groove 22 and the groove 21 and the second groove 22 may be formed by one etching step or two button steps, not limited to the embodiment 201032349. As shown in Fig. 4(d), at the bottom of the second recess 22, the bare substrate u & face (4) is formed into a substrate recess 23 which is expanded outward, thereby forming wafers on both sides of the substrate recess 23! A substrate inclined wall 14 which is inclined in the same direction as the adjacent inclined side walls 13 is formed, respectively. Similarly, the other side of the substrate η of each wafer i is simultaneously formed with another substrate concave 23, and another substrate inclined wall 14 which is inclined in the same direction as the adjacent oblique side wall 13 is formed. Here, the etching process can also utilize dry etching or wet etching. In this embodiment, the wet J method is used to mix phosphoric acid and water and heat as a button etching substrate jj to make the tilt angle of the substrate inclined wall 14 At 40 to 60 degrees. As shown in FIG. 4(e), a two-electrode is formed on each of the wafers by a metallization process, and each of the electrodes is a first electrode 151 electrically connected to the first type semiconductor $(2), and a second type semiconductor. Layer 123 forms a first electrode unit 152 that is electrically connected. The first electrode unit 151 includes an electrode 15U disposed on a surface of the land 133 of one of the inclined side walls 13, and a conductive layer 1512 extending from the electrode 1511 along the adjacent second inclined surface 132 to the inclined wall of the substrate. The second electrode unit 152 includes a second type semiconductor layer 1. The electrode 152 of the surface extends from the electrode 1521 along the other inclined side wall 13 to the conductive layer 1522 on the inclined wall 14 of the substrate. Further, an insulating layer 153 is formed between the conductive layer 1522 of the second electrode unit 152 and the corresponding inclined sidewall 13 to prevent the first electrode unit 151 and the second electrode unit 152 from being short-circuited. The distribution of the first electrode unit 151 and the second electrode unit 152 on the wafer i can be coordinated with reference to the top view of FIG. Before the electrode 1521 is formed, a transparent electrode such as an indium tin oxide 201032349 (ITO) film (not shown) may be coated on the surface of the second type semiconductor layer 123 to increase the uniformity of conduction. As shown in FIG. 4(f), the bottom surface 111 of the substrate 11 on the opposite side of the epitaxial layer unit 12 is ground, and the substrate recesses 23 are ground through so that the conductive layers 1512 and 1522 on the inclined walls 14 of the substrate are exposed to the bottom surface 1U. . In the present embodiment, the thickness of the substrate 11 after polishing is about 50 to 1 Å. Thereafter, the mother wafer 1 is cut to form a plurality of individual wafers 1. As shown in FIG. 6 , the wafer 制 obtained in the foregoing step is the embodiment 1 of the present invention, and includes: a substrate U, an epitaxial layer unit 12 ◎ , and two slanting units 16 . And two electrode units 151, 152. The substrate u has a surface 112 and a bottom surface ill. The epitaxial layer unit 12 is located on the surface 112 of the substrate u and includes a first type semiconductor layer 121, a light emitting layer 122 and a second type semiconductor layer 123. The first type semiconductor layer 121 is located on the surface u of the substrate u, and the light emitting layer 122 is located between the first type semiconductor layer 121 and the second type semiconductor layer 123. The two inclined surface units 16 are respectively located on the two opposite sides of each of the inclined surfaces. The 16 series is inclined downward from the epitaxial layer unit 12 toward the bottom surface U1 of the substrate u and is externally inclined, each of which includes one of the inclined side walls 13 of the crystal layer unit 丨2. And a substrate inclined wall 14 located on one of the substrates 11. Each of the inclined sidewalls 13 further includes a first inclined surface 131 extending from the side of the second type semi-conductive layer 123 to a portion of the first semiconductor layer 121 side and a second inclined surface 相邻 of an adjacent substrate n, and the first The inclined surface 131 and the second inclined surface 132 are connected by a platform 133. The two electrode units 151 and 152 are respectively a first electrode unit 151 electrically connected to the first type semiconductor layer 121, and a second electrode unit 152 electrically connected to the second type semiconductor layer 123. The first electrode unit ΐ5ι includes 10 201032349 an electrode 1511 disposed on a surface of the platform 133 of one of the inclined side walls 13 and a conductive layer 1512 extending from the electrode 1511 along the adjacent second inclined surface 132 to the inclined wall 14 of the substrate. The second electrode unit 152 includes an electrode 1521 disposed on the surface of the second type semiconductor layer 123, and a conductive layer 1522 extending from the electrode 1521 along the other inclined side wall 13 to the substrate inclined wall 14. Further, a conductive-insulating layer 153 is further provided between the conductive layer 1522 of the second electrode unit 152 and the corresponding inclined side wall 13. In addition, the substrate U can also be a conductive substrate
，若基板具有導電性時，需在基板傾斜壁上設絕緣層。在 本實施例中，基板傾斜壁14之傾斜角約介於4〇_6〇度有 利於封裝時再封裝載板上鍍製延伸導電層與導電層1512、 1522相連接，有關發光二極體晶#丨的封|方式，將於下 文中說明。 圖7(a)〜(g)說明本發明發光二極體的封裝方法之實施例 1的實施流程’其中圖7(a)〜圖7⑷還說明本發 =法。如圖7⑷所示’在—封裝餘3上形成_保護^ 再圖案化保護層31，以形成一貫穿保護層31之穿孔 3U。在本實施例巾，封裝載板3材質切，保護層31材質 ίΠ。封裝餘3亦可為其他不㈣材質，例如氮化銘 鋁等陶竞材料。保制材質也可為Si〇x、 :Nx/Sl〇x、或金屬（例如犯、—等’保護層”的形成 法可依據其材質選用，例如非金屬 iCVF»、 +一 J用氣相沉積法 L等二高溫爐製程’金屬材質可用電錢、機錄或蒸 11 201032349 如圖7(b)所不，利用蝕刻液通過穿孔311蝕刻封裝載板 3形成一開口 321大於穿孔311之凹槽32，使相鄰穿孔 3U之部分保護層31凸伸於凹槽32中。在本實施例中，蝕 刻液為KOH溶液，濃度30 ν〇ι %之K〇H溶液於8〇β(：或濃 度45vol%之KOH溶液於85°C條件下，蝕刻速率約為i 蝕刻液的選用可依據實際需求調整，不以本實施 例為限。 如圖7(c)所示，於保護層31及凹槽32上形成一金屬層 33、34,且藉由部分凸伸於凹槽32中之保護層31的屏蔽〇 ’使凹槽32相鄰保護層31處（鄰近開〇 321處）未被覆 金屬層34。金屬層33、34可藉由減鑛或蒸鍍方式沉積，材 質可為Ti/A卜Ti/Ni/Ag或其他可用以反射光線的一般常見 的反射層材質。 如圖7(d)所示，移除保護層31及位於保護層31上的金 屬層33,剩下在凹槽32中的金屬㊆34，即形成一位於凹 槽32中的反射杯34。藉由前述步驟形成的反射杯34只有 在圖案化保護層31時需用到-道光罩製程以定義穿孔3ΐι❺ 位置，再利用保護層31的屏蔽，使得鄰近凹槽32開口 321 處沒有沉積金屬層34,所以反射杯34不會超出凹槽32開 口 32卜而能省去定義反射# 34開口區域以避免超出凹槽 32開口 321的光罩製程。 如圖7⑷所示，取前述製得的一發光二極體晶片i固設 於反射杯34中。更進一步的說，發光二極體晶片i係利用 -固晶膠38固^於反射杯34内，在本實施例中固晶膠 12 201032349 38為絕緣材質’使得第一電極早元151的導電層1512斑第 一電極單元152的導電層1522與反射杯34電性分離。 再如圖7(f)所示’以金屬化製程形成二延伸導電層35 ’各延伸導電層35分別連接發光二極體晶片1之第一電極 单元151的導電層1512與第一電極單元152的導電層1522 ，且由基板傾斜壁14處連接，當然亦可由傾斜側壁η處 連接，使第一電極單元151與第二電極單元152藉由各延 伸導電層35延伸出反射杯34外的封裝載板3上，在本實 • 施例中，由於反射杯34與封裝載板3均為導電體，所以在 形成延伸導電層35之前，需先在反射杯34及封裝載板3 上預定形成延伸導電層35的位置形成一絕緣層36，以避免 延伸導電層35與反射杯34及封裝載板3接觸。如圖7(g)所 示，於反射杯34中填充透光膠材37,以密封發光二極體晶 片1。透光膠材37可含有螢光粉或不含螢光粉，視使用需 求而定。 雖然本實施例中發光二極體晶片！是設置在反射杯W 中，但是前述形成延伸導電層35的實施步驟也可適用於— 般載板’或是一般反射杯。 資施例2 曼光二極體晶片的匍作 本發明發光二極體晶片的製法之實施例2的實施步驟 與實施例1大致相同，可配合參閱圖4⑷〜圖4(f)，其差異 之處在於，如圖8所示，在研磨基板u，的底面ui，以露出 各基板傾斜壁M’的導電層1512,、1522，後，實施例2利用 13 201032349 金屬化製程在底面111’形成二分別與各基板傾斜壁14,的導 電層1512’、1522’連接的導電層1513’、1523,，使第一、第 二電極單元 151’、152’的導電層 1512，、1513，、1522，、 1523’延伸至基板11’底面111’。此外，在該金屬化製程步 驟前，亦可進一步地包含將底面111’拋光以提供一較平士曰 與光滑表面的步驟。之後，切割母片10’上的各晶片j，以形 成多數個獨立的晶片Γ。 發先~—極體晶片 如圖9所示’前述步驟製得之晶片1，為本發明發光二❹ 極體晶片之實施例2’與實施例1大致相同，其所差異之處 在於，實施例2的第一電極單元151’含包括一延伸於基板 11’底面111’的導電層1513，，且第二電極單元152,含包括 一延伸於基板11’底面11Γ的導電層1523，。 發光二極體的封裝 圖10(a)〜(c)說明本發明發光二極體的封裝方法之實施 例2的實施流程，用以封裝前述之發光二極體晶片Γ。 如圖10(a)所示，先於反射杯34,中定義預定設置發光⑩ 二極體晶片Γ底面111’之二導電層1513’、1523,的位置（ 圖未標號），並利用金屬化製程形成二延伸導電層35，，使 各延伸導電層35,分別由各導電層1513，、1523,之預定位置 延伸至反射杯34’外的封裝載板3,上。在本實施例中，形成 反射杯34’的實施步驟與實施例1相同，可參閱圖7(a)〜圖 7(d)。由於反射杯34,與封裝載板3,均為導電體，所以在形 成延伸導電層35,之前’需先在反射杯34,及封裝載板3,上 14 201032349 預定形成延伸導電層35,的位置形成—絕緣層％，，以避免 延伸導電層35’與反射杯34,及封裝載板3,接觸。 如圖10(b)所示，將一發光二極體晶片j，固設於反射 杯34’中，並使二導電層1513，、1523,分別與相對應之各延 伸導電層35’電連接。 如圖10(c)所示，於反射杯34’中填充透光膠材37，，以 密封發光二極體晶片1，。透光膠材37，可含有螢光粉或不含 螢光粉’視使用需求而定。 • 雖然本實施例中發光二極體晶片1，是設置在反射杯34, 中，但是前述形成延伸導電層35,再與發光二極體晶片丨，相 接的實施步驟也可適用於一般載板，或是一般反射杯。 資施例3 圖11(a)〜圖11(f)說明本發明發光二極體封裝方法的實 施例3。 如圖11(a)所示，先分別在一封裝載板41的正面411及 背面412被覆一保護層42’再圖案化保護層42形成複數穿 © 孔421、422，以定義預訂設置反射杯的凹槽位置421，及 分別位於凹槽位置421兩侧預定設置穿槽44 (參閱圖u(b) )的穿槽位置422。位於正面411與背面412的穿槽位置 422上下相對應。如圖11 (b)所示，再利用姓刻液姓刻封裝 載板41，通過保護層42的穿孔421在封裝載板41正面411 形成一預定設置反射杯471 (參閱圖11(c))的凹槽43,使 凹槽43的開口 431大於穿孔421，並且通過各穿孔422由 封裝載板41的正面411及背面412相對蝕刻而形成二分別 15 201032349 鄰近凹槽43❾穿槽44。藉由每一穿槽44形成其相鄰兩封 裝結構4的侧壁45 ’且各側壁45具有一由封裝載板41正 面411住中間外傾的上傾斜面451及—由封裝載板^背面 412往中間外傾的下傾斜面452。在本實施例中，封裝載板 41的材質為矽’保護層42的材質及蝕刻方式可參照實施例 1，於此不再重述。 如圖11(c)所示，再由封裝載板41正面411沉積一金屬 層47,使凹槽43及各穿槽44的上傾斜面451被覆金屬層 47，其中凹槽43與保護層42相鄰處未被覆金屬層47 ,而◎ 於凹槽43内形成一反射杯471。 如圖ii(d)所示，移除封裝載板41正面411與背面412 的保護層42，由於本實施例之封裝載板41具有導電性，移 除保護層42後，由封裝載板41的正面411與背面412沉積 絕緣層46。 如圖11(e)所示’利用金屬化製程在封裝載板41的背面 412形成具有預定圖案的導電層48，包括二分別由封裝載 板41背面412延伸至各下傾斜面452的下導電層481，及⑩ 一位於封裝載板41背面412的傳導區482，傳導區482可 供與外部散熱裝置（圖未示出）導接。或者，導電層48亦 可由lift-off製程製作。 如圖11(f)所示，取如實施例1所述的發光二極體晶片 1固設於反射杯471中，配合參閱圖7(e)〜圖7(g)所述的步 驟’本實施例3進一步使實施例1中的延伸導電層35延伸 至各上傾斜面451形成二上導電層483，各上導電層483分 16 201032349 別與相對應的各下導電層481相連接且分別與第一電極單 兀151及第二電極單元152電連接，使第一、第二電極單 元151、152可延伸至封裝載板41的背面412。再於反射杯 471中填充-透光膠材49將發光二極體晶片}密封以形 成-封裝結構4。透光㈣49可視需求含有螢光粉或不含 勞光粉。前述實施步驟可在同一封裝載板41 ±完成多數個 封裝結構4，經由切割後可製得多數個獨立的封裝結構4， 各獨立的封裝結構4可直接設置於—制產品的電路板（ 參 圖未示出），不需使用打線製程，而方便下游應用端的組裝 程序。 實施例3的封裝方式利用在反射杯471外部的穿槽 使上導電$ 483與下導電層481相連接，可避免破壞發 光二極鳢晶>ί 1的密封性，而且上導電層483與下導電層 481分別形成在上傾斜面451與下傾斜面452，藉由斜面可 使金屬層容易沉積，而能提昇製程良率。 ❿ 實施例4 實施例4係封裝發光二極體晶片丨，（參閲圖9)的另一 實施方S，·其f施步辣部分與實施们时施步驟相同， 參閱圖11⑷〜圖11⑷。接著參閱圖12(a)，利用金屬化製程 在封裝載板41的背面412形成具有預定圖案的導電層48， 包括二分別由封裝載板41背面412延伸至各下傾斜面452 的下導電層48卜及-位於封裝載板41背面412的傳導區 482’傳導！I 482可供與外部散熱裝置（圖未示出）導接。 17 201032349 並且於反射杯471中定義預定設置發光二極體晶片1，底面 之第一、第二電極單元151，、152,的導電層1513，、1523,之 位置，再利用金屬化製程形成二上導電層483，，使各上導 電層483’分別由第一、第二電極單元151’、152’之預定位 置（圖未標號）延伸至各上傾斜面451，而與各下導電層 481相連接。同樣地，導電層48及上電導電層483,亦可利 用lift-off製程製作。 參閱圖12(b)，固設發光二極體晶片1’於反射杯471中 ’並使二導電層1513’、1523,分別與相對應之各上導電層❹ 483’電連接，亦即，使各上導電層483,分別與相對應之第 一、第二電極單元151’、152’電連接。再於反射杯471中填 充透光穋材49 ’以密封發光二極體晶片1，^透光膠材49可 含有螢光粉或不含螢光粉，視使用需求而定。 實施例5 圖13(a)〜圖13(h)說明本發明發光二極體封裝方法的實 施例5的實施步驟。實施例5的實施步驟可用於封裝一般 電極位於正面的發光二極體晶片5。 Λ 參閱圖13(a)及圖13(b)，其實施步驟與實施例3的圖 11(a)與圖11(b)大致相同，在封裝載板41上形成—凹槽 與二穿槽44,惟，保護層42與封裝基板41之間還有一絕 緣層46。 ' 氧化形 金屬層 參閱圖13(c)，將凹槽43及穿槽44的裸露表面 成氧化層以作為絕緣層46，。 參閱圖13(d)，再由封裝載板41正面411沉積一 18 201032349 47 ’使凹槽43及各穿槽44的上傾斜面451被覆金屬層ο ，其中凹槽43與保護層42相鄰處未被覆金屬層47,而於 凹槽43内形成一反射杯471。 參閱圖13(e)，移除封裝載板41正面4丨1與背面々I]的 保護層42，並利用金屬化製程在封裝載板41的背面Μ]形 成具有預定圖案的導電層48,包括二分別由封裝載板Μ背 面412延伸至各下傾斜面452的下導電層481，及一位於封 裝載板41背面412的傳導區482，傳導區482可供與外部 Φ 散熱裝置（圖未示出）導接。 參閱圖13(f)，將一發光二極體晶片5固設在反射杯 471中，設置二導電塊51於該發光二極體晶片5的二電極 上（圖未標號），其中在發光二極體晶片5的各電極上分別 設置一導電塊51，使該等導電塊51凸出反射杯471外。在 本實施例中’各導電塊51為高度約50〜ΙΟΟμπι之金球。雖 然本實施例是先固設發光二極體晶片5再設置導電塊51， 但是也可以先設置導電塊51後，再將發光二極體晶片5固 ® 設於反射杯471中，但結合該二導電塊51之該發光二極體 晶片5之整體高度需高出該反射杯471深度。 如圖13(g)所示，於反射杯471中填充透光膠材49以密 封發光二極體晶片5。透光膠材49可視需求含有螢光粉或 不含螢光粉。 如圖13(h)所示，待透光膠材49固化後研磨其表面，並 使該等導電塊51部分裸露於透光膠材49表面。也就是說 ，該等導電塊51之裸露表面的位置高於反射杯471開口的 19 201032349 位置。配合參閱圖14，再以金屬化製程形成分別連接各導 電塊51並延伸至上傾斜面451的二上導電層483”，使各上 導電層483”分別與各電極電連接，且各上導電層483”分別 與相對應的下導電層481連接。之後步驟與實施例3相同 ’經由切割可行成多數個獨立的封裝結構4,。 前述圖13(f)〜圖13(h)所示的步驟亦可適用一般的反射 杯。如圖15所示，當反射杯61設在一般封裝載板6時， 前述二上導電層483”即為延伸出反射杯61開口外的封裝載 板6表面之延伸導電層62,延伸導電層62可供與外部電極❹ (圖未示出）電連接。 歸納上述，本發明所提供的發光二極體晶片1、丨，的製 法’其係藉由形成傾斜侧壁13及基板傾斜壁14，以在其斜 面上利用金屬化製程沉積導電層1512、1512,，相較於在垂 直面上沉積導電層容易控制，故能提昇製程良率，降低製 造成本。 此外，本發明所提供的發光二極體晶片1、丨，，藉由斜 面單元16、16’使連接電極1511、1521、1511，、1521，之導⑩ 電層1512、1522、1512’、1522’延伸至基板傾斜壁14,拉 近導電層1512、1522、1512,、1522’與提供外部電性連接之 延伸導電層35、35’間距離，減少斷線的可能。 更進一步的說，本發明之發光二極體晶片1，藉由斜面 單元16使連接電極1511、1521之導電層1512、1522延伸 至基板傾斜壁14，而發光二極體晶片1，之導電層ι513，、 1523’延伸至基板11’底面m，，再利用金屬化製程製作延 20 201032349 伸導電層35、35’與發光二極體晶片，形成電連接，則 二需要打線製程’適用於晶圓級封裝或系統封裝，而能節 省打線的封裝時間，以及節省打線所佔用的空間以縮 J體積#於整合其他光電元件具有小型化優勢且與其 他LED技術整合，例如奈米晶體製程的整合，也較為彈性 〇 由實施例1〜實施例5所述的實施步驟可知，本發明提 #之發光二極體的封裝方法不需要打線製程，能適用於晶 ® 圓級封裝或系統封裝，依據不同的發光二極體晶片1、Γ、 5結構可選擇適用的方法步驟。進—步地，如實施例3〜實 施例5所述，還能形成可直接設置於一應用產品的電路板 之封裝結構4、4’ ’不需使用打線製程，不僅能夠節省封裝 製程時間及縮小封裝結構4、4’的趙積’還能方便下游應用 端的組裝程序。 此外，如圖7⑷部）、_)、11⑷七⑷、12⑷與 U⑷_13⑷所不之封裝方法、封裝載板架構與反射杯架構， 並不限定僅適用於本發明所揭露之發光二極體晶# ι、卜 亦可應用於一般發光二極體晶片。 惟以上所述者，僅為本發明之較佳實施例而已，當不 能以此限定本發明實施之範圍，即大凡依本發明申請專利 範圍及發明說明内容所作之簡單的等效變化與修飾，皆仍 屬本發明專利涵蓋之範圍内。 【圖式簡單說明】 圖1是一不意、圖，說明一習知的發光二極體晶片； 21 201032349 圖2是一俯視圖，說明日本專利公開案jp2〇〇813〇875 所揭示的一發光二極體晶片； 圖3是一圖2的截面圖； 圖4(a)〜圖4(f)是說明本發明發光二極體晶片的製法之 實施例1的實施步驟流程圖； 圖5是一圖4(f)的俯視圖，說明實施例i的二電極單元 的位置； 圖6是一示意圖，說明本發明發光二極體晶片之實施 例1 ; 圖7(a)〜圖7(g)是說明本發明發光二極體封裝方法之實 施例1的實施步驟流程圖； 圖8是接續圖4(a)〜圖4(f)的流程圖，說明本發明發光 二極體晶片的製法之實施例2的實施步驟； 圖9是一示意圖’說明本發明發光二極體晶片之實施 例2 ; 圖10(a)〜圖l〇(c)是接續圖7(a)〜圖7(d)的流程圖說明 本發明發光二極體封裝方法之實施例2的實施步驟； 圖11(a)〜圖11(f)是說明本發明發光二極鱧封裝方法之 實施例3的實施步驟流程圖； 圖12(a)〜圖12(b)是接續圖11(a)〜圖11(d)的流程圖說 明本發明發光二極體封裝方法之實施例4的實施步驟； 圖13(a)〜圖13(h)是說明本發明發光二極體封震方法之 實施例5的實施步驟流程圖； 圖14是一圓13(h)的俯視圖，說明實施例5的上導電層 22 201032349 的位置；及 圖15是一示意圖，說明實施例5之發光二極體晶片的 另一封裝態樣。If the substrate has electrical conductivity, an insulating layer is provided on the inclined wall of the substrate. In this embodiment, the tilt angle of the substrate inclined wall 14 is about 4〇_6〇, which is beneficial for the connection of the plated extended conductive layer and the conductive layers 1512 and 1522 on the repackage carrier. The way of the seal of the crystal #丨 will be explained below. Fig. 7 (a) to (g) illustrate the execution flow of the first embodiment of the package method of the light-emitting diode of the present invention, wherein Fig. 7(a) to Fig. 7(4) also illustrate the present invention. As shown in Fig. 7 (4), a protective layer 31 is formed on the package 3 to form a through hole 3U penetrating the protective layer 31. In the towel of this embodiment, the material of the package carrier 3 is cut, and the material of the protective layer 31 is Π. The remaining package 3 can also be other materials that are not (4), such as nitrite materials such as nitriding aluminum. The protective material can also be Si〇x, :Nx/Sl〇x, or metal (for example, the 'protective layer' of the sin, etc. can be selected according to its material, such as non-metal iCVF», +J Deposition method L and other two high-temperature furnace process 'metal material can be used for electricity, machine recording or steaming 11 201032349 As shown in Figure 7 (b), etching the package carrier 3 through the perforation 311 using an etching solution to form an opening 321 larger than the perforation 311 The groove 32 is such that a part of the protective layer 31 of the adjacent perforation 3U protrudes into the groove 32. In the embodiment, the etching solution is a KOH solution, and the concentration of 30 〇 〇 % of the K 〇 H solution is 8 〇 β (: Or the concentration of 45 vol% of the KOH solution at 85 ° C, the etching rate is about i. The etching solution can be adjusted according to actual needs, not limited to this embodiment. As shown in Figure 7 (c), in the protective layer 31 And forming a metal layer 33, 34 on the groove 32, and the shielding layer 部分' of the protective layer 31 partially protruding in the groove 32 causes the groove 32 to be adjacent to the protective layer 31 (near the opening 321) The metal layer 34 is coated. The metal layers 33, 34 can be deposited by means of reduced or evaporated, and the material can be Ti/A, Ti/Ni/Ag or other materials for reflection. The common reflective layer material of the wire. As shown in Fig. 7(d), the protective layer 31 and the metal layer 33 on the protective layer 31 are removed, and the metal VII 34 remaining in the recess 32 is formed to be concave. The reflective cup 34 in the groove 32. The reflective cup 34 formed by the foregoing steps only needs to use a mask process to define the position of the perforation 3 ΐ ❺ when patterning the protective layer 31, and then use the shielding of the protective layer 31 so that the adjacent groove There is no metal layer 34 deposited at the opening 321 of the opening 32, so that the reflecting cup 34 does not extend beyond the opening 32 of the recess 32, and the masking process for defining the opening area of the reflection #34 can be omitted to avoid the reticle process beyond the opening 321 of the recess 32. As shown in Fig. 7(4) The light-emitting diode wafer i is fixed in the reflective cup 34. Further, the light-emitting diode wafer i is fixed in the reflective cup 34 by using the solid-solid glue 38. In the embodiment, the solid crystal adhesive 12 201032349 38 is an insulating material such that the conductive layer 1522 of the first electrode unit 152 of the first electrode 151 is electrically separated from the reflective cup 34. Further, as shown in FIG. 7(f) Showing the extension of each of the two extended conductive layers 35' formed by a metallization process The layer 35 is connected to the conductive layer 1512 of the first electrode unit 151 of the LED chip 1 and the conductive layer 1522 of the first electrode unit 152, respectively, and is connected by the inclined wall 14 of the substrate, and of course, may be connected by the inclined sidewall η. The first electrode unit 151 and the second electrode unit 152 extend from the package carrier 3 outside the reflective cup 34 by the respective extended conductive layers 35. In the embodiment, the reflective cup 34 and the package carrier 3 are both Conductor, so before forming the extended conductive layer 35, an insulating layer 36 is formed on the reflective cup 34 and the package carrier 3 to form an extended conductive layer 35 to avoid extending the conductive layer 35 and the reflective cup 34 and the package. The carrier 3 is in contact. As shown in Fig. 7(g), the reflective cup 34 is filled with a light-transmitting adhesive 37 to seal the light-emitting diode wafer 1. The light-transmitting adhesive 37 may contain phosphor powder or no phosphor powder, depending on the needs of use. Although the light emitting diode chip in this embodiment! It is disposed in the reflective cup W, but the aforementioned step of forming the extended conductive layer 35 can also be applied to a general carrier plate or a general reflective cup. The second embodiment of the method for fabricating a light-emitting diode wafer of the present invention is substantially the same as that of the first embodiment, and can be referred to FIG. 4(4) to FIG. 4(f). As shown in FIG. 8, after polishing the bottom surface ui of the substrate u to expose the conductive layers 1512, 1522 of the substrate inclined walls M', the second embodiment is formed on the bottom surface 111' by the 13 201032349 metallization process. Two conductive layers 1513', 1523 connected to the conductive layers 1512', 1522' of the substrate inclined walls 14, respectively, to make the conductive layers 1512, 1513, 1522 of the first and second electrode units 151', 152' , 1523' extends to the bottom surface 111' of the substrate 11'. In addition, prior to the metallization process, a step of polishing the bottom surface 111' to provide a flattened surface and a smooth surface may be further included. Thereafter, each wafer j on the mother sheet 10' is cut to form a plurality of individual wafer cassettes. The wafer 1 obtained by the above steps is the same as the first embodiment of the present invention. The embodiment 2' of the present invention is substantially the same as the first embodiment except that the implementation is performed. The first electrode unit 151' of the example 2 includes a conductive layer 1513 extending from the bottom surface 111' of the substrate 11', and the second electrode unit 152 includes a conductive layer 1523 extending from the bottom surface 11 of the substrate 11'. The package of the light-emitting diodes Fig. 10 (a) to (c) illustrate the implementation flow of the second embodiment of the package method of the light-emitting diode of the present invention for packaging the above-described light-emitting diode wafer cassette. As shown in Fig. 10 (a), prior to the reflector cup 34, the position (not shown) of the two conductive layers 1513', 1523 of the bottom surface 111' of the light-emitting 10 diode wafer is defined, and metallization is utilized. The process forms two extended conductive layers 35 such that each of the extended conductive layers 35 extends from a predetermined position of each of the conductive layers 1513, 1523 to the package carrier 3 outside the reflective cup 34'. In the present embodiment, the steps of forming the reflecting cup 34' are the same as those of the first embodiment, and reference is made to Figs. 7(a) to 7(d). Since the reflective cup 34 and the package carrier 3 are both electrically conductive, before the formation of the extended conductive layer 35, it is necessary to form the extended conductive layer 35 on the reflective cup 34 and the package carrier 3, upper 14 201032349. The position is formed - the insulating layer %, to prevent the extended conductive layer 35' from coming into contact with the reflective cup 34, and the package carrier 3. As shown in FIG. 10(b), a light-emitting diode chip j is fixed in the reflective cup 34', and the two conductive layers 1513, 1523 are electrically connected to the corresponding extended conductive layers 35', respectively. . As shown in Fig. 10(c), the reflective cup 34' is filled with a light-transmitting adhesive 37 to seal the light-emitting diode wafer 1. The light-transmitting adhesive 37 may contain fluorescent powder or no fluorescent powder depending on the needs of use. • Although the light-emitting diode chip 1 is disposed in the reflective cup 34 in the present embodiment, the step of forming the extended conductive layer 35 and then contacting the light-emitting diode wafer is also applicable to the general load. Board, or a general reflector cup. EMBODIMENT 3 Fig. 11(a) to Fig. 11(f) illustrate a third embodiment of the method of packaging a light-emitting diode of the present invention. As shown in FIG. 11(a), a protective layer 42' is respectively coated on the front surface 411 and the back surface 412 of a loading plate 41, and the protective layer 42 is patterned to form a plurality of holes 421, 422 to define a predetermined reflective cup. The groove position 421 and the grooved position 422 of the groove 44 (see FIG. u(b)) are respectively disposed on both sides of the groove position 421. The front surface 411 corresponds to the grooved position 422 of the back surface 412. As shown in FIG. 11(b), the carrier plate 41 is packaged by the surname of the surname, and a predetermined reflective cup 471 is formed on the front surface 411 of the package carrier 41 through the through hole 421 of the protective layer 42 (see FIG. 11(c)). The groove 43 is such that the opening 431 of the groove 43 is larger than the through hole 421, and is etched by the front surface 411 and the back surface 412 of the package carrier 41 through the respective through holes 422 to form two respectively, respectively, 15201032349 adjacent to the groove 43. The sidewalls 45' of the two adjacent package structures 4 are formed by each of the through slots 44, and each of the sidewalls 45 has an upper inclined surface 451 which is tilted by the front surface 411 of the package carrier 41 and is backed by the package carrier 412 is a downwardly inclined surface 452 that is outwardly inclined toward the center. In the present embodiment, the material of the package carrier 41 and the etching method of the material of the protective layer 42 can be referred to the embodiment 1, and will not be repeated here. As shown in FIG. 11(c), a metal layer 47 is further deposited on the front surface 411 of the package carrier 41, so that the recess 43 and the upper inclined surface 451 of each of the slots 44 are covered with a metal layer 47, wherein the recess 43 and the protective layer 42 are provided. The adjacent portion is not covered with the metal layer 47, and ◎ a reflective cup 471 is formed in the recess 43. As shown in FIG. ii(d), the protective layer 42 of the front surface 411 and the back surface 412 of the package carrier 41 is removed. Since the package carrier 41 of the embodiment has conductivity, after the protective layer 42 is removed, the package carrier 41 is removed. An insulating layer 46 is deposited on the front side 411 and the back side 412. As shown in FIG. 11(e), a conductive layer 48 having a predetermined pattern is formed on the back surface 412 of the package carrier 41 by a metallization process, including two lower conductive layers respectively extending from the back surface 412 of the package carrier 41 to the respective lower inclined surfaces 452. Layers 481, and 10 are located in a conductive region 482 on the back side 412 of the package carrier 41, and the conductive region 482 is adapted to be coupled to an external heat sink (not shown). Alternatively, conductive layer 48 can also be fabricated by a lift-off process. As shown in FIG. 11(f), the light-emitting diode wafer 1 as described in the first embodiment is fixed in the reflective cup 471, and the steps described in FIG. 7(e) to FIG. 7(g) are referred to. Embodiment 3 further extends the extended conductive layer 35 of Embodiment 1 to each of the upper inclined faces 451 to form two upper conductive layers 483, and each of the upper conductive layers 483 and 16 201032349 are connected to the corresponding lower conductive layers 481 and respectively The first electrode unit 151 and the second electrode unit 152 are electrically connected to the first electrode unit 151 and 152 so as to extend to the back surface 412 of the package carrier 41. The light-filling paste 49 is then filled in the reflective cup 471 to seal the light-emitting diode wafer to form a package structure 4. Light transmission (4) 49 may contain fluorescent powder or no polishing powder depending on the requirements. The foregoing implementation steps can complete a plurality of package structures 4 on the same package carrier 41. After cutting, a plurality of independent package structures 4 can be fabricated, and the individual package structures 4 can be directly disposed on the circuit board of the product (see The figure is not shown), and the assembly process of the downstream application end is convenient without using a wire bonding process. The packaging method of Embodiment 3 utilizes the through-groove outside the reflective cup 471 to connect the upper conductive $483 to the lower conductive layer 481, thereby avoiding the destruction of the sealing property of the light-emitting diode, and the upper conductive layer 483 and The lower conductive layer 481 is formed on the upper inclined surface 451 and the lower inclined surface 452, respectively, and the metal layer can be easily deposited by the inclined surface, thereby improving the process yield.实施 Embodiment 4 Embodiment 4 is a package of a light-emitting diode wafer 丨, (see FIG. 9) another embodiment S, wherein the step of applying the spicy portion is the same as that of the embodiment, and referring to FIG. 11 (4) to FIG. 11 (4) . Referring next to FIG. 12(a), a conductive layer 48 having a predetermined pattern is formed on the back surface 412 of the package carrier 41 by a metallization process, including two lower conductive layers extending from the back surface 412 of the package carrier 41 to the respective lower inclined surfaces 452, respectively. 48b - the conduction zone 482' located on the back side 412 of the package carrier 41 is conducted! The I 482 can be interfaced with an external heat sink (not shown). 17 201032349 and defining, in the reflective cup 471, the positions of the conductive layers 1513, 1523 of the first and second electrode units 151, 152 of the bottom surface of the light-emitting diode wafer 1, and the metallization process are formed. The upper conductive layer 483 is extended from the predetermined positions (not labeled) of the first and second electrode units 151', 152' to the respective upper inclined surfaces 451, and to the respective lower conductive layers 481, respectively. Connected. Similarly, the conductive layer 48 and the electrically conductive layer 483 can also be fabricated using a lift-off process. Referring to FIG. 12(b), the LED chip 1' is fixed in the reflective cup 471 and the two conductive layers 1513' and 1523 are electrically connected to the corresponding upper conductive layers ❹ 483', that is, Each of the upper conductive layers 483 is electrically connected to the corresponding first and second electrode units 151', 152', respectively. The light-transmissive coffin 49 is filled in the reflective cup 471 to seal the light-emitting diode wafer 1. The light-transmitting adhesive 49 may contain phosphor powder or no phosphor powder, depending on the needs of use. Embodiment 5 Figures 13(a) to 13(h) illustrate the implementation steps of Embodiment 5 of the light-emitting diode packaging method of the present invention. The implementation steps of Embodiment 5 can be used to package a light-emitting diode wafer 5 having a general electrode on the front side. 13(a) and 13(b), the implementation steps are substantially the same as those of FIG. 11(a) and FIG. 11(b) of the third embodiment, and a groove and a second groove are formed in the package carrier 41. 44. However, there is an insulating layer 46 between the protective layer 42 and the package substrate 41. 'Oxidized Metal Layer Referring to Fig. 13(c), the exposed surface of the groove 43 and the through groove 44 is an oxide layer as the insulating layer 46. Referring to FIG. 13(d), an 18, 201032349 47' is deposited from the front surface 411 of the package carrier 41 such that the recess 43 and the upper inclined surface 451 of each of the slots 44 are covered with a metal layer ο, wherein the recess 43 is adjacent to the protective layer 42. The metal layer 47 is not covered, and a reflective cup 471 is formed in the recess 43. Referring to FIG. 13(e), the protective layer 42 of the front surface 丨1 and the back surface 々I] of the package carrier 41 is removed, and a conductive layer 48 having a predetermined pattern is formed on the back surface of the package carrier 41 by a metallization process. The second conductive layer 481 extends from the back surface 412 of the package carrier 412 to the lower inclined surface 452, and a conductive region 482 on the back surface 412 of the package carrier 41. The conductive region 482 is provided for external Φ heat dissipation (Fig. Show) a guide. Referring to FIG. 13(f), a light-emitting diode wafer 5 is fixed in the reflective cup 471, and two conductive blocks 51 are disposed on the two electrodes of the light-emitting diode wafer 5 (not labeled). A conductive block 51 is disposed on each electrode of the polar body wafer 5 so that the conductive blocks 51 protrude outside the reflective cup 471. In the present embodiment, each of the conductive blocks 51 is a gold ball having a height of about 50 to ΙΟΟμπι. In this embodiment, the light-emitting diode wafer 5 is first fixed and then the conductive block 51 is disposed. However, after the conductive block 51 is first disposed, the light-emitting diode wafer 5 is fixedly disposed in the reflective cup 471, but The overall height of the light-emitting diode wafer 5 of the two conductive blocks 51 needs to be higher than the depth of the reflective cup 471. As shown in Fig. 13 (g), the reflective cup 471 is filled with a light-transmitting adhesive 49 to seal the light-emitting diode wafer 5. The light-transmitting adhesive 49 may contain fluorescent powder or no fluorescent powder as needed. As shown in FIG. 13(h), the surface of the light-transmitting adhesive 49 is polished after the surface of the light-transmitting adhesive 49 is cured. That is, the exposed surface of the conductive blocks 51 is positioned higher than the 19 201032349 position of the opening of the reflective cup 471. Referring to FIG. 14, a second conductive layer 483" respectively connecting the conductive blocks 51 and extending to the upper inclined surface 451 is formed by a metallization process, so that the upper conductive layers 483" are electrically connected to the respective electrodes, and the upper conductive layers are respectively connected. 483" is respectively connected to the corresponding lower conductive layer 481. The subsequent steps are the same as in the third embodiment. A plurality of independent package structures 4 can be formed by cutting. The steps shown in the above Figs. 13(f) to 13(h) A general reflector cup can also be applied. As shown in FIG. 15, when the reflector cup 61 is disposed on the general package carrier 6, the two upper conductive layers 483" are the surface of the package carrier 6 extending beyond the opening of the reflector cup 61. The conductive layer 62 is extended and the conductive layer 62 is extended for electrical connection with an external electrode (not shown). In summary, the method for fabricating a light-emitting diode wafer 1 of the present invention is to form a conductive sidewall 1512 by using a metallization process on the inclined surface thereof by forming the inclined sidewall 13 and the substrate inclined wall 14. Compared with the deposition of the conductive layer on the vertical surface, it is easy to control, so that the process yield can be improved and the manufacturing cost can be reduced. In addition, the LEDs 1 and 丨 provided by the present invention are connected to the electrodes 1511, 1521, 1511, and 1521 by the bevel units 16, 16', and the electrical layers 1512, 1522, 1512', 1522 'Extension to the substrate inclined wall 14 pulls the distance between the conductive layers 1512, 1522, 1512, 1522' and the extended conductive layers 35, 35' which provide external electrical connections, reducing the possibility of wire breakage. Further, in the light-emitting diode wafer 1 of the present invention, the conductive layers 1512, 1522 of the connection electrodes 1511, 1521 are extended to the substrate inclined wall 14 by the bevel unit 16, and the conductive layer of the light-emitting diode wafer 1, Ι513, 1523' is extended to the bottom surface m of the substrate 11', and then the metallization process is used to fabricate the extension 20 201032349. The conductive layers 35, 35' and the light-emitting diode wafer are formed to form an electrical connection, and the second wire-passing process is required. Round package or system package, which can save the packaging time of wire bonding, and save the space occupied by wire bonding to reduce the J volume. The integration of other optoelectronic components has the advantages of miniaturization and integration with other LED technologies, such as the integration of nano crystal process. It is also relatively flexible. It can be seen from the implementation steps described in the first embodiment to the fifth embodiment that the package method of the light-emitting diode of the present invention does not require a wire bonding process, and can be applied to a crystal® circular package or a system package. Different light-emitting diode wafer 1, Γ, 5 structures can be selected for the applicable method steps. Further, as described in Embodiments 3 to 5, the package structure 4, 4'' which can be directly disposed on a circuit board of an application product can be formed without using a wire bonding process, which can save packaging process time and Reducing the package structure 4, 4 'Zhao Ji' can also facilitate the assembly process of the downstream application end. In addition, as shown in FIG. 7 (4), _), 11 (4), seven (4), 12 (4), and U (4) _13 (4), the package method, the package carrier structure, and the reflector cup structure are not limited to the light-emitting diode crystals disclosed in the present invention. ι, Bu can also be applied to general LED chips. The above is only the preferred embodiment of the present invention, and the scope of the invention is not limited thereto, that is, the simple equivalent changes and modifications made by the scope of the invention and the description of the invention are All remain within the scope of the invention patent. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram showing a conventional light-emitting diode wafer; 21 201032349 FIG. 2 is a plan view showing a light-emitting two disclosed in Japanese Patent Laid-Open Publication No. JP-A No. 813-875 FIG. 3 is a cross-sectional view of FIG. 2; FIG. 4(a) to FIG. 4(f) are flow charts showing the steps of the first embodiment of the method for fabricating the light-emitting diode wafer of the present invention; 4(f) is a plan view showing the position of the two-electrode unit of the embodiment i; and FIG. 6 is a schematic view showing the first embodiment of the light-emitting diode wafer of the present invention; FIGS. 7(a) to 7(g) are A flow chart of the implementation steps of the first embodiment of the light-emitting diode package method of the present invention; FIG. 8 is a flow chart subsequent to FIG. 4(a) to FIG. 4(f), illustrating the implementation of the method for fabricating the light-emitting diode wafer of the present invention. FIG. 9 is a schematic view showing Embodiment 2 of the light-emitting diode wafer of the present invention; FIG. 10(a) to FIG. 1(c) are continued from FIG. 7(a) to FIG. 7(d) The flow chart illustrates the implementation steps of Embodiment 2 of the LED package method of the present invention; and FIGS. 11(a) to 11(f) are diagrams illustrating the LED package of the present invention. FIG. 12(a) to FIG. 12(b) are flowcharts showing the light-emitting diode packaging method of the present invention, which are continued from the flowcharts of FIGS. 11(a) to 11(d). FIG. 13(a) to FIG. 13(h) are flowcharts showing the implementation steps of the fifth embodiment of the light-emitting diode sealing method of the present invention; FIG. 14 is a plan view of a circle 13(h) illustrating the implementation. The position of the upper conductive layer 22 201032349 of Example 5; and FIG. 15 is a schematic view showing another package aspect of the light-emitting diode wafer of Embodiment 5.
23 201032349 【主要元件符號說明】 1 ........ ••發光二極體晶片 1512, · …導電層 Γ ....... …發光二極體晶片 1513, · …導電層 10....... …母片 152 ··· …第二電極單元 10, ·… …母片 152’ … …第二電極單元 11…… …基板 1521 ·· …電極 11，·… …基板 1522 ·· …導電層 111 ···. …底面 1522’ · …導電層 111，… • · ·底面 1523, · …導電層 112 ···· • · ·表面 153 ··.· …絕緣層 12…… …磊晶層單元 16…… …·斜面單元 121 ···· …第一型半導體層 21…… …凹槽 122 ···· …發光層 22…… …·第二凹槽 123 ···. …第二型半導體層 23…… …基板凹槽 13…… …傾斜側壁 3 ....... …·封裝載板 131 ···· …第 斜面 35…… •…封裝載板 132 ···· …第二斜面 31…… •…保護層 133 ···· …平台 311… …·穿孔 14…… …基板傾斜壁 32…… …·凹槽 14, ···. …基板傾斜壁 321… •…開口 151 ··· …第一電極單元 33···.· •…金屬層 151，.·· …第一電極單元 34••… •…金屬層（反 1511 .· • · ·電極 ) 1512 ·· …導電層 34，···· •…反射杯 24 20103234923 201032349 [Explanation of main component symbols] 1 ........ ••Light-emitting diode wafer 1512, ... conductive layer Γ.......light-emitting diode wafer 1513, ... conductive layer 10....... ...the mother piece 152 ···...the second electrode unit 10, the mother piece 152', the second electrode unit 11, the substrate 1521, the electrode 11, the ... Substrate 1522 · · Conductive layer 111 · · · · ... bottom surface 1522 ′ · ... conductive layer 111, ... · · · bottom surface 1523, · ... conductive layer 112 · · · · · · · Surface 153 ···· 12... ... epitaxial layer unit 16 ... ... · bevel unit 121 · · · · ... first type semiconductor layer 21 ... ... groove 122 · · · · ... light-emitting layer 22 ... ... ... second groove 123 The second type semiconductor layer 23 ... the substrate recess 13 ... ... the inclined side wall 3 ... ... ... package carrier 131 ... ... ... ... ... ... ... ... ... ... ... ... ... ... package Carrier plate 132 ····...second slope 31...•...protective layer 133 ·····platform 311...·perforation 14...substrate inclined wall 32... 14, ...........substrate inclined wall 321... •...opening 151 ···...first electrode unit 33······...metal layer 151,...·...first electrode unit 34••... •... Metal layer (reverse 1511 .· • · · electrode) 1512 ··...conductive layer 34,····•...reflecting cup 24 201032349
35…·· •…延伸導電層 471 ·· …反射杯 35,… •…延伸導電層 48…… …導電層 36••… •…絕緣層 481 ···· …下導電層 37··... •…透光膠材 482 ···· …傳導區 37,… •…透光膠材 483 ··.. …上導電層 38…… •固日日勝 483,… …上導電層 4…… •…封裝結構 483，，..· …上導電層 4, ···.. •…封裝結構 49…… …透光膠材 41 ••… •…封裝載板 5 ....... …發光二極體晶片 411… ----正面 51…… …導電塊 412… …·背面 6 ....... …封裝載板 42…… •…保護層 61…… …反射杯 421… …·凹槽位置 62…… …延伸導電層 422… •…穿槽位置 91…… …發光二極體晶片 43…… •…凹槽 92…… …載板 44…… •…穿槽 93…… …外部電極 45…… •…側壁 94…… aa片 451… •…上傾斜面 941 …· …開孔 452… •…下傾斜面 95…… …導電層 46…… •…絕緣層 96…… …電極 47…… •…金屬層 97…… …電極 2535...··•...extending conductive layer 471 ···reflecting cup 35,...·...extending conductive layer 48...conducting layer 36••...•...insulating layer 481 ····...lower conductive layer 37··. .. •...translucent adhesive 482 ···· ...conducting zone 37,... •...translucent adhesive 483 ··.. ...upper conductive layer 38... • Gu Ri Risheng 483, ... upper conductive layer 4 ......•...Package structure 483,,.....Upper conductive layer 4, ···..•...Package structure 49............Translucent adhesive 41 ••... •...Package carrier 5 ..... .. ...the light-emitting diode wafer 411...-front surface 51...the conductive block 412...the back side 6.......the package carrier board 42...the protective layer 61...the reflection Cup 421 ... ... groove position 62 ... ... extended conductive layer 422 ... ... ... through slot position 91 ... ... light-emitting diode wafer 43 ... ... ... groove 92 ... ... carrier plate 44 ... ... ... wear The groove 93...the outer electrode 45...the side wall 94...aa piece 451...•...the upper inclined surface 941 ...·...the opening 452...the...the lower inclined surface 95...the conductive layer 46... Edge layer 96... ...electrode 47... •...metal layer 97... ...electrode 25