TWI398967B - Light-emitting diode chip, and manufacturing method therefor - Google Patents

Abstract

A light-emitting diode chip includes a substrate, an epitaxial layer unit, two inclined plane units, and two electrode units. The substrate has a surface and a bottom face. The epitaxial layer unit is located on the surface of the substrate. Each of the inclined plane units is inclined downwardly and outwardly from the epitaxial layer unit toward the bottom face of the substrate, and includes an inclined sidewall located at the epitaxial layer unit, and a substrate inclined wall located at the substrate. Each of the electrode units includes an electrode provided on the epitaxial layer unit, and a conductive layer extending from the electrode along the corresponding inclined plane unit to the substrate inclined wall.

Description

Light-emitting diode chip and its preparation method

The invention relates to a light-emitting diode wafer, a method for manufacturing the same and a packaging method thereof, in particular to a light-emitting diode chip with a small package size and a fast processing speed, a method for manufacturing the same, and a packaging method thereof.

As shown in FIG. 1, the conventional light-emitting diode chip 91 is usually electrically connected to the external electrode 93 on the carrier 92 by wire bonding. Since the wire bonding process requires a large space for the carrier plate 92, and the wire bonding process is one by one connection of the machine, the process efficiency is extremely low, which is disadvantageous to a system in package or a wafer level package.

In order to improve the shortcomings of the wire bonding process, the current common method is to use a flip-chip method for electrical connection to save the wire bonding process. However, the flip chip process requires a large number of gold balls on a single wafer, which is time consuming and affects packaging efficiency. In addition to the flip chip method, there are other packaging methods that do not need to be wired. For example, the flip chip adheres the electrode on the surface of the wafer directly to the electrode on the carrier without using a gold ball. In this way, the electrode on the surface of the wafer needs to be made. High, and has excellent flatness, high production accuracy requirements, relatively difficult to make the process. Another way is to adjust the structure of the wafer so that the wafer electrode extends from the surface of the wafer to the bottom surface of the wafer. For example, the wafer fabrication method disclosed in Japanese Patent Publication No. JP 2008-130875, as shown in FIGS. 2 and 3, is to open a hole in the wafer 94. 941, a conductive layer 95 is plated such that the conductive layer 95 connects the electrode 96 on the surface of the wafer 94 to the electrode 97 on the bottom surface of the wafer 94 through the opening 941, so that the electrode 94 of the wafer 94 can be located at the bottom surface thereof. However, in the case of JP 2008-130875, the wall surface defining the opening 941 is a vertical wall surface, and when the conductive layer is plated, there is a disadvantage of poor step coverage, which tends to cause unevenness of the conductive layer and affect conductivity.

In order to solve the foregoing problems, the present invention utilizes inclined sidewalls formed on both sides of a light-emitting diode wafer, and the inclined surface generated by the inclined sidewalls can make the conductive layer be uniformly deposited on the inclined surface to avoid the disadvantage of poor step coverage. The electrode on the surface of the light-emitting diode wafer is extended to the two sides of the substrate of the wafer or the bottom surface of the substrate by the conductive layer on the inclined surface, which is beneficial to the subsequent packaging process, and moreover, the wire is not required to be used, and the wire can be reduced. The volume of the package structure.

Further, the present invention also provides a method for manufacturing a reflective cup using a semiconductor process technology and a method for packaging a light emitting diode, which can be applied to a system package or a wafer level package. The method for manufacturing the reflective cup of the present invention only needs to complete the groove structure with the reflective layer by using a single mask process, and requires two mask processes compared with the conventional process, which can reduce the process time and the manufacturing cost. The packaging method provided by the invention can form an electrical connection with the wires of the package carrier board without a wire bonding process, which not only saves process time, improves production efficiency, but also reduces the volume of the package structure.

Furthermore, the present invention also provides a packaging method capable of extending the electrodes of the LED substrate to the bottom surface of the package carrier, and does not need to be opened in the reflective cup to avoid the effect of destroying the sealing wafer, and can solve the general problem. Opening the hole at the bottom of the reflector cup to extend the electrode to the bottom of the package carrier causes the wafer to be easily wetted and the structure of the package structure is fragile, and the package structure can be directly disposed on the circuit board of an application product without The use of the wire-bonding process can reduce the defect rate caused by wire breakage, improve the reliability of the package, and make the assembly process of the downstream application end easier.

In the light-emitting diode chip provided by the present invention, the conductive layer of the connection electrode is extended to the inclined wall or the bottom surface of the substrate by the bevel unit, and the light-emitting diode chip can be fixed in the package carrier to directly form an electrical connection, or can be utilized. The metallization process produces an extended conductive layer to form an electrical connection. Since the wire bonding process is not required, it is helpful for wafer level packaging or system packaging, thereby saving the packaging time of one wire and one wire, and saving the space occupied by the wire to reduce the volume. The integration of other optoelectronic components has the advantage of miniaturization, and integration with other LED technologies, such as the integration of nano crystal processes, is also more flexible. In addition, the method for fabricating a light-emitting diode wafer provided by the present invention can form a conductive layer by using a metallization process on the inclined surface thereof by forming the inclined sidewall and the inclined wall of the substrate, which is easier to control than depositing the conductive layer on the vertical surface. Therefore, it can improve the process yield and reduce the manufacturing cost.

The method for manufacturing a reflective cup for a light-emitting diode package provided by the present invention, by partially shielding a protective layer protruding in the groove, so that the gold layer covered in the groove does not exceed the groove opening, and Eliminate a mask process to reduce process time and cost.

The method for packaging a light-emitting diode provided by the invention can complete the packaging of a plurality of light-emitting diode chips on the same package carrier board, and can also be used for wafer level packaging or system packaging, according to the method of packaging the plurality of light-emitting diode chips. Different light-emitting diode structure can select suitable method steps to extend the conductive layer connecting the wafer electrodes out of the reflective cup, and further extend from the outside of the reflective cup to the bottom surface of the package carrier to maintain the integrity of the wafer seal. The packaging method of the present invention not only saves the packaging process time and reduces the volume of the package structure, but also facilitates the assembly process of the downstream application end.

The foregoing and other technical aspects, features and advantages of the present invention will be apparent from the Detailed Description of the <RTIgt;

Before the present invention is described in detail, it is noted that in the following description, similar elements are denoted by the same reference numerals.

Example 1 Fabrication of light-emitting diode chips

Referring to Fig. 4 (a) to Fig. 4 (f), a flow chart showing the steps of the first embodiment of the method for fabricating the light-emitting diode wafer of the present invention will be described. The implementation steps include:

As shown in FIG. 4(a), a master 10 having an epitaxial structure is completed. The master 10 includes a substrate 11 and an epitaxial layer unit 12 formed on the substrate 11. The epitaxial layer unit 12 includes a first type semiconductor layer 121 formed on the substrate 11, a light emitting layer 122 formed on the first type semiconductor layer 121, and a second type semiconductor layer 123 formed on the light emitting layer 122. In this embodiment, the substrate 11 is made of sapphire and has a thickness of about 350 μm; the first type semiconductor layer 121 is n-type gallium nitride (n-GaN), and the second type semiconductor layer 123 is p-type gallium nitride ( p-GaN).

A patterning process using semiconductor process technology defines a plurality of locations on the master wafer 10 that are intended to form a wafer and a location that is intended to form a recess between the wafers (not shown). The following steps illustrate how the sidewalls and electrode cells of each wafer can be formed using an etch and metallization process. For ease of illustration, only the implementation between two adjacent wafers is shown. As shown in FIG. 4(b), a portion of the first type semiconductor layer 121 is etched by the second type semiconductor layer 123 by an etching process at a position where the groove 21 is formed, so that the first type semiconductor layer 121 is exposed to form an opening. The groove 21 which is expanded outward, that is, a first inclined surface 131 which extends from the side of the second-type semiconductor layer 123 to the side of the portion of the first-type semiconductor layer 121 is formed on one side of each wafer 1. As shown in FIG. 4(c), the bottom portion of the recess 21 between the two wafers 1, that is, the exposed surface of the first type semiconductor layer 121, defines the position of a second recess 22, and then etches the first type. A surface of the semiconductor layer 121 to the surface of the substrate 11 is formed with a second recess 22 which is expanded outwardly, and a part of the surface of the substrate 11 is exposed, thereby forming a side of the first type semiconductor layer 121 on one side of each wafer 1 and adjacent thereto. a second inclined surface 132 of the substrate 11 and a platform 133 connected to the first inclined surface 131 and the second inclined surface 132, and the first inclined surface 131, the second inclined surface 132 and the platform 133 form one of the epitaxial layer units 12 and The inclined side wall 13 is inclined outward. The other side of the epitaxial layer unit 12 of each wafer 1 is also formed by another set of recesses 21 and second recesses 22 into a sloping side wall 13 which is inclined downward and outward. The etching process may be performed by dry etching or wet etching, and an appropriate etching method may be selected according to the material of the epitaxial layer unit 12. This is a well-known technique in the field of the invention, and details are not described herein. It should be noted that the foregoing steps of forming the recess 21 and the second recess 22 are only one of the embodiments, and the recess 21 and the second recess can also be defined by using different photoresist thickness or halftone halftone processes. The position of the two recesses 22, and the recess 21 and the second recess 22 may be formed by one etching step or two etching steps, not limited to this embodiment.

As shown in FIG. 4(d), at the bottom of the second recess 22, that is, the surface of the exposed substrate 11, a substrate recess 23 which is expanded outward is formed by etching, whereby the wafers 1 on both sides of the substrate recess 23 are respectively formed. A substrate inclined wall 14 that is inclined in the same direction as the adjacent inclined side walls 13. Similarly, the other side of the substrate 11 of each wafer 1 is simultaneously formed with another substrate recess 23, and another substrate inclined wall 14 which is inclined in the same direction as the adjacent inclined side walls 13 is formed. Here, the etching process can also utilize dry etching or wet etching. In the present embodiment, the substrate 11 is etched by using a wet etching method by mixing phosphoric acid with water and heating as an etching solution, so that the tilt angle of the substrate inclined wall 14 is about Between 40 and 60 degrees.

As shown in FIG. 4(e), a two-electrode unit is formed on each of the wafers 1 by a metallization process, and is a first electrode unit 151 electrically connected to the first-type semiconductor layer 121, and a first type and a second type. The semiconductor layer 123 forms a second electrode unit 152 that is electrically connected. The first electrode unit 151 includes an electrode 1511 disposed on a surface of the platform 133 of one of the inclined sidewalls 13, and a conductive layer 1512 extending from the electrode 1511 along the adjacent second slope 132 to the substrate inclined wall 14. The second electrode unit 152 includes an electrode 1521 disposed on the surface of the second type semiconductor layer 123, and a conductive layer 1522 extending from the electrode 1521 along the other inclined sidewall 13 to the substrate inclined wall 14. Moreover, an insulating layer 153 is formed between the conductive layer 1522 of the second electrode unit 152 and the corresponding inclined sidewall 13 to prevent the first electrode unit 151 from being short-circuited with the second electrode unit 152. The distribution of the first electrode unit 151 and the second electrode unit 152 on the wafer 1 can be coordinated with reference to the top view of FIG. 5. Before the electrode 1521 is formed, a transparent electrode such as an indium tin oxide (ITO) film (not shown) may be coated on the surface of the second type semiconductor layer 123 to increase the uniformity of conduction.

As shown in FIG. 4(f), the bottom surface 111 of the substrate 11 on the opposite side of the epitaxial layer unit 12 is ground, and the substrate recesses 23 are worn through, so that the conductive layers 1512 and 1522 on the inclined walls 14 of the substrate are exposed to the bottom surface 111. . In the present embodiment, the thickness of the substrate 11 after polishing is about 50 to 100 μm. Thereafter, the mother wafer 10 is cut to form a plurality of individual wafers 1.

Light-emitting diode chip

As shown in FIG. 6 , the wafer 1 obtained in the foregoing step is the first embodiment of the present invention, including a substrate 11 , an epitaxial layer unit 12 , two inclined surface units 16 , and two electrode units 151 and 152 . . The substrate 11 has a surface 112 and a bottom surface 111. The epitaxial layer unit 12 is located on the surface 112 of the substrate 11 and includes a first type semiconductor layer 121, a light emitting layer 122 and a second type semiconductor layer 123. The first type semiconductor layer 121 is located on the surface 112 of the substrate 11, and the light emitting layer 122 is located between the first type semiconductor layer 121 and the second type semiconductor layer 123. The two beveling units 16 are respectively located on the two opposite sides, and each of the inclined surface units 16 is inclined downward and outward by the epitaxial layer unit 12 toward the bottom surface 111 of the substrate 11, each of which includes an inclined side wall 13 of the epitaxial layer unit 12, and Located on one of the substrate 11 inclined walls 14. Each of the inclined sidewalls 13 further includes a first inclined surface 131 extending from the side of the second-type semiconductor layer 123 to a portion of the first-type semiconductor layer 121 and a second inclined surface 132 of an adjacent substrate 11, and the first inclined surface 131 and The second inclined faces 132 are connected by a platform 133. The two electrode units 151 and 152 are respectively a first electrode unit 151 electrically connected to the first type semiconductor layer 121 and a second electrode unit 152 electrically connected to the second type semiconductor layer 123. The first electrode unit 151 includes an electrode 1511 disposed on a surface of the platform 133 of one of the inclined sidewalls 13 and a conductive layer 1512 extending from the electrode 1511 along the adjacent second slope 132 to the substrate inclined wall 14. The second electrode unit 152 includes an electrode 1521 disposed on the surface of the second type semiconductor layer 123, and a conductive layer 1522 extending from the electrode 1521 along the other inclined sidewall 13 to the substrate inclined wall 14. Moreover, an insulating layer 153 is further disposed between the conductive layer 1522 of the second electrode unit 152 and the corresponding inclined sidewall 13. Further, the substrate 11 may be a substrate having conductivity. When the substrate has electrical conductivity, an insulating layer is provided on the inclined wall of the substrate. In this embodiment, the tilt angle of the substrate inclined wall 14 is about 40-60 degrees, which is advantageous for the connection of the plated extended conductive layer and the conductive layer 1512, 1522 on the repackage carrier during packaging, and the related light emitting diode chip The package method of 1 will be explained below.

LED package

7(a) to 7(g) are views showing an implementation flow of the first embodiment of the package method of the light-emitting diode of the present invention, and Figs. 7(a) to 7(d) also illustrate the method of manufacturing the reflector cup of the present invention. As shown in FIG. 7(a), a protective layer 31 is formed on a loading plate 3, and the protective layer 31 is patterned to form a through hole 311 penetrating the protective layer 31. In this embodiment, the package carrier 3 is made of 矽, and the protective layer 31 is made of SiN _x . The package carrier 3 may also be other non-conductive materials such as ceramic materials such as aluminum nitride or aluminum oxide. The material of the protective layer 31 may be SiO _x , SiN _x /SiO _x , or metal (for example, Ni, Au), etc. The formation method of the protective layer 31 may be selected according to the material thereof, for example, a non-metal material may be formed by vapor deposition (CVD). Or high-humidity high-temperature furnace process, metal materials can be electroplated, sputtered or evaporated.

As shown in FIG. 7(b), the package carrier 3 is etched through the via 311 by using an etchant to form a recess 32 having an opening 321 larger than the through hole 311, so that a portion of the protective layer 31 of the adjacent via 311 protrudes into the recess 32. . In the present embodiment, the etching solution is a KOH solution, and the KOH solution having a concentration of 30 vol% is etched at a temperature of 80 ° C or a 45 vol% KOH solution at 85 ° C, and the etching rate is about 1 μm/min. The selection of the etching solution can be adjusted according to actual needs, and is not limited to the embodiment.

As shown in FIG. 7(c), a metal layer 33, 34 is formed on the protective layer 31 and the recess 32, and the recess 32 is adjacent by the shielding of the protective layer 31 partially protruding in the recess 32. The protective layer 31 (near the opening 321) is not covered with the metal layer 34. The metal layers 33, 34 can be deposited by sputtering or evaporation, and the material can be Ti/Al, Ti/Ni/Ag or other common reflective layer materials that can be used to reflect light.

As shown in FIG. 7(d), the protective layer 31 and the metal layer 33 on the protective layer 31 are removed, leaving the metal layer 34 in the recess 32, that is, forming a reflective cup 34 in the recess 32. The reflective cup 34 formed by the foregoing steps only needs to use a mask process to define the position of the through hole 311 when the protective layer 31 is patterned, and then shields the protective layer 31 so that no metal layer is deposited near the opening 321 of the groove 32. 34, so the reflector cup 34 does not extend beyond the opening 321 of the recess 32, and the reticle process that defines the open area of the reflector cup 34 to avoid exceeding the opening 321 of the recess 32 can be eliminated.

As shown in FIG. 7(e), a light-emitting diode wafer 1 obtained as described above is fixed in the reflective cup 34. Further, the LED chip 1 is fixed in the reflective cup 34 by a die bonding adhesive 38. In the embodiment, the die bonding adhesive 38 is made of an insulating material, so that the conductive layer 1512 of the first electrode unit 151 is The conductive layer 1522 of the second electrode unit 152 is electrically separated from the reflective cup 34.

Further, as shown in FIG. 7(f), two extended conductive layers 35 are formed by a metallization process, and each of the extended conductive layers 35 is respectively connected to the conductive layer 1512 and the second electrode unit 152 of the first electrode unit 151 of the light-emitting diode wafer 1. The conductive layer 1522 is connected by the inclined wall 14 of the substrate, and may of course be connected by the inclined sidewalls 13 so that the first electrode unit 151 and the second electrode unit 152 extend out of the reflective cup 34 by the extended conductive layers 35. On the carrier 3, in this embodiment, since the reflective cup 34 and the package carrier 3 are both electrically conductive, it is necessary to form an extended conductive on the reflective cup 34 and the package carrier 3 before forming the extended conductive layer 35. The location of the layer 35 forms an insulating layer 36 to prevent the extended conductive layer 35 from contacting the reflective cup 34 and the package carrier 3. As shown in FIG. 7(g), the reflective cup 34 is filled with a light-transmitting adhesive 37 to seal the light-emitting diode wafer 1. The light-transmitting adhesive 37 may contain fluorescent powder or no fluorescent powder, depending on the needs of use.

Although the light-emitting diode wafer 1 is disposed in the reflective cup 34 in the present embodiment, the foregoing steps of forming the extended conductive layer 35 can also be applied to a general carrier or a general reflective cup.

Example 2 Fabrication of light-emitting diode chips

The implementation steps of Embodiment 2 of the method for fabricating a light-emitting diode wafer of the present invention are substantially the same as those of Embodiment 1, and can be referred to FIG. 4(a) to FIG. 4(f). The difference is that, as shown in FIG. After the bottom surface 111' of the substrate 11' is polished to expose the conductive layers 1512', 1522' of the substrate inclined walls 14', the second embodiment forms a conductive relationship with the substrate inclined walls 14' on the bottom surface 111' by a metallization process. The conductive layers 1513', 1523' connected to the layers 1512', 1522' extend the conductive layers 1512', 1513', 1522', 1523' of the first and second electrode units 151', 152' to the bottom surface 111 of the substrate 11' '. Additionally, prior to the metallization process step, the step of polishing the bottom surface 111' to provide a relatively flat and smooth surface may be further included. Thereafter, each wafer 1' on the mother substrate 10' is cut to form a plurality of individual wafers 1'.

Light-emitting diode chip

As shown in FIG. 9, the wafer 1' obtained in the foregoing step is the second embodiment of the light-emitting diode wafer of the present invention, which is substantially the same as the first embodiment, and is different in the first electrode unit 151 of the second embodiment. 'Contains a conductive layer 1513' extending over the bottom surface 111' of the substrate 11', and the second electrode unit 152' includes a conductive layer 1523' extending from the bottom surface 111' of the substrate 11'.

LED package

Figs. 10(a) through 10(c) are views showing an implementation flow of the second embodiment of the package method of the light-emitting diode of the present invention for encapsulating the above-described light-emitting diode wafer 1'.

As shown in FIG. 10(a), the position (not shown) of the two conductive layers 1513', 1523' of the bottom surface 111' of the light-emitting diode wafer 1' is predetermined to be defined in the reflective cup 34', and metallization is utilized. The process forms two extended conductive layers 35' such that each of the extended conductive layers 35' extends from a predetermined position of each of the conductive layers 1513', 1523' to the package carrier 3' outside the reflective cup 34'. In the present embodiment, the steps of forming the reflecting cup 34' are the same as those of the first embodiment, and reference is made to Figs. 7(a) to 7(d). Since the reflective cup 34' and the package carrier 3' are both electrically conductive, it is necessary to form the extended conductive layer 35' on the reflective cup 34' and the package carrier 3' before forming the extended conductive layer 35'. An insulating layer 36' prevents the extended conductive layer 35' from coming into contact with the reflective cup 34' and the package carrier 3'.

As shown in FIG. 10(b), a light-emitting diode wafer 1' is fixed in the reflective cup 34', and the two conductive layers 1513', 1523' are electrically connected to the corresponding extended conductive layers 35', respectively. .

As shown in Fig. 10 (c), the reflective cup 34' is filled with a light-transmitting adhesive 37' to seal the light-emitting diode wafer 1'. The light-transmitting adhesive 37' may contain phosphor powder or no phosphor powder, depending on the needs of use.

Although the light-emitting diode wafer 1' is disposed in the reflective cup 34' in this embodiment, the foregoing step of forming the extended conductive layer 35' and then contacting the light-emitting diode wafer 1' can also be applied to a general carrier. Or a general reflector cup.

Example 3

11(a) to 11(f) illustrate a third embodiment of the light emitting diode packaging method of the present invention.

As shown in FIG. 11(a), a protective layer 42 is first coated on the front surface 411 and the back surface 412 of a loading plate 41, and the protective layer 42 is patterned to form a plurality of through holes 421 and 422 to define a concave shape for which the reflecting cup is reserved. The groove position 421 and the grooved position 422 of the groove 44 (see FIG. 11(b)) are disposed on both sides of the groove position 421, respectively. The front surface 411 corresponds to the grooved position 422 of the back surface 412. As shown in FIG. 11(b), the package carrier 41 is etched by an etching solution, and a recessed portion 411 of the protective layer 42 is formed on the front surface 411 of the package carrier 41 to form a concave portion for which a reflecting cup 471 (see FIG. 11(c)) is disposed. The groove 43 is such that the opening 431 of the groove 43 is larger than the through hole 421, and is etched by the front surface 411 and the back surface 412 of the package carrier 41 through the respective through holes 422 to form two through grooves 44 respectively adjacent to the groove 43. The sidewalls 45 of the two adjacent package structures 4 are formed by each of the slots 44, and each of the sidewalls 45 has an upper inclined surface 451 which is outwardly tilted from the front surface 411 of the package carrier 41 and a rear surface 412 of the package carrier 41. A downwardly inclined surface 452 that is outwardly inclined toward the center. In the present embodiment, the material of the package carrier 41 is 矽, and the material and etching method of the protective layer 42 can be referred to the first embodiment, and will not be repeated here.

As shown in FIG. 11(c), a metal layer 47 is further deposited on the front surface 411 of the package carrier 41, so that the recess 43 and the upper inclined surface 451 of each of the slots 44 are covered with a metal layer 47, wherein the recess 43 and the protective layer 42 are provided. The adjacent portion is not covered with the metal layer 47, and a reflective cup 471 is formed in the recess 43.

As shown in FIG. 11(d), the protective layer 42 of the front surface 411 and the rear surface 412 of the package carrier 41 is removed. Since the package carrier 41 of the present embodiment has conductivity, after the protective layer 42 is removed, the package carrier 41 is removed. An insulating layer 46 is deposited on the front side 411 and the back side 412.

As shown in FIG. 11(e), a conductive layer 48 having a predetermined pattern is formed on the back surface 412 of the package carrier 41 by a metallization process, including two lower conductive layers respectively extending from the back surface 412 of the package carrier 41 to the respective lower inclined surfaces 452. Layer 481, and a conductive region 482 on the back side 412 of the package carrier 41, the conductive region 482 is adapted to be coupled to an external heat sink (not shown). Alternatively, conductive layer 48 can also be fabricated by a lift-off process.

As shown in FIG. 11(f), the light-emitting diode wafer 1 as described in the first embodiment is fixed in the reflective cup 471, and the steps described in FIGS. 7(e) to 7(g) are used. Embodiment 3 further extends the extended conductive layer 35 of Embodiment 1 to each of the upper inclined faces 451 to form two upper conductive layers 483, and each of the upper conductive layers 483 is respectively connected to the corresponding lower conductive layer 481 and respectively respectively The electrode unit 151 and the second electrode unit 152 are electrically connected such that the first and second electrode units 151, 152 can extend to the back surface 412 of the package carrier 41. The light-emitting adhesive material 49 is filled in the reflective cup 471 to seal the light-emitting diode wafer 1 to form a package structure 4. The light-transmitting adhesive 49 may contain fluorescent powder or no fluorescent powder as needed. The foregoing implementation steps can complete a plurality of package structures 4 on the same package carrier 41. After cutting, a plurality of independent package structures 4 can be fabricated, and the individual package structures 4 can be directly disposed on a circuit board of an application product. Not shown), the wire bonding process is not required, and the assembly process of the downstream application end is facilitated.

The packaging method of Embodiment 3 utilizes the through-groove 44 outside the reflective cup 471 to connect the upper conductive layer 483 with the lower conductive layer 481, thereby avoiding damage to the sealing property of the LED wafer 1, and the upper conductive layer 483 and the lower layer. The conductive layer 481 is formed on the upper inclined surface 451 and the lower inclined surface 452, respectively, and the metal layer can be easily deposited by the inclined surface, thereby improving the process yield.

Example 4

Embodiment 4 is another embodiment in which the light-emitting diode wafer 1' (see Fig. 9) is packaged, and the implementation steps are the same as those of the embodiment 3, and reference is made to Figs. 11(a) to 11(d). Referring next to FIG. 12(a), a conductive layer 48 having a predetermined pattern is formed on the back surface 412 of the package carrier 41 by a metallization process, including two lower conductive layers extending from the back surface 412 of the package carrier 41 to the respective lower inclined surfaces 452, respectively. 481, and a conductive region 482 on the back side 412 of the package carrier 41, the conductive region 482 is adapted to be coupled to an external heat sink (not shown). And defining, in the reflective cup 471, the positions of the conductive layers 1513 ′, 1523 ′ of the first and second electrode units 151 ′, 152 ′ of the bottom surface of the light-emitting diode wafer 1 ′ are disposed, and then forming a conductive layer by using a metallization process. The layer 483' is such that each of the upper conductive layers 483' is extended from the predetermined positions (not labeled) of the first and second electrode units 151', 152' to the respective upper inclined surfaces 451, and is connected to the respective lower conductive layers 481. . Similarly, conductive layer 48 and upper conductive layer 483' can also be fabricated using a lift-off process.

Referring to FIG. 12(b), the LED chip 1' is fixed in the reflective cup 471, and the two conductive layers 1513', 1523' are electrically connected to the corresponding upper conductive layers 483', that is, Each of the upper conductive layers 483' is electrically connected to the corresponding first and second electrode units 151', 152', respectively. The light-transmitting paste 49 is further filled in the reflective cup 471 to seal the light-emitting diode wafer 1'. The light-transmitting adhesive 49 may contain fluorescent powder or no fluorescent powder, depending on the needs of use.

Example 5

13(a) to 13(h) illustrate the implementation steps of the embodiment 5 of the light-emitting diode packaging method of the present invention. The implementation steps of Embodiment 5 can be used to package a light-emitting diode wafer 5 having a general electrode on the front side.

13(a) and 13(b), the implementation steps are substantially the same as those of FIG. 11(a) and FIG. 11(b) of the third embodiment, and a groove 43 and a second groove are formed in the package carrier 41. 44. However, there is an insulating layer 46 between the protective layer 42 and the package substrate 41.

Referring to Fig. 13 (c), the exposed surface of the recess 43 and the through groove 44 is oxidized to form an oxide layer as the insulating layer 46'.

Referring to FIG. 13(d), a metal layer 47 is deposited from the front surface 411 of the package carrier 41 such that the recess 43 and the upper inclined surface 451 of each of the through slots 44 are covered with a metal layer 47, wherein the recess 43 is adjacent to the protective layer 42. The metal layer 47 is not covered, and a reflective cup 471 is formed in the recess 43.

Referring to FIG. 13(e), the protective layer 42 of the front surface 411 and the rear surface 412 of the package carrier 41 is removed, and a conductive layer 48 having a predetermined pattern is formed on the back surface 412 of the package carrier 41 by a metallization process, including two packages respectively. The back surface 412 of the carrier board 41 extends to the lower conductive layer 481 of each of the lower inclined surfaces 452, and a conductive region 482 on the back surface 412 of the package carrier 41. The conductive region 482 is for guiding with an external heat sink (not shown).

Referring to FIG. 13(f), a light-emitting diode wafer 5 is fixed in the reflective cup 471, and two conductive blocks 51 are disposed on the two electrodes of the light-emitting diode wafer 5 (not labeled). A conductive block 51 is disposed on each electrode of the polar body wafer 5 so that the conductive blocks 51 protrude outside the reflective cup 471. In this embodiment, each of the conductive blocks 51 is a gold ball having a height of about 50 to 100 μm. In this embodiment, the light-emitting diode wafer 5 is first fixed and then the conductive block 51 is disposed. However, after the conductive block 51 is first disposed, the light-emitting diode wafer 5 is fixed in the reflective cup 471, but the two are combined. The overall height of the light-emitting diode chip 5 of the conductive block 51 needs to be higher than the depth of the reflective cup 471.

As shown in FIG. 13(g), the reflective cup 471 is filled with a light-transmitting adhesive 49 to seal the light-emitting diode wafer 5. The light-transmitting adhesive 49 may contain fluorescent powder or no fluorescent powder as needed.

As shown in FIG. 13(h), after the light-transmitting adhesive 49 is cured, the surface thereof is ground, and the conductive blocks 51 are partially exposed on the surface of the light-transmitting adhesive 49. That is, the position of the exposed surface of the conductive blocks 51 is higher than the position of the opening of the reflective cup 471. Referring to FIG. 14, a second conductive layer 483" respectively connecting the conductive blocks 51 and extending to the upper inclined surface 451 is formed by a metallization process, so that the upper conductive layers 483" are electrically connected to the respective electrodes, and the upper conductive layers are respectively connected. 483" is respectively connected to the corresponding lower conductive layer 481. The subsequent steps are the same as in Embodiment 3, and it is possible to form a plurality of independent package structures 4' via cutting.

The steps shown in Figures 13(f) to 13(h) above can also be applied to a general reflector cup. As shown in FIG. 15, when the reflective cup 61 is disposed on the general package carrier 6, the two upper conductive layers 483" are extended conductive layers 62 extending from the surface of the package carrier 6 outside the opening of the reflective cup 61, and the conductive layer is extended. 62 is electrically connectable to an external electrode (not shown).

In summary, the method for fabricating the LED chips 1 and 1 ′ according to the present invention is to form the inclined sidewalls 13 and the substrate inclined walls 14 to deposit the conductive layers 1512 and 1512 on the slopes thereof by a metallization process. Compared with the deposition of the conductive layer on the vertical surface, it is easy to control, so the process yield can be improved and the manufacturing cost can be reduced.

In addition, the LEDs 1, 1' provided by the present invention extend the conductive layers 1512, 1522, 1512', 1522' of the connection electrodes 1511, 1521, 1511', 1521' by the bevel units 16, 16'. To the substrate inclined wall 14, the distance between the conductive layers 1512, 1522, 1512', 1522' and the extended conductive layers 35, 35' which provide external electrical connection is reduced, thereby reducing the possibility of disconnection.

Furthermore, in the light-emitting diode wafer 1 of the present invention, the conductive layers 1512, 1522 of the connection electrodes 1511, 1521 are extended to the substrate inclined wall 14 by the bevel unit 16, and the conductive layer of the LED wafer 1' is illuminated. 1513', 1523' extends to the bottom surface 111' of the substrate 11', and then the metallization process is used to form the extended conductive layer 35, 35' to form an electrical connection with the LED wafer 1, 1 ', which does not require a wire bonding process, and is suitable for crystal Round-scale package or system package, which can save the packaging time of one-and-one wire and save the space occupied by wire-bonding to reduce the size. It has the advantages of miniaturization for integrating other photoelectric components and integration with other LED technologies, such as nano crystal process. The integration is also more flexible.

It can be seen from the implementation steps described in the first embodiment to the fifth embodiment that the method for packaging the LEDs of the present invention does not require a wire bonding process and can be applied to a wafer level package or a system package according to different light emitting diode chips. 1, 1 ', 5 structure can choose the applicable method steps. Further, as described in Embodiments 3 to 5, the package structure 4, 4' which can be directly disposed on the circuit board of an application product can be formed, and the package process time and the package can be reduced without using the wire bonding process. The volume of the structure 4, 4' can also facilitate the assembly process of the downstream application end.

In addition, as shown in FIGS. 7(a)-7(d), 10(a), 11(a)-11(e), 12(a) and 13(a)-13(e), the packaging method and package are shown. The carrier structure and the reflector cup structure are not limited to the light-emitting diode chips 1 and 1' which are only applicable to the present invention, and can also be applied to a general light-emitting diode wafer.

The above is only the preferred embodiment of the present invention, and the scope of the invention is not limited thereto, that is, the simple equivalent changes and modifications made by the scope of the invention and the description of the invention are All remain within the scope of the invention patent.

1. . . Light-emitting diode chip

1'. . . Light-emitting diode chip

10. . . Master piece

10’. . . Master piece

11. . . Substrate

11’. . . Substrate

111. . . Bottom

111’. . . Bottom

112. . . surface

12. . . Epitaxial layer unit

121. . . First type semiconductor layer

122. . . Luminous layer

123. . . Second type semiconductor layer

13. . . Sloping side wall

131. . . First slope

132. . . Second slope

133. . . platform

14. . . Sloping wall of substrate

14’. . . Sloping wall of substrate

151. . . First electrode unit

151’. . . First electrode unit

1511. . . electrode

1512. . . Conductive layer

1512’. . . Conductive layer

1513’. . . Conductive layer

152. . . Second electrode unit

152’. . . Second electrode unit

1521. . . electrode

1522. . . Conductive layer

1522’. . . Conductive layer

1523’. . . Conductive layer

153. . . Insulation

16. . . Bevel unit

twenty one. . . Groove

twenty two. . . Second groove

twenty three. . . Substrate recess

3. . . Package carrier

3’. . . Package carrier

31. . . The protective layer

311. . . perforation

32. . . Groove

321. . . Opening

33. . . Metal layer

34. . . Metal layer (reflective cup)

34’. . . Reflective cup

35. . . Extended conductive layer

35’. . . Extended conductive layer

36. . . Insulation

37. . . Light-transmissive glue

37’. . . Light-transmissive glue

38. . . Solid crystal glue

4. . . Package structure

4’. . . Package structure

41. . . Package carrier

411. . . positive

412. . . back

42. . . The protective layer

421. . . Groove position

422. . . Grooving position

43. . . Groove

44. . . Grooving

45. . . Side wall

451. . . Inclined surface

452. . . Lower slope

46. . . Insulation

47. . . Metal layer

471. . . Reflective cup

48. . . Conductive layer

481. . . Lower conductive layer

482. . . Conduction zone

483. . . Upper conductive layer

483’. . . Upper conductive layer

483"... upper conductive layer

49. . . Light-transmissive glue

5. . . Light-emitting diode chip

51. . . Conductive block

6. . . Package carrier

61. . . Reflective cup

62. . . Extended conductive layer

91. . . Light-emitting diode chip

92. . . Carrier board

93. . . External electrode

94. . . Wafer

941. . . Opening

95. . . Conductive layer

96. . . electrode

97. . . electrode

Figure 1 is a schematic view showing a conventional light-emitting diode wafer;

Figure 2 is a plan view showing a light-emitting diode wafer disclosed in Japanese Patent Laid-Open Publication No. 2008-130875;

Figure 3 is a cross-sectional view of Figure 2;

4(a) to 4(f) are flow charts showing the steps of the first embodiment of the method for fabricating the light-emitting diode wafer of the present invention;

Figure 5 is a plan view of Figure 4 (f) illustrating the position of the two-electrode unit of Embodiment 1;

Figure 6 is a schematic view showing Embodiment 1 of the light-emitting diode chip of the present invention;

7(a) to 7(g) are flow charts illustrating the steps of the embodiment 1 of the method for packaging a light-emitting diode according to the present invention;

Figure 8 is a flow chart subsequent to Figure 4 (a) to Figure 4 (f), illustrating the implementation steps of the second embodiment of the method for fabricating the light-emitting diode wafer of the present invention;

Figure 9 is a schematic view showing Embodiment 2 of the light-emitting diode chip of the present invention;

10(a) to 10(c) are flowcharts subsequent to FIGS. 7(a) to 7(d), illustrating the implementation steps of the embodiment 2 of the light emitting diode package method of the present invention;

11(a) to 11(f) are flow charts showing the implementation steps of Embodiment 3 of the LED package method of the present invention;

12(a) to 12(b) are flowcharts of FIG. 11(a) to FIG. 11(d), illustrating the implementation steps of Embodiment 4 of the LED package method of the present invention;

13(a) to 13(h) are flow charts showing the implementation steps of Embodiment 5 of the LED package method of the present invention;

Figure 14 is a plan view of Figure 13 (h) illustrating the position of the upper conductive layer of Embodiment 5;

Figure 15 is a schematic view showing another package aspect of the light-emitting diode wafer of Embodiment 5.

1. . . Light-emitting diode chip

11. . . Substrate

111. . . Bottom

112. . . surface

12. . . Epitaxial layer unit

121. . . First type semiconductor layer

122. . . Luminous layer

123. . . Second type semiconductor layer

13. . . Sloping side wall

131. . . First slope

132. . . Second slope

133. . . platform

14. . . Sloping wall of substrate

151. . . First electrode unit

1511. . . electrode

1512. . . Conductive layer

152. . . Second electrode unit

1521. . . electrode

1522. . . Conductive layer

153. . . Insulation

16. . . Bevel unit

Claims (13)

A light-emitting diode wafer comprising: a substrate having a surface and a bottom surface; an epitaxial layer unit located on a surface of the substrate; and two inclined surface units each facing the substrate by the epitaxial layer unit The bottom surface is downwardly and outwardly inclined, and includes an inclined sidewall on one of the epitaxial layer units and an inclined wall of the substrate on the substrate; and two electrode units, each of the electrode units including a layer disposed on the epitaxial layer unit An electrode, and a conductive layer extending from the corresponding bevel unit to the inclined wall of the substrate. The light-emitting diode wafer according to claim 1, wherein each of the conductive layers further extends to a bottom surface of the substrate. The illuminating diode chip according to claim 1 or 2, wherein an insulating layer is further disposed between the conductive layer of one of the two electrode units and the corresponding inclined sidewall. The illuminating diode chip according to claim 1 or 2, wherein the epitaxial layer unit comprises a first type semiconductor layer, a light emitting layer and a second type semiconductor layer, the first type semiconductor layer Located on the surface of the substrate, and the light emitting layer is located between the first type semiconductor layer and the second type semiconductor layer; the two electrode units are respectively a first electrode unit electrically connected to the first type semiconductor layer, and And a second electrode unit electrically connected to the second type semiconductor layer, and an insulating layer is further disposed between the conductive layer of the second electrode unit and the corresponding inclined sidewall. The illuminating diode chip according to claim 4, wherein each of the slanting sidewalls further includes a first slope extending from the second semiconductor layer side to a portion of the first semiconductor layer side and a second inclined surface adjacent to the substrate, and the first inclined surface and the second inclined surface are connected by a platform. The light-emitting diode wafer according to claim 1 or 2, wherein each of the inclined walls of the substrate has an inclination angle of 40 to 60 degrees. The light-emitting diode wafer according to claim 1 or 2, wherein the inclined wall of the substrate is inclined in the same direction as the adjacent inclined side wall. The illuminating diode chip according to claim 1 or 2, wherein the two slanting units are respectively located on opposite sides. A method for manufacturing a light-emitting diode wafer, the method comprising: providing a substrate; forming an epitaxial layer on a surface of the substrate; etching the epitaxial layer, forming a downward direction on both sides of the epitaxial layer and tilting outward Slanting the sidewalls and exposing a portion of the surface of the substrate; etching the surface of the exposed substrate to form a substrate recess, each of the substrate recesses having a substrate inclined wall; forming a two-electrode unit, wherein each of the electrode units includes a An electrode of the epitaxial layer unit, and a first conductive layer extending from the inclined sidewall to the adjacent inclined wall of the substrate; and grinding the bottom surface of the substrate to expose the first conductive layer to the bottom surface. The method for fabricating a light-emitting diode according to claim 9 further comprises the step of forming a second conductive layer on the bottom surface of the polished substrate for connecting the first conductive layer. A method of fabricating a light-emitting diode wafer according to claim 9 or claim 10, wherein the inclined wall of the substrate is inclined in the same direction as the adjacent inclined side wall. The method for fabricating a light-emitting diode according to claim 9 or 10, wherein the epitaxial layer unit comprises a first type semiconductor layer, a light emitting layer and a second type semiconductor layer in sequence; The epitaxial layer etching step further includes the steps of: etching the second type semiconductor layer, the light emitting layer and the first type semiconductor layer, and partially exposing the first type semiconductor layer to form each of the inclined sidewalls by the first Extending the second semiconductor layer side downward to a portion of the first bevel of the first type semiconductor layer; and etching a portion of the exposed surface of the first type semiconductor layer to the substrate to expose a portion of the surface of the substrate to form each a second inclined surface adjacent to the substrate and a platform connected to the first inclined surface and the second inclined surface. The method for fabricating a light-emitting diode according to claim 9 or 10, wherein before the step of forming the pair of electrode units, the method further comprises the step of: forming an insulating layer on the first conductive layer and corresponding the tilt Between the side walls.