TWI398967B - Light-emitting diode chip, and manufacturing method therefor - Google Patents

Light-emitting diode chip, and manufacturing method therefor Download PDF

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TWI398967B
TWI398967B TW98105482A TW98105482A TWI398967B TW I398967 B TWI398967 B TW I398967B TW 98105482 A TW98105482 A TW 98105482A TW 98105482 A TW98105482 A TW 98105482A TW I398967 B TWI398967 B TW I398967B
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substrate
layer
light
emitting diode
semiconductor layer
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TW98105482A
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TW201032349A (en
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Chih Chiang Kao
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Lite On Electronics Guangzhou
Lite On Technology Corp
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Abstract

A light-emitting diode chip includes a substrate, an epitaxial layer unit, two inclined plane units, and two electrode units. The substrate has a surface and a bottom face. The epitaxial layer unit is located on the surface of the substrate. Each of the inclined plane units is inclined downwardly and outwardly from the epitaxial layer unit toward the bottom face of the substrate, and includes an inclined sidewall located at the epitaxial layer unit, and a substrate inclined wall located at the substrate. Each of the electrode units includes an electrode provided on the epitaxial layer unit, and a conductive layer extending from the electrode along the corresponding inclined plane unit to the substrate inclined wall.

Description

發光二極體晶片及其製法Light-emitting diode chip and its preparation method

本發明是有關於一種發光二極體晶片、其製法及封裝方法,特別是指一種封裝體積小且製程速度快的發光二極體晶片、其製法及封裝方法。The invention relates to a light-emitting diode wafer, a method for manufacturing the same and a packaging method thereof, in particular to a light-emitting diode chip with a small package size and a fast processing speed, a method for manufacturing the same, and a packaging method thereof.

如圖1所示,習知發光二極體晶片91通常藉由打線方式與載板92上的外部電極93電連接。由於打線製程需要佔用載板92較大的空間,而且打線過程是用機器一條一條的連接,製程效率極低,不利於系統封裝(system in package)或晶圓級封裝(wafer level package)。As shown in FIG. 1, the conventional light-emitting diode chip 91 is usually electrically connected to the external electrode 93 on the carrier 92 by wire bonding. Since the wire bonding process requires a large space for the carrier plate 92, and the wire bonding process is one by one connection of the machine, the process efficiency is extremely low, which is disadvantageous to a system in package or a wafer level package.

為了改善打線製程的缺點,目前常見的方式是利用覆晶(flip-chip)的方式作電性連結,以省去打線製程。但是覆晶製程需在單顆晶片上植大量金球,過程耗時,也影響封裝效率。除了覆晶方式之外,另有一些不需打線的封裝方式,例如翻轉晶片將位於晶片表面的電極直接與載板上的電極黏著而不使用金球,如此方式則需使晶片表面的電極等高,且具有極佳的平整度,製作精度要求較高,相對使製程難度較高。另一種方式是調整晶片結構,使晶片電極由晶片表面延伸至晶片底面,例如日本專利公開案JP2008-130875所揭示的晶片製造方法,如圖2及圖3所示,是在晶片94上開孔941,鍍上導電層95,使導電層95通過開孔941將晶片94表面的電極96與晶片94底面的電極97連接,而使晶片94電極97可位於其底面處。但是JP2008-130875案中,其界定開孔941的壁面為垂直的壁面,在鍍製導電層時,會有階梯覆蓋性不良的缺點,容易導致導電層不均勻而影響導電性。In order to improve the shortcomings of the wire bonding process, the current common method is to use a flip-chip method for electrical connection to save the wire bonding process. However, the flip chip process requires a large number of gold balls on a single wafer, which is time consuming and affects packaging efficiency. In addition to the flip chip method, there are other packaging methods that do not need to be wired. For example, the flip chip adheres the electrode on the surface of the wafer directly to the electrode on the carrier without using a gold ball. In this way, the electrode on the surface of the wafer needs to be made. High, and has excellent flatness, high production accuracy requirements, relatively difficult to make the process. Another way is to adjust the structure of the wafer so that the wafer electrode extends from the surface of the wafer to the bottom surface of the wafer. For example, the wafer fabrication method disclosed in Japanese Patent Publication No. JP 2008-130875, as shown in FIGS. 2 and 3, is to open a hole in the wafer 94. 941, a conductive layer 95 is plated such that the conductive layer 95 connects the electrode 96 on the surface of the wafer 94 to the electrode 97 on the bottom surface of the wafer 94 through the opening 941, so that the electrode 94 of the wafer 94 can be located at the bottom surface thereof. However, in the case of JP 2008-130875, the wall surface defining the opening 941 is a vertical wall surface, and when the conductive layer is plated, there is a disadvantage of poor step coverage, which tends to cause unevenness of the conductive layer and affect conductivity.

為了解決前述的問題,本發明利用在發光二極體晶片兩側形成傾斜側壁,藉由傾斜側壁產生的斜面,可使導電層容易在斜面上均勻沉積,以避免階梯覆蓋性不良的缺點,並藉由斜面上的導電層,將發光二極體晶片表面的電極延伸至晶片的基板兩側或是基板的底面,有利於後續的封裝製程,更甚者,不需使用到打線,可減小封裝結構的體積。In order to solve the foregoing problems, the present invention utilizes inclined sidewalls formed on both sides of a light-emitting diode wafer, and the inclined surface generated by the inclined sidewalls can make the conductive layer be uniformly deposited on the inclined surface to avoid the disadvantage of poor step coverage. The electrode on the surface of the light-emitting diode wafer is extended to the two sides of the substrate of the wafer or the bottom surface of the substrate by the conductive layer on the inclined surface, which is beneficial to the subsequent packaging process, and moreover, the wire is not required to be used, and the wire can be reduced. The volume of the package structure.

進一步地,本發明亦提供利用半導體製程技術的反射杯的製法及發光二極體的封裝方法,可應用於系統封裝或晶圓級封裝。本發明反射杯的製法僅需利用一次光罩製程即可完成具有反射層的凹槽結構,相較於習知製程需要兩道光罩製程,能夠減少製程時間及製作成本。而本發明提供的封裝方法不需要打線製程即可與封裝載板的導線形成電連接,不僅能夠節省製程時間,增進生產效率,還能縮小封裝結構的體積。Further, the present invention also provides a method for manufacturing a reflective cup using a semiconductor process technology and a method for packaging a light emitting diode, which can be applied to a system package or a wafer level package. The method for manufacturing the reflective cup of the present invention only needs to complete the groove structure with the reflective layer by using a single mask process, and requires two mask processes compared with the conventional process, which can reduce the process time and the manufacturing cost. The packaging method provided by the invention can form an electrical connection with the wires of the package carrier board without a wire bonding process, which not only saves process time, improves production efficiency, but also reduces the volume of the package structure.

更進一步地,本發明還提供一種能夠將發光二極體晶片的電極延伸至封裝載板的底面之封裝方法,且不需在反射杯中開孔,以避免破壞密封晶片的效果,可解決一般由反射杯底部開孔以將電極延伸至封裝載板底部所導致晶片容易受潮以及封裝結構的結構脆弱的問題,而其所製成的封裝結構可直接設置於一應用產品的電路板,不需使用打線製程,除可減少因斷線造成的不良率,提升封裝可靠度,還可使下游應用端的組裝程序更加簡便。Furthermore, the present invention also provides a packaging method capable of extending the electrodes of the LED substrate to the bottom surface of the package carrier, and does not need to be opened in the reflective cup to avoid the effect of destroying the sealing wafer, and can solve the general problem. Opening the hole at the bottom of the reflector cup to extend the electrode to the bottom of the package carrier causes the wafer to be easily wetted and the structure of the package structure is fragile, and the package structure can be directly disposed on the circuit board of an application product without The use of the wire-bonding process can reduce the defect rate caused by wire breakage, improve the reliability of the package, and make the assembly process of the downstream application end easier.

本發明所提供的發光二極體晶片,藉由斜面單元使連接電極之導電層延伸至基板傾斜壁或底面,可將發光二極體晶片固設於封裝載板中直接形成電連接,或利用金屬化製程製作延伸導電層形成電連接,由於不需要打線製程,有助於晶圓級封裝或系統封裝,而能節省一一打線的封裝時間,以及節省打線所佔用的空間以縮小體積,對於整合其他光電元件具有小型化優勢,且與其他LED技術整合,例如奈米晶體製程的整合,也較為彈性。此外,本發明所提供的發光二極體晶片的製法,藉由形成傾斜側壁及基板傾斜壁,以在其斜面上利用金屬化製程沉積導電層,相較於在垂直面上沉積導電層容易控制,故能提昇製程良率,降低製造成本。In the light-emitting diode chip provided by the present invention, the conductive layer of the connection electrode is extended to the inclined wall or the bottom surface of the substrate by the bevel unit, and the light-emitting diode chip can be fixed in the package carrier to directly form an electrical connection, or can be utilized. The metallization process produces an extended conductive layer to form an electrical connection. Since the wire bonding process is not required, it is helpful for wafer level packaging or system packaging, thereby saving the packaging time of one wire and one wire, and saving the space occupied by the wire to reduce the volume. The integration of other optoelectronic components has the advantage of miniaturization, and integration with other LED technologies, such as the integration of nano crystal processes, is also more flexible. In addition, the method for fabricating a light-emitting diode wafer provided by the present invention can form a conductive layer by using a metallization process on the inclined surface thereof by forming the inclined sidewall and the inclined wall of the substrate, which is easier to control than depositing the conductive layer on the vertical surface. Therefore, it can improve the process yield and reduce the manufacturing cost.

本發明所提供的用於發光二極體封裝之反射杯的製法,藉由部分凸伸於凹槽中之保護層的屏蔽,使被覆於凹槽的金層層未超出凹槽開口,而能省去一道光罩製程,以降低製程時間及成本。The method for manufacturing a reflective cup for a light-emitting diode package provided by the present invention, by partially shielding a protective layer protruding in the groove, so that the gold layer covered in the groove does not exceed the groove opening, and Eliminate a mask process to reduce process time and cost.

本發明提供之發光二極體的封裝方法,可在同一封裝載板上完成多數個發光二極體晶片的封裝,亦可不需要打線製程,故更能適用於晶圓級封裝或系統封裝,依據不同的發光二極體晶片結構可選擇適用的方法步驟,將連接晶片電極的導電層延伸出反射杯外,進一步地,還能由反射杯外延伸至封裝載板底面,以維持晶片密封的完整性,使本發明之封裝方法不僅能夠節省封裝製程時間及縮小封裝結構的體積,還能方便下游應用端的組裝程序。The method for packaging a light-emitting diode provided by the invention can complete the packaging of a plurality of light-emitting diode chips on the same package carrier board, and can also be used for wafer level packaging or system packaging, according to the method of packaging the plurality of light-emitting diode chips. Different light-emitting diode structure can select suitable method steps to extend the conductive layer connecting the wafer electrodes out of the reflective cup, and further extend from the outside of the reflective cup to the bottom surface of the package carrier to maintain the integrity of the wafer seal. The packaging method of the present invention not only saves the packaging process time and reduces the volume of the package structure, but also facilitates the assembly process of the downstream application end.

有關本發明之前述及其他技術內容、特點與功效,在以下配合參考圖式之五個較佳實施例的詳細說明中,將可清楚的呈現。The foregoing and other technical aspects, features and advantages of the present invention will be apparent from the Detailed Description of the <RTIgt;

在本發明被詳細描述之前,要注意的是,在以下的說明內容中,類似的元件是以相同的編號來表示。Before the present invention is described in detail, it is noted that in the following description, similar elements are denoted by the same reference numerals.

實施例1Example 1 發光二極體晶片的製作Fabrication of light-emitting diode chips

參閱圖4(a)~圖4(f),說明本發明發光二極體晶片的製法之實施例1的實施步驟流程圖。其實施步驟包含:Referring to Fig. 4 (a) to Fig. 4 (f), a flow chart showing the steps of the first embodiment of the method for fabricating the light-emitting diode wafer of the present invention will be described. The implementation steps include:

如圖4(a)所示,取一已完成磊晶結構的母片10,母片10包括一基板11及一形成於基板11上的磊晶層單元12。磊晶層單元12包括一形成於基板11上的第一型半導體層121、一形成於第一型半導體層121上的發光層122及一形成於發光層122上的第二型半導體層123。在本實施例中,基板11為藍寶石(sapphire)材質,厚度約350μm;第一型半導體層121為n型氮化鎵(n-GaN),第二型半導體層123為p型氮化鎵(p-GaN)。As shown in FIG. 4(a), a master 10 having an epitaxial structure is completed. The master 10 includes a substrate 11 and an epitaxial layer unit 12 formed on the substrate 11. The epitaxial layer unit 12 includes a first type semiconductor layer 121 formed on the substrate 11, a light emitting layer 122 formed on the first type semiconductor layer 121, and a second type semiconductor layer 123 formed on the light emitting layer 122. In this embodiment, the substrate 11 is made of sapphire and has a thickness of about 350 μm; the first type semiconductor layer 121 is n-type gallium nitride (n-GaN), and the second type semiconductor layer 123 is p-type gallium nitride ( p-GaN).

利用半導體製程技術的圖案化製程在母片10上定義出複數個預定形成一晶片的位置及預定形成兩晶片之間的凹槽的位置(圖未示出)。以下步驟要說明如何利用蝕刻及金屬化製程形成各晶片的側壁及電極單元,為方便說明起見,圖式中僅示出兩個相鄰晶片之間的實施過程。如圖4(b)所示,在預定形成凹槽21的位置利用蝕刻製程由第二型半導體層123蝕刻至部分第一型半導體層121,使第一型半導體層121裸露,而形成一開口往外擴張的凹槽21,也就是說在各晶片1之一側形成由第二型半導體層123側往下延伸至部分第一型半導體層121側的一第一斜面131。如圖4(c)所示,再於介於兩晶片1中間之凹槽21底部,即第一型半導體層121的部分裸露表面,定義一第二凹槽22的位置,然後蝕刻第一型半導體層121至基板11表面形成一開口往外擴張的第二凹槽22,而使基板11的部分表面裸露,藉此在各晶片1之一側形成位於第一型半導體層121側邊並相鄰基板11的一第二斜面132及一連接於第一斜面131與第二斜面132的平台133,而第一斜面131、第二斜面132及平台133即形成磊晶層單元12之一往下並往外傾斜的傾斜側壁13。各晶片1之磊晶層單元12的另一側亦由另一組凹槽21及第二凹槽22形成一往下並往外傾斜的傾斜側壁13。前述蝕刻製程可利用乾式蝕刻或濕式蝕刻,可依據磊晶層單元12的材質選用適當的蝕刻方式,此為本發明領域的公知技術,於此不再贅述。值得注意的是,前述形成凹槽21與第二凹槽22的實施步驟僅為實施方式的一種,其亦可利用不同光阻厚度或半色調網點(halftone)製程同時定義出凹槽21與第二凹槽22的位置,並可利用一次蝕刻步驟或兩次蝕刻步驟形成凹槽21與第二凹槽22,不以本實施例為限。A patterning process using semiconductor process technology defines a plurality of locations on the master wafer 10 that are intended to form a wafer and a location that is intended to form a recess between the wafers (not shown). The following steps illustrate how the sidewalls and electrode cells of each wafer can be formed using an etch and metallization process. For ease of illustration, only the implementation between two adjacent wafers is shown. As shown in FIG. 4(b), a portion of the first type semiconductor layer 121 is etched by the second type semiconductor layer 123 by an etching process at a position where the groove 21 is formed, so that the first type semiconductor layer 121 is exposed to form an opening. The groove 21 which is expanded outward, that is, a first inclined surface 131 which extends from the side of the second-type semiconductor layer 123 to the side of the portion of the first-type semiconductor layer 121 is formed on one side of each wafer 1. As shown in FIG. 4(c), the bottom portion of the recess 21 between the two wafers 1, that is, the exposed surface of the first type semiconductor layer 121, defines the position of a second recess 22, and then etches the first type. A surface of the semiconductor layer 121 to the surface of the substrate 11 is formed with a second recess 22 which is expanded outwardly, and a part of the surface of the substrate 11 is exposed, thereby forming a side of the first type semiconductor layer 121 on one side of each wafer 1 and adjacent thereto. a second inclined surface 132 of the substrate 11 and a platform 133 connected to the first inclined surface 131 and the second inclined surface 132, and the first inclined surface 131, the second inclined surface 132 and the platform 133 form one of the epitaxial layer units 12 and The inclined side wall 13 is inclined outward. The other side of the epitaxial layer unit 12 of each wafer 1 is also formed by another set of recesses 21 and second recesses 22 into a sloping side wall 13 which is inclined downward and outward. The etching process may be performed by dry etching or wet etching, and an appropriate etching method may be selected according to the material of the epitaxial layer unit 12. This is a well-known technique in the field of the invention, and details are not described herein. It should be noted that the foregoing steps of forming the recess 21 and the second recess 22 are only one of the embodiments, and the recess 21 and the second recess can also be defined by using different photoresist thickness or halftone halftone processes. The position of the two recesses 22, and the recess 21 and the second recess 22 may be formed by one etching step or two etching steps, not limited to this embodiment.

如圖4(d)所示,在第二凹槽22底部,即裸露的基板11表面,蝕刻形成一開口往外擴張的基板凹槽23,藉此於基板凹槽23兩側的晶片1分別形成一與其相鄰的傾斜側壁13同向傾斜的基板傾斜壁14。同樣地,各晶片1的基板11之另一側同時形成另一基板凹槽23,並形成另一與其相鄰的傾斜側壁13同向傾斜的基板傾斜壁14。此處蝕刻製程同樣可利用乾式蝕刻或濕式蝕刻,在本實施例中,是利用濕式蝕刻方式,以磷酸與水混合並加熱作為蝕刻液蝕刻基板11,使基板傾斜壁14的傾斜角約介於40~60度。As shown in FIG. 4(d), at the bottom of the second recess 22, that is, the surface of the exposed substrate 11, a substrate recess 23 which is expanded outward is formed by etching, whereby the wafers 1 on both sides of the substrate recess 23 are respectively formed. A substrate inclined wall 14 that is inclined in the same direction as the adjacent inclined side walls 13. Similarly, the other side of the substrate 11 of each wafer 1 is simultaneously formed with another substrate recess 23, and another substrate inclined wall 14 which is inclined in the same direction as the adjacent inclined side walls 13 is formed. Here, the etching process can also utilize dry etching or wet etching. In the present embodiment, the substrate 11 is etched by using a wet etching method by mixing phosphoric acid with water and heating as an etching solution, so that the tilt angle of the substrate inclined wall 14 is about Between 40 and 60 degrees.

如圖4(e)所示,利用金屬化製程,於各晶片1上形成二電極單元,分別為一與第一型半導體層121形成電連接之第一電極單元151,及一與第二型半導體層123形成電連接之第二電極單元152。第一電極單元151包括一設於其中一傾斜側壁13之平台133表面之電極1511,及一由電極1511沿相鄰的第二斜面132延伸至基板傾斜壁14上的導電層1512。第二電極單元152包括一設於第二型半導體層123表面之電極1521,及一由電極1521沿另一傾斜側壁13延伸至基板傾斜壁14上的導電層1522。而且第二電極單元152的導電層1522與對應的傾斜側壁13之間先形成有一絕緣層153,以避免第一電極單元151與第二電極單元152短路。第一電極單元151與第二電極單元152在晶片1上的分佈可配合參閱圖5的俯視圖。在形成電極1521前,亦可在第二型半導體層123表面被覆透明電極,如氧化銦錫(ITO)膜(圖未示出)以增加導電均勻性。As shown in FIG. 4(e), a two-electrode unit is formed on each of the wafers 1 by a metallization process, and is a first electrode unit 151 electrically connected to the first-type semiconductor layer 121, and a first type and a second type. The semiconductor layer 123 forms a second electrode unit 152 that is electrically connected. The first electrode unit 151 includes an electrode 1511 disposed on a surface of the platform 133 of one of the inclined sidewalls 13, and a conductive layer 1512 extending from the electrode 1511 along the adjacent second slope 132 to the substrate inclined wall 14. The second electrode unit 152 includes an electrode 1521 disposed on the surface of the second type semiconductor layer 123, and a conductive layer 1522 extending from the electrode 1521 along the other inclined sidewall 13 to the substrate inclined wall 14. Moreover, an insulating layer 153 is formed between the conductive layer 1522 of the second electrode unit 152 and the corresponding inclined sidewall 13 to prevent the first electrode unit 151 from being short-circuited with the second electrode unit 152. The distribution of the first electrode unit 151 and the second electrode unit 152 on the wafer 1 can be coordinated with reference to the top view of FIG. 5. Before the electrode 1521 is formed, a transparent electrode such as an indium tin oxide (ITO) film (not shown) may be coated on the surface of the second type semiconductor layer 123 to increase the uniformity of conduction.

如圖4(f)所示,研磨位於磊晶層單元12相反側的基板11之底面111,將各基板凹槽23磨穿,使各基板傾斜壁14上的導電層1512、1522露出底面111。在本實施中,研磨後的基板11厚度約為50~100μm。之後,切割母片10以形成多數個獨立的晶片1。As shown in FIG. 4(f), the bottom surface 111 of the substrate 11 on the opposite side of the epitaxial layer unit 12 is ground, and the substrate recesses 23 are worn through, so that the conductive layers 1512 and 1522 on the inclined walls 14 of the substrate are exposed to the bottom surface 111. . In the present embodiment, the thickness of the substrate 11 after polishing is about 50 to 100 μm. Thereafter, the mother wafer 10 is cut to form a plurality of individual wafers 1.

發光二極體晶片Light-emitting diode chip

如圖6所示,前述步驟製得之晶片1為本發明發光二極體晶片之實施例1,包含:一基板11、一磊晶層單元12、二斜面單元16及二電極單元151、152。基板11具有一表面112及一底面111。磊晶層單元12位於基板11的表面112,並包括一第一型半導體層121、一發光層122及一第二型半導體層123,第一型半導體層121位於基板11表面112,且發光層122位於第一型半導體層121與第二型半導體層123之間。二斜面單元16分別位於兩對側邊,各斜面單元16係由磊晶層單元12朝基板11的底面111方向往下並往外傾斜,各包括位於磊晶層單元12之一傾斜側壁13,及位於基板11之一基板傾斜壁14。各傾斜側壁13還包括一由第二型半導體層123側往下延伸至部分第一型半導體層121側的第一斜面131及一相鄰基板11的第二斜面132,而第一斜面131與第二斜面132之間由一平台133相連接。二電極單元151、152分別為一與第一型半導體層121電性連接之第一電極單元151,以及一與第二型半導體層123電性連接之第二電極單元152。第一電極單元151包括一設於其中一傾斜側壁13之平台133表面的電極1511及及一由電極1511沿相鄰的第二斜面132延伸至基板傾斜壁14上的導電層1512。第二電極單元152包括一設於第二型半導體層123表面之電極1521,及一由電極1521沿另一傾斜側壁13延伸至基板傾斜壁14上的導電層1522。而且第二電極單元152的導電層1522與對應的傾斜側壁13之間還設有一絕緣層153。此外,基板11亦可為具導電性之基板,若基板具有導電性時,需在基板傾斜壁上設絕緣層。在本實施例中,基板傾斜壁14之傾斜角約介於40-60度,有利於封裝時再封裝載板上鍍製延伸導電層與導電層1512、1522相連接,有關發光二極體晶片1的封裝方式,將於下文中說明。As shown in FIG. 6 , the wafer 1 obtained in the foregoing step is the first embodiment of the present invention, including a substrate 11 , an epitaxial layer unit 12 , two inclined surface units 16 , and two electrode units 151 and 152 . . The substrate 11 has a surface 112 and a bottom surface 111. The epitaxial layer unit 12 is located on the surface 112 of the substrate 11 and includes a first type semiconductor layer 121, a light emitting layer 122 and a second type semiconductor layer 123. The first type semiconductor layer 121 is located on the surface 112 of the substrate 11, and the light emitting layer 122 is located between the first type semiconductor layer 121 and the second type semiconductor layer 123. The two beveling units 16 are respectively located on the two opposite sides, and each of the inclined surface units 16 is inclined downward and outward by the epitaxial layer unit 12 toward the bottom surface 111 of the substrate 11, each of which includes an inclined side wall 13 of the epitaxial layer unit 12, and Located on one of the substrate 11 inclined walls 14. Each of the inclined sidewalls 13 further includes a first inclined surface 131 extending from the side of the second-type semiconductor layer 123 to a portion of the first-type semiconductor layer 121 and a second inclined surface 132 of an adjacent substrate 11, and the first inclined surface 131 and The second inclined faces 132 are connected by a platform 133. The two electrode units 151 and 152 are respectively a first electrode unit 151 electrically connected to the first type semiconductor layer 121 and a second electrode unit 152 electrically connected to the second type semiconductor layer 123. The first electrode unit 151 includes an electrode 1511 disposed on a surface of the platform 133 of one of the inclined sidewalls 13 and a conductive layer 1512 extending from the electrode 1511 along the adjacent second slope 132 to the substrate inclined wall 14. The second electrode unit 152 includes an electrode 1521 disposed on the surface of the second type semiconductor layer 123, and a conductive layer 1522 extending from the electrode 1521 along the other inclined sidewall 13 to the substrate inclined wall 14. Moreover, an insulating layer 153 is further disposed between the conductive layer 1522 of the second electrode unit 152 and the corresponding inclined sidewall 13. Further, the substrate 11 may be a substrate having conductivity. When the substrate has electrical conductivity, an insulating layer is provided on the inclined wall of the substrate. In this embodiment, the tilt angle of the substrate inclined wall 14 is about 40-60 degrees, which is advantageous for the connection of the plated extended conductive layer and the conductive layer 1512, 1522 on the repackage carrier during packaging, and the related light emitting diode chip The package method of 1 will be explained below.

發光二極體的封裝LED package

圖7(a)~(g)說明本發明發光二極體的封裝方法之實施例1的實施流程,其中圖7(a)~圖7(d)還說明本發明之反射杯的製法。如圖7(a)所示,在一封裝載板3上形成一保護層31,再圖案化保護層31,以形成一貫穿保護層31之穿孔311。在本實施例中,封裝載板3材質為矽,保護層31材質為SiNx 。封裝載板3亦可為其他不導電材質,例如氮化鋁或氧化鋁等陶瓷材料。保護層31材質也可為SiOx 、SiNx /SiOx 、或金屬(例如Ni、Au)等,保護層31的形成方法可依據其材質選用,例如非金屬材質可用氣相沉積法(CVD)、或高濕高溫爐製程,金屬材質可用電鍍、濺鍍或蒸鍍等方式。7(a) to 7(g) are views showing an implementation flow of the first embodiment of the package method of the light-emitting diode of the present invention, and Figs. 7(a) to 7(d) also illustrate the method of manufacturing the reflector cup of the present invention. As shown in FIG. 7(a), a protective layer 31 is formed on a loading plate 3, and the protective layer 31 is patterned to form a through hole 311 penetrating the protective layer 31. In this embodiment, the package carrier 3 is made of 矽, and the protective layer 31 is made of SiN x . The package carrier 3 may also be other non-conductive materials such as ceramic materials such as aluminum nitride or aluminum oxide. The material of the protective layer 31 may be SiO x , SiN x /SiO x , or metal (for example, Ni, Au), etc. The formation method of the protective layer 31 may be selected according to the material thereof, for example, a non-metal material may be formed by vapor deposition (CVD). Or high-humidity high-temperature furnace process, metal materials can be electroplated, sputtered or evaporated.

如圖7(b)所示,利用蝕刻液通過穿孔311蝕刻封裝載板3,形成一開口321大於穿孔311之凹槽32,使相鄰穿孔311之部分保護層31凸伸於凹槽32中。在本實施例中,蝕刻液為KOH溶液,濃度30vol%之KOH溶液於80℃或濃度45vol%之KOH溶液於85℃條件下,蝕刻速率約為1μm/min。蝕刻液的選用可依據實際需求調整,不以本實施例為限。As shown in FIG. 7(b), the package carrier 3 is etched through the via 311 by using an etchant to form a recess 32 having an opening 321 larger than the through hole 311, so that a portion of the protective layer 31 of the adjacent via 311 protrudes into the recess 32. . In the present embodiment, the etching solution is a KOH solution, and the KOH solution having a concentration of 30 vol% is etched at a temperature of 80 ° C or a 45 vol% KOH solution at 85 ° C, and the etching rate is about 1 μm/min. The selection of the etching solution can be adjusted according to actual needs, and is not limited to the embodiment.

如圖7(c)所示,於保護層31及凹槽32上形成一金屬層33、34,且藉由部分凸伸於凹槽32中之保護層31的屏蔽,使凹槽32相鄰保護層31處(鄰近開口321處)未被覆金屬層34。金屬層33、34可藉由濺鍍或蒸鍍方式沉積,材質可為Ti/Al、Ti/Ni/Ag或其他可用以反射光線的一般常見的反射層材質。As shown in FIG. 7(c), a metal layer 33, 34 is formed on the protective layer 31 and the recess 32, and the recess 32 is adjacent by the shielding of the protective layer 31 partially protruding in the recess 32. The protective layer 31 (near the opening 321) is not covered with the metal layer 34. The metal layers 33, 34 can be deposited by sputtering or evaporation, and the material can be Ti/Al, Ti/Ni/Ag or other common reflective layer materials that can be used to reflect light.

如圖7(d)所示,移除保護層31及位於保護層31上的金屬層33,剩下在凹槽32中的金屬層34,即形成一位於凹槽32中的反射杯34。藉由前述步驟形成的反射杯34只有在圖案化保護層31時需用到一道光罩製程以定義穿孔311位置,再利用保護層31的屏蔽,使得鄰近凹槽32開口321處沒有沉積金屬層34,所以反射杯34不會超出凹槽32開口321,而能省去定義反射杯34開口區域以避免超出凹槽32開口321的光罩製程。As shown in FIG. 7(d), the protective layer 31 and the metal layer 33 on the protective layer 31 are removed, leaving the metal layer 34 in the recess 32, that is, forming a reflective cup 34 in the recess 32. The reflective cup 34 formed by the foregoing steps only needs to use a mask process to define the position of the through hole 311 when the protective layer 31 is patterned, and then shields the protective layer 31 so that no metal layer is deposited near the opening 321 of the groove 32. 34, so the reflector cup 34 does not extend beyond the opening 321 of the recess 32, and the reticle process that defines the open area of the reflector cup 34 to avoid exceeding the opening 321 of the recess 32 can be eliminated.

如圖7(e)所示,取前述製得的一發光二極體晶片1固設於反射杯34中。更進一步的說,發光二極體晶片1係利用一固晶膠38固定於反射杯34內,在本實施例中,固晶膠38為絕緣材質,使得第一電極單元151的導電層1512與第二電極單元152的導電層1522與反射杯34電性分離。As shown in FIG. 7(e), a light-emitting diode wafer 1 obtained as described above is fixed in the reflective cup 34. Further, the LED chip 1 is fixed in the reflective cup 34 by a die bonding adhesive 38. In the embodiment, the die bonding adhesive 38 is made of an insulating material, so that the conductive layer 1512 of the first electrode unit 151 is The conductive layer 1522 of the second electrode unit 152 is electrically separated from the reflective cup 34.

再如圖7(f)所示,以金屬化製程形成二延伸導電層35,各延伸導電層35分別連接發光二極體晶片1之第一電極單元151的導電層1512與第二電極單元152的導電層1522,且由基板傾斜壁14處連接,當然亦可由傾斜側壁13處連接,使第一電極單元151與第二電極單元152藉由各延伸導電層35延伸出反射杯34外的封裝載板3上,在本實施例中,由於反射杯34與封裝載板3均為導電體,所以在形成延伸導電層35之前,需先在反射杯34及封裝載板3上預定形成延伸導電層35的位置形成一絕緣層36,以避免延伸導電層35與反射杯34及封裝載板3接觸。如圖7(g)所示,於反射杯34中填充透光膠材37,以密封發光二極體晶片1。透光膠材37可含有螢光粉或不含螢光粉,視使用需求而定。Further, as shown in FIG. 7(f), two extended conductive layers 35 are formed by a metallization process, and each of the extended conductive layers 35 is respectively connected to the conductive layer 1512 and the second electrode unit 152 of the first electrode unit 151 of the light-emitting diode wafer 1. The conductive layer 1522 is connected by the inclined wall 14 of the substrate, and may of course be connected by the inclined sidewalls 13 so that the first electrode unit 151 and the second electrode unit 152 extend out of the reflective cup 34 by the extended conductive layers 35. On the carrier 3, in this embodiment, since the reflective cup 34 and the package carrier 3 are both electrically conductive, it is necessary to form an extended conductive on the reflective cup 34 and the package carrier 3 before forming the extended conductive layer 35. The location of the layer 35 forms an insulating layer 36 to prevent the extended conductive layer 35 from contacting the reflective cup 34 and the package carrier 3. As shown in FIG. 7(g), the reflective cup 34 is filled with a light-transmitting adhesive 37 to seal the light-emitting diode wafer 1. The light-transmitting adhesive 37 may contain fluorescent powder or no fluorescent powder, depending on the needs of use.

雖然本實施例中發光二極體晶片1是設置在反射杯34中,但是前述形成延伸導電層35的實施步驟也可適用於一般載板,或是一般反射杯。Although the light-emitting diode wafer 1 is disposed in the reflective cup 34 in the present embodiment, the foregoing steps of forming the extended conductive layer 35 can also be applied to a general carrier or a general reflective cup.

實施例2Example 2 發光二極體晶片的製作Fabrication of light-emitting diode chips

本發明發光二極體晶片的製法之實施例2的實施步驟與實施例1大致相同,可配合參閱圖4(a)~圖4(f),其差異之處在於,如圖8所示,在研磨基板11’的底面111’以露出各基板傾斜壁14’的導電層1512’、1522’後,實施例2利用金屬化製程在底面111’形成二分別與各基板傾斜壁14’的導電層1512’、1522’連接的導電層1513’、1523’,使第一、第二電極單元151’、152’的導電層1512’、1513’、1522’、1523’延伸至基板11’底面111’。此外,在該金屬化製程步驟前,亦可進一步地包含將底面111’拋光以提供一較平坦與光滑表面的步驟。之後,切割母片10’上的各晶片1’以形成多數個獨立的晶片1’。The implementation steps of Embodiment 2 of the method for fabricating a light-emitting diode wafer of the present invention are substantially the same as those of Embodiment 1, and can be referred to FIG. 4(a) to FIG. 4(f). The difference is that, as shown in FIG. After the bottom surface 111' of the substrate 11' is polished to expose the conductive layers 1512', 1522' of the substrate inclined walls 14', the second embodiment forms a conductive relationship with the substrate inclined walls 14' on the bottom surface 111' by a metallization process. The conductive layers 1513', 1523' connected to the layers 1512', 1522' extend the conductive layers 1512', 1513', 1522', 1523' of the first and second electrode units 151', 152' to the bottom surface 111 of the substrate 11' '. Additionally, prior to the metallization process step, the step of polishing the bottom surface 111' to provide a relatively flat and smooth surface may be further included. Thereafter, each wafer 1' on the mother substrate 10' is cut to form a plurality of individual wafers 1'.

發光二極體晶片Light-emitting diode chip

如圖9所示,前述步驟製得之晶片1’為本發明發光二極體晶片之實施例2,與實施例1大致相同,其所差異之處在於,實施例2的第一電極單元151’含包括一延伸於基板11’底面111’的導電層1513’,且第二電極單元152’含包括一延伸於基板11’底面111’的導電層1523’。As shown in FIG. 9, the wafer 1' obtained in the foregoing step is the second embodiment of the light-emitting diode wafer of the present invention, which is substantially the same as the first embodiment, and is different in the first electrode unit 151 of the second embodiment. 'Contains a conductive layer 1513' extending over the bottom surface 111' of the substrate 11', and the second electrode unit 152' includes a conductive layer 1523' extending from the bottom surface 111' of the substrate 11'.

發光二極體的封裝LED package

圖10(a)~(c)說明本發明發光二極體的封裝方法之實施例2的實施流程,用以封裝前述之發光二極體晶片1’。Figs. 10(a) through 10(c) are views showing an implementation flow of the second embodiment of the package method of the light-emitting diode of the present invention for encapsulating the above-described light-emitting diode wafer 1'.

如圖10(a)所示,先於反射杯34’中定義預定設置發光二極體晶片1’底面111’之二導電層1513’、1523’的位置(圖未標號),並利用金屬化製程形成二延伸導電層35’,使各延伸導電層35’分別由各導電層1513’、1523’之預定位置延伸至反射杯34’外的封裝載板3’上。在本實施例中,形成反射杯34’的實施步驟與實施例1相同,可參閱圖7(a)~圖7(d)。由於反射杯34’與封裝載板3’均為導電體,所以在形成延伸導電層35’之前,需先在反射杯34’及封裝載板3’上預定形成延伸導電層35’的位置形成一絕緣層36’,以避免延伸導電層35’與反射杯34’及封裝載板3’接觸。As shown in FIG. 10(a), the position (not shown) of the two conductive layers 1513', 1523' of the bottom surface 111' of the light-emitting diode wafer 1' is predetermined to be defined in the reflective cup 34', and metallization is utilized. The process forms two extended conductive layers 35' such that each of the extended conductive layers 35' extends from a predetermined position of each of the conductive layers 1513', 1523' to the package carrier 3' outside the reflective cup 34'. In the present embodiment, the steps of forming the reflecting cup 34' are the same as those of the first embodiment, and reference is made to Figs. 7(a) to 7(d). Since the reflective cup 34' and the package carrier 3' are both electrically conductive, it is necessary to form the extended conductive layer 35' on the reflective cup 34' and the package carrier 3' before forming the extended conductive layer 35'. An insulating layer 36' prevents the extended conductive layer 35' from coming into contact with the reflective cup 34' and the package carrier 3'.

如圖10(b)所示,將一發光二極體晶片1’固設於反射杯34’中,並使二導電層1513’、1523’分別與相對應之各延伸導電層35’電連接。As shown in FIG. 10(b), a light-emitting diode wafer 1' is fixed in the reflective cup 34', and the two conductive layers 1513', 1523' are electrically connected to the corresponding extended conductive layers 35', respectively. .

如圖10(c)所示,於反射杯34’中填充透光膠材37’,以密封發光二極體晶片1’。透光膠材37’可含有螢光粉或不含螢光粉,視使用需求而定。As shown in Fig. 10 (c), the reflective cup 34' is filled with a light-transmitting adhesive 37' to seal the light-emitting diode wafer 1'. The light-transmitting adhesive 37' may contain phosphor powder or no phosphor powder, depending on the needs of use.

雖然本實施例中發光二極體晶片1’是設置在反射杯34’中,但是前述形成延伸導電層35’再與發光二極體晶片1’相接的實施步驟也可適用於一般載板,或是一般反射杯。Although the light-emitting diode wafer 1' is disposed in the reflective cup 34' in this embodiment, the foregoing step of forming the extended conductive layer 35' and then contacting the light-emitting diode wafer 1' can also be applied to a general carrier. Or a general reflector cup.

實施例3Example 3

圖11(a)~圖11(f)說明本發明發光二極體封裝方法的實施例3。11(a) to 11(f) illustrate a third embodiment of the light emitting diode packaging method of the present invention.

如圖11(a)所示,先分別在一封裝載板41的正面411及背面412被覆一保護層42,再圖案化保護層42形成複數穿孔421、422,以定義預訂設置反射杯的凹槽位置421,及分別位於凹槽位置421兩側預定設置穿槽44(參閱圖11(b))的穿槽位置422。位於正面411與背面412的穿槽位置422上下相對應。如圖11(b)所示,再利用蝕刻液蝕刻封裝載板41,通過保護層42的穿孔421在封裝載板41正面411形成一預定設置反射杯471(參閱圖11(c))的凹槽43,使凹槽43的開口431大於穿孔421,並且通過各穿孔422由封裝載板41的正面411及背面412相對蝕刻而形成二分別鄰近凹槽43的穿槽44。藉由每一穿槽44形成其相鄰兩封裝結構4的側壁45,且各側壁45具有一由封裝載板41正面411往中間外傾的上傾斜面451及一由封裝載板41背面412往中間外傾的下傾斜面452。在本實施例中,封裝載板41的材質為矽,保護層42的材質及蝕刻方式可參照實施例1,於此不再重述。As shown in FIG. 11(a), a protective layer 42 is first coated on the front surface 411 and the back surface 412 of a loading plate 41, and the protective layer 42 is patterned to form a plurality of through holes 421 and 422 to define a concave shape for which the reflecting cup is reserved. The groove position 421 and the grooved position 422 of the groove 44 (see FIG. 11(b)) are disposed on both sides of the groove position 421, respectively. The front surface 411 corresponds to the grooved position 422 of the back surface 412. As shown in FIG. 11(b), the package carrier 41 is etched by an etching solution, and a recessed portion 411 of the protective layer 42 is formed on the front surface 411 of the package carrier 41 to form a concave portion for which a reflecting cup 471 (see FIG. 11(c)) is disposed. The groove 43 is such that the opening 431 of the groove 43 is larger than the through hole 421, and is etched by the front surface 411 and the back surface 412 of the package carrier 41 through the respective through holes 422 to form two through grooves 44 respectively adjacent to the groove 43. The sidewalls 45 of the two adjacent package structures 4 are formed by each of the slots 44, and each of the sidewalls 45 has an upper inclined surface 451 which is outwardly tilted from the front surface 411 of the package carrier 41 and a rear surface 412 of the package carrier 41. A downwardly inclined surface 452 that is outwardly inclined toward the center. In the present embodiment, the material of the package carrier 41 is 矽, and the material and etching method of the protective layer 42 can be referred to the first embodiment, and will not be repeated here.

如圖11(c)所示,再由封裝載板41正面411沉積一金屬層47,使凹槽43及各穿槽44的上傾斜面451被覆金屬層47,其中凹槽43與保護層42相鄰處未被覆金屬層47,而於凹槽43內形成一反射杯471。As shown in FIG. 11(c), a metal layer 47 is further deposited on the front surface 411 of the package carrier 41, so that the recess 43 and the upper inclined surface 451 of each of the slots 44 are covered with a metal layer 47, wherein the recess 43 and the protective layer 42 are provided. The adjacent portion is not covered with the metal layer 47, and a reflective cup 471 is formed in the recess 43.

如圖11(d)所示,移除封裝載板41正面411與背面412的保護層42,由於本實施例之封裝載板41具有導電性,移除保護層42後,由封裝載板41的正面411與背面412沉積絕緣層46。As shown in FIG. 11(d), the protective layer 42 of the front surface 411 and the rear surface 412 of the package carrier 41 is removed. Since the package carrier 41 of the present embodiment has conductivity, after the protective layer 42 is removed, the package carrier 41 is removed. An insulating layer 46 is deposited on the front side 411 and the back side 412.

如圖11(e)所示,利用金屬化製程在封裝載板41的背面412形成具有預定圖案的導電層48,包括二分別由封裝載板41背面412延伸至各下傾斜面452的下導電層481,及一位於封裝載板41背面412的傳導區482,傳導區482可供與外部散熱裝置(圖未示出)導接。或者,導電層48亦可由lift-off製程製作。As shown in FIG. 11(e), a conductive layer 48 having a predetermined pattern is formed on the back surface 412 of the package carrier 41 by a metallization process, including two lower conductive layers respectively extending from the back surface 412 of the package carrier 41 to the respective lower inclined surfaces 452. Layer 481, and a conductive region 482 on the back side 412 of the package carrier 41, the conductive region 482 is adapted to be coupled to an external heat sink (not shown). Alternatively, conductive layer 48 can also be fabricated by a lift-off process.

如圖11(f)所示,取如實施例1所述的發光二極體晶片1固設於反射杯471中,配合參閱圖7(e)~圖7(g)所述的步驟,本實施例3進一步使實施例1中的延伸導電層35延伸至各上傾斜面451形成二上導電層483,各上導電層483分別與相對應的各下導電層481相連接且分別與第一電極單元151及第二電極單元152電連接,使第一、第二電極單元151、152可延伸至封裝載板41的背面412。再於反射杯471中填充一透光膠材49將發光二極體晶片1密封,以形成一封裝結構4。透光膠材49可視需求含有螢光粉或不含螢光粉。前述實施步驟可在同一封裝載板41上完成多數個封裝結構4,經由切割後可製得多數個獨立的封裝結構4,各獨立的封裝結構4可直接設置於一應用產品的電路板(圖未示出),不需使用打線製程,而方便下游應用端的組裝程序。As shown in FIG. 11(f), the light-emitting diode wafer 1 as described in the first embodiment is fixed in the reflective cup 471, and the steps described in FIGS. 7(e) to 7(g) are used. Embodiment 3 further extends the extended conductive layer 35 of Embodiment 1 to each of the upper inclined faces 451 to form two upper conductive layers 483, and each of the upper conductive layers 483 is respectively connected to the corresponding lower conductive layer 481 and respectively respectively The electrode unit 151 and the second electrode unit 152 are electrically connected such that the first and second electrode units 151, 152 can extend to the back surface 412 of the package carrier 41. The light-emitting adhesive material 49 is filled in the reflective cup 471 to seal the light-emitting diode wafer 1 to form a package structure 4. The light-transmitting adhesive 49 may contain fluorescent powder or no fluorescent powder as needed. The foregoing implementation steps can complete a plurality of package structures 4 on the same package carrier 41. After cutting, a plurality of independent package structures 4 can be fabricated, and the individual package structures 4 can be directly disposed on a circuit board of an application product. Not shown), the wire bonding process is not required, and the assembly process of the downstream application end is facilitated.

實施例3的封裝方式利用在反射杯471外部的穿槽44,使上導電層483與下導電層481相連接,可避免破壞發光二極體晶片1的密封性,而且上導電層483與下導電層481分別形成在上傾斜面451與下傾斜面452,藉由斜面可使金屬層容易沉積,而能提昇製程良率。The packaging method of Embodiment 3 utilizes the through-groove 44 outside the reflective cup 471 to connect the upper conductive layer 483 with the lower conductive layer 481, thereby avoiding damage to the sealing property of the LED wafer 1, and the upper conductive layer 483 and the lower layer. The conductive layer 481 is formed on the upper inclined surface 451 and the lower inclined surface 452, respectively, and the metal layer can be easily deposited by the inclined surface, thereby improving the process yield.

實施例4Example 4

實施例4係封裝發光二極體晶片1’(參閱圖9)的另一實施方式,其實施步驟部分與實施例3的實施步驟相同,參閱圖11(a)~圖11(d)。接著參閱圖12(a),利用金屬化製程在封裝載板41的背面412形成具有預定圖案的導電層48,包括二分別由封裝載板41背面412延伸至各下傾斜面452的下導電層481,及一位於封裝載板41背面412的傳導區482,傳導區482可供與外部散熱裝置(圖未示出)導接。並且於反射杯471中定義預定設置發光二極體晶片1’底面之第一、第二電極單元151’、152’的導電層1513’、1523’之位置,再利用金屬化製程形成二上導電層483’,使各上導電層483’分別由第一、第二電極單元151’、152’之預定位置(圖未標號)延伸至各上傾斜面451,而與各下導電層481相連接。同樣地,導電層48及上電導電層483’亦可利用lift-off製程製作。Embodiment 4 is another embodiment in which the light-emitting diode wafer 1' (see Fig. 9) is packaged, and the implementation steps are the same as those of the embodiment 3, and reference is made to Figs. 11(a) to 11(d). Referring next to FIG. 12(a), a conductive layer 48 having a predetermined pattern is formed on the back surface 412 of the package carrier 41 by a metallization process, including two lower conductive layers extending from the back surface 412 of the package carrier 41 to the respective lower inclined surfaces 452, respectively. 481, and a conductive region 482 on the back side 412 of the package carrier 41, the conductive region 482 is adapted to be coupled to an external heat sink (not shown). And defining, in the reflective cup 471, the positions of the conductive layers 1513 ′, 1523 ′ of the first and second electrode units 151 ′, 152 ′ of the bottom surface of the light-emitting diode wafer 1 ′ are disposed, and then forming a conductive layer by using a metallization process. The layer 483' is such that each of the upper conductive layers 483' is extended from the predetermined positions (not labeled) of the first and second electrode units 151', 152' to the respective upper inclined surfaces 451, and is connected to the respective lower conductive layers 481. . Similarly, conductive layer 48 and upper conductive layer 483' can also be fabricated using a lift-off process.

參閱圖12(b),固設發光二極體晶片1’於反射杯471中,並使二導電層1513’、1523’分別與相對應之各上導電層483’電連接,亦即,使各上導電層483’分別與相對應之第一、第二電極單元151’、152’電連接。再於反射杯471中填充透光膠材49,以密封發光二極體晶片1’。透光膠材49可含有螢光粉或不含螢光粉,視使用需求而定。Referring to FIG. 12(b), the LED chip 1' is fixed in the reflective cup 471, and the two conductive layers 1513', 1523' are electrically connected to the corresponding upper conductive layers 483', that is, Each of the upper conductive layers 483' is electrically connected to the corresponding first and second electrode units 151', 152', respectively. The light-transmitting paste 49 is further filled in the reflective cup 471 to seal the light-emitting diode wafer 1'. The light-transmitting adhesive 49 may contain fluorescent powder or no fluorescent powder, depending on the needs of use.

實施例5Example 5

圖13(a)~圖13(h)說明本發明發光二極體封裝方法的實施例5的實施步驟。實施例5的實施步驟可用於封裝一般電極位於正面的發光二極體晶片5。13(a) to 13(h) illustrate the implementation steps of the embodiment 5 of the light-emitting diode packaging method of the present invention. The implementation steps of Embodiment 5 can be used to package a light-emitting diode wafer 5 having a general electrode on the front side.

參閱圖13(a)及圖13(b),其實施步驟與實施例3的圖11(a)與圖11(b)大致相同,在封裝載板41上形成一凹槽43與二穿槽44,惟,保護層42與封裝基板41之間還有一絕緣層46。13(a) and 13(b), the implementation steps are substantially the same as those of FIG. 11(a) and FIG. 11(b) of the third embodiment, and a groove 43 and a second groove are formed in the package carrier 41. 44. However, there is an insulating layer 46 between the protective layer 42 and the package substrate 41.

參閱圖13(c),將凹槽43及穿槽44的裸露表面氧化形成氧化層以作為絕緣層46’。Referring to Fig. 13 (c), the exposed surface of the recess 43 and the through groove 44 is oxidized to form an oxide layer as the insulating layer 46'.

參閱圖13(d),再由封裝載板41正面411沉積一金屬層47,使凹槽43及各穿槽44的上傾斜面451被覆金屬層47,其中凹槽43與保護層42相鄰處未被覆金屬層47,而於凹槽43內形成一反射杯471。Referring to FIG. 13(d), a metal layer 47 is deposited from the front surface 411 of the package carrier 41 such that the recess 43 and the upper inclined surface 451 of each of the through slots 44 are covered with a metal layer 47, wherein the recess 43 is adjacent to the protective layer 42. The metal layer 47 is not covered, and a reflective cup 471 is formed in the recess 43.

參閱圖13(e),移除封裝載板41正面411與背面412的保護層42,並利用金屬化製程在封裝載板41的背面412形成具有預定圖案的導電層48,包括二分別由封裝載板41背面412延伸至各下傾斜面452的下導電層481,及一位於封裝載板41背面412的傳導區482,傳導區482可供與外部散熱裝置(圖未示出)導接。Referring to FIG. 13(e), the protective layer 42 of the front surface 411 and the rear surface 412 of the package carrier 41 is removed, and a conductive layer 48 having a predetermined pattern is formed on the back surface 412 of the package carrier 41 by a metallization process, including two packages respectively. The back surface 412 of the carrier board 41 extends to the lower conductive layer 481 of each of the lower inclined surfaces 452, and a conductive region 482 on the back surface 412 of the package carrier 41. The conductive region 482 is for guiding with an external heat sink (not shown).

參閱圖13(f),將一發光二極體晶片5固設在反射杯471中,設置二導電塊51於該發光二極體晶片5的二電極上(圖未標號),其中在發光二極體晶片5的各電極上分別設置一導電塊51,使該等導電塊51凸出反射杯471外。在本實施例中,各導電塊51為高度約50~100μm之金球。雖然本實施例是先固設發光二極體晶片5再設置導電塊51,但是也可以先設置導電塊51後,再將發光二極體晶片5固設於反射杯471中,但結合該二導電塊51之該發光二極體晶片5之整體高度需高出該反射杯471深度。Referring to FIG. 13(f), a light-emitting diode wafer 5 is fixed in the reflective cup 471, and two conductive blocks 51 are disposed on the two electrodes of the light-emitting diode wafer 5 (not labeled). A conductive block 51 is disposed on each electrode of the polar body wafer 5 so that the conductive blocks 51 protrude outside the reflective cup 471. In this embodiment, each of the conductive blocks 51 is a gold ball having a height of about 50 to 100 μm. In this embodiment, the light-emitting diode wafer 5 is first fixed and then the conductive block 51 is disposed. However, after the conductive block 51 is first disposed, the light-emitting diode wafer 5 is fixed in the reflective cup 471, but the two are combined. The overall height of the light-emitting diode chip 5 of the conductive block 51 needs to be higher than the depth of the reflective cup 471.

如圖13(g)所示,於反射杯471中填充透光膠材49以密封發光二極體晶片5。透光膠材49可視需求含有螢光粉或不含螢光粉。As shown in FIG. 13(g), the reflective cup 471 is filled with a light-transmitting adhesive 49 to seal the light-emitting diode wafer 5. The light-transmitting adhesive 49 may contain fluorescent powder or no fluorescent powder as needed.

如圖13(h)所示,待透光膠材49固化後研磨其表面,並使該等導電塊51部分裸露於透光膠材49表面。也就是說,該等導電塊51之裸露表面的位置高於反射杯471開口的位置。配合參閱圖14,再以金屬化製程形成分別連接各導電塊51並延伸至上傾斜面451的二上導電層483”,使各上導電層483”分別與各電極電連接,且各上導電層483”分別與相對應的下導電層481連接。之後步驟與實施例3相同,經由切割可行成多數個獨立的封裝結構4’。As shown in FIG. 13(h), after the light-transmitting adhesive 49 is cured, the surface thereof is ground, and the conductive blocks 51 are partially exposed on the surface of the light-transmitting adhesive 49. That is, the position of the exposed surface of the conductive blocks 51 is higher than the position of the opening of the reflective cup 471. Referring to FIG. 14, a second conductive layer 483" respectively connecting the conductive blocks 51 and extending to the upper inclined surface 451 is formed by a metallization process, so that the upper conductive layers 483" are electrically connected to the respective electrodes, and the upper conductive layers are respectively connected. 483" is respectively connected to the corresponding lower conductive layer 481. The subsequent steps are the same as in Embodiment 3, and it is possible to form a plurality of independent package structures 4' via cutting.

前述圖13(f)~圖13(h)所示的步驟亦可適用一般的反射杯。如圖15所示,當反射杯61設在一般封裝載板6時,前述二上導電層483”即為延伸出反射杯61開口外的封裝載板6表面之延伸導電層62,延伸導電層62可供與外部電極(圖未示出)電連接。The steps shown in Figures 13(f) to 13(h) above can also be applied to a general reflector cup. As shown in FIG. 15, when the reflective cup 61 is disposed on the general package carrier 6, the two upper conductive layers 483" are extended conductive layers 62 extending from the surface of the package carrier 6 outside the opening of the reflective cup 61, and the conductive layer is extended. 62 is electrically connectable to an external electrode (not shown).

歸納上述,本發明所提供的發光二極體晶片1、1’的製法,其係藉由形成傾斜側壁13及基板傾斜壁14,以在其斜面上利用金屬化製程沉積導電層1512、1512’,相較於在垂直面上沉積導電層容易控制,故能提昇製程良率,降低製造成本。In summary, the method for fabricating the LED chips 1 and 1 ′ according to the present invention is to form the inclined sidewalls 13 and the substrate inclined walls 14 to deposit the conductive layers 1512 and 1512 on the slopes thereof by a metallization process. Compared with the deposition of the conductive layer on the vertical surface, it is easy to control, so the process yield can be improved and the manufacturing cost can be reduced.

此外,本發明所提供的發光二極體晶片1、1’,藉由斜面單元16、16’使連接電極1511、1521、1511’、1521’之導電層1512、1522、1512’、1522’延伸至基板傾斜壁14,拉近導電層1512、1522、1512’、1522’與提供外部電性連接之延伸導電層35、35’間距離,減少斷線的可能。In addition, the LEDs 1, 1' provided by the present invention extend the conductive layers 1512, 1522, 1512', 1522' of the connection electrodes 1511, 1521, 1511', 1521' by the bevel units 16, 16'. To the substrate inclined wall 14, the distance between the conductive layers 1512, 1522, 1512', 1522' and the extended conductive layers 35, 35' which provide external electrical connection is reduced, thereby reducing the possibility of disconnection.

更進一步的說,本發明之發光二極體晶片1,藉由斜面單元16使連接電極1511、1521之導電層1512、1522延伸至基板傾斜壁14,而發光二極體晶片1’之導電層1513’、1523’延伸至基板11’底面111’,再利用金屬化製程製作延伸導電層35、35’與發光二極體晶片1、1’形成電連接,則不需要打線製程,適用於晶圓級封裝或系統封裝,而能節省一一打線的封裝時間,以及節省打線所佔用的空間以縮小體積,對於整合其他光電元件具有小型化優勢,且與其他LED技術整合,例如奈米晶體製程的整合,也較為彈性。Furthermore, in the light-emitting diode wafer 1 of the present invention, the conductive layers 1512, 1522 of the connection electrodes 1511, 1521 are extended to the substrate inclined wall 14 by the bevel unit 16, and the conductive layer of the LED wafer 1' is illuminated. 1513', 1523' extends to the bottom surface 111' of the substrate 11', and then the metallization process is used to form the extended conductive layer 35, 35' to form an electrical connection with the LED wafer 1, 1 ', which does not require a wire bonding process, and is suitable for crystal Round-scale package or system package, which can save the packaging time of one-and-one wire and save the space occupied by wire-bonding to reduce the size. It has the advantages of miniaturization for integrating other photoelectric components and integration with other LED technologies, such as nano crystal process. The integration is also more flexible.

由實施例1~實施例5所述的實施步驟可知,本發明提供之發光二極體的封裝方法不需要打線製程,能適用於晶圓級封裝或系統封裝,依據不同的發光二極體晶片1、1’、5結構可選擇適用的方法步驟。進一步地,如實施例3~實施例5所述,還能形成可直接設置於一應用產品的電路板之封裝結構4、4’,不需使用打線製程,不僅能夠節省封裝製程時間及縮小封裝結構4、4’的體積,還能方便下游應用端的組裝程序。It can be seen from the implementation steps described in the first embodiment to the fifth embodiment that the method for packaging the LEDs of the present invention does not require a wire bonding process and can be applied to a wafer level package or a system package according to different light emitting diode chips. 1, 1 ', 5 structure can choose the applicable method steps. Further, as described in Embodiments 3 to 5, the package structure 4, 4' which can be directly disposed on the circuit board of an application product can be formed, and the package process time and the package can be reduced without using the wire bonding process. The volume of the structure 4, 4' can also facilitate the assembly process of the downstream application end.

此外,如圖7(a)-7(d)、10(a)、11(a)-11(e)、12(a)與13(a)-13(e)所示之封裝方法、封裝載板架構與反射杯架構,並不限定僅適用於本發明所揭露之發光二極體晶片1、1’,亦可應用於一般發光二極體晶片。In addition, as shown in FIGS. 7(a)-7(d), 10(a), 11(a)-11(e), 12(a) and 13(a)-13(e), the packaging method and package are shown. The carrier structure and the reflector cup structure are not limited to the light-emitting diode chips 1 and 1' which are only applicable to the present invention, and can also be applied to a general light-emitting diode wafer.

惟以上所述者,僅為本發明之較佳實施例而已,當不能以此限定本發明實施之範圍,即大凡依本發明申請專利範圍及發明說明內容所作之簡單的等效變化與修飾,皆仍屬本發明專利涵蓋之範圍內。The above is only the preferred embodiment of the present invention, and the scope of the invention is not limited thereto, that is, the simple equivalent changes and modifications made by the scope of the invention and the description of the invention are All remain within the scope of the invention patent.

1...發光二極體晶片1. . . Light-emitting diode chip

1’...發光二極體晶片1'. . . Light-emitting diode chip

10...母片10. . . Master piece

10’...母片10’. . . Master piece

11...基板11. . . Substrate

11’...基板11’. . . Substrate

111...底面111. . . Bottom

111’...底面111’. . . Bottom

112...表面112. . . surface

12...磊晶層單元12. . . Epitaxial layer unit

121...第一型半導體層121. . . First type semiconductor layer

122...發光層122. . . Luminous layer

123...第二型半導體層123. . . Second type semiconductor layer

13...傾斜側壁13. . . Sloping side wall

131...第一斜面131. . . First slope

132...第二斜面132. . . Second slope

133...平台133. . . platform

14...基板傾斜壁14. . . Sloping wall of substrate

14’...基板傾斜壁14’. . . Sloping wall of substrate

151...第一電極單元151. . . First electrode unit

151’...第一電極單元151’. . . First electrode unit

1511...電極1511. . . electrode

1512...導電層1512. . . Conductive layer

1512’...導電層1512’. . . Conductive layer

1513’...導電層1513’. . . Conductive layer

152...第二電極單元152. . . Second electrode unit

152’...第二電極單元152’. . . Second electrode unit

1521...電極1521. . . electrode

1522...導電層1522. . . Conductive layer

1522’...導電層1522’. . . Conductive layer

1523’...導電層1523’. . . Conductive layer

153...絕緣層153. . . Insulation

16...斜面單元16. . . Bevel unit

21...凹槽twenty one. . . Groove

22...第二凹槽twenty two. . . Second groove

23...基板凹槽twenty three. . . Substrate recess

3...封裝載板3. . . Package carrier

3’...封裝載板3’. . . Package carrier

31...保護層31. . . The protective layer

311...穿孔311. . . perforation

32...凹槽32. . . Groove

321...開口321. . . Opening

33...金屬層33. . . Metal layer

34...金屬層(反射杯)34. . . Metal layer (reflective cup)

34’...反射杯34’. . . Reflective cup

35...延伸導電層35. . . Extended conductive layer

35’...延伸導電層35’. . . Extended conductive layer

36...絕緣層36. . . Insulation

37...透光膠材37. . . Light-transmissive glue

37’...透光膠材37’. . . Light-transmissive glue

38...固晶膠38. . . Solid crystal glue

4...封裝結構4. . . Package structure

4’...封裝結構4’. . . Package structure

41...封裝載板41. . . Package carrier

411...正面411. . . positive

412...背面412. . . back

42...保護層42. . . The protective layer

421...凹槽位置421. . . Groove position

422...穿槽位置422. . . Grooving position

43...凹槽43. . . Groove

44...穿槽44. . . Grooving

45...側壁45. . . Side wall

451...上傾斜面451. . . Inclined surface

452...下傾斜面452. . . Lower slope

46...絕緣層46. . . Insulation

47...金屬層47. . . Metal layer

471...反射杯471. . . Reflective cup

48...導電層48. . . Conductive layer

481...下導電層481. . . Lower conductive layer

482...傳導區482. . . Conduction zone

483...上導電層483. . . Upper conductive layer

483’...上導電層483’. . . Upper conductive layer

483”...上導電層483"... upper conductive layer

49...透光膠材49. . . Light-transmissive glue

5...發光二極體晶片5. . . Light-emitting diode chip

51...導電塊51. . . Conductive block

6...封裝載板6. . . Package carrier

61...反射杯61. . . Reflective cup

62...延伸導電層62. . . Extended conductive layer

91...發光二極體晶片91. . . Light-emitting diode chip

92...載板92. . . Carrier board

93...外部電極93. . . External electrode

94...晶片94. . . Wafer

941...開孔941. . . Opening

95...導電層95. . . Conductive layer

96...電極96. . . electrode

97...電極97. . . electrode

圖1是一示意圖,說明一習知的發光二極體晶片;Figure 1 is a schematic view showing a conventional light-emitting diode wafer;

圖2是一俯視圖,說明日本專利公開案JP2008-130875所揭示的一發光二極體晶片;Figure 2 is a plan view showing a light-emitting diode wafer disclosed in Japanese Patent Laid-Open Publication No. 2008-130875;

圖3是一圖2的截面圖;Figure 3 is a cross-sectional view of Figure 2;

圖4(a)~圖4(f)是說明本發明發光二極體晶片的製法之實施例1的實施步驟流程圖;4(a) to 4(f) are flow charts showing the steps of the first embodiment of the method for fabricating the light-emitting diode wafer of the present invention;

圖5是一圖4(f)的俯視圖,說明實施例1的二電極單元的位置;Figure 5 is a plan view of Figure 4 (f) illustrating the position of the two-electrode unit of Embodiment 1;

圖6是一示意圖,說明本發明發光二極體晶片之實施例1;Figure 6 is a schematic view showing Embodiment 1 of the light-emitting diode chip of the present invention;

圖7(a)~圖7(g)是說明本發明發光二極體封裝方法之實施例1的實施步驟流程圖;7(a) to 7(g) are flow charts illustrating the steps of the embodiment 1 of the method for packaging a light-emitting diode according to the present invention;

圖8是接續圖4(a)~圖4(f)的流程圖,說明本發明發光二極體晶片的製法之實施例2的實施步驟;Figure 8 is a flow chart subsequent to Figure 4 (a) to Figure 4 (f), illustrating the implementation steps of the second embodiment of the method for fabricating the light-emitting diode wafer of the present invention;

圖9是一示意圖,說明本發明發光二極體晶片之實施例2;Figure 9 is a schematic view showing Embodiment 2 of the light-emitting diode chip of the present invention;

圖10(a)~圖10(c)是接續圖7(a)~圖7(d)的流程圖,說明本發明發光二極體封裝方法之實施例2的實施步驟;10(a) to 10(c) are flowcharts subsequent to FIGS. 7(a) to 7(d), illustrating the implementation steps of the embodiment 2 of the light emitting diode package method of the present invention;

圖11(a)~圖11(f)是說明本發明發光二極體封裝方法之實施例3的實施步驟流程圖;11(a) to 11(f) are flow charts showing the implementation steps of Embodiment 3 of the LED package method of the present invention;

圖12(a)~圖12(b)是接續圖11(a)~圖11(d)的流程圖,說明本發明發光二極體封裝方法之實施例4的實施步驟;12(a) to 12(b) are flowcharts of FIG. 11(a) to FIG. 11(d), illustrating the implementation steps of Embodiment 4 of the LED package method of the present invention;

圖13(a)~圖13(h)是說明本發明發光二極體封裝方法之實施例5的實施步驟流程圖;13(a) to 13(h) are flow charts showing the implementation steps of Embodiment 5 of the LED package method of the present invention;

圖14是一圖13(h)的俯視圖,說明實施例5的上導電層的位置;及Figure 14 is a plan view of Figure 13 (h) illustrating the position of the upper conductive layer of Embodiment 5;

圖15是一示意圖,說明實施例5之發光二極體晶片的另一封裝態樣。Figure 15 is a schematic view showing another package aspect of the light-emitting diode wafer of Embodiment 5.

1...發光二極體晶片1. . . Light-emitting diode chip

11...基板11. . . Substrate

111...底面111. . . Bottom

112...表面112. . . surface

12...磊晶層單元12. . . Epitaxial layer unit

121...第一型半導體層121. . . First type semiconductor layer

122...發光層122. . . Luminous layer

123...第二型半導體層123. . . Second type semiconductor layer

13...傾斜側壁13. . . Sloping side wall

131...第一斜面131. . . First slope

132...第二斜面132. . . Second slope

133...平台133. . . platform

14...基板傾斜壁14. . . Sloping wall of substrate

151...第一電極單元151. . . First electrode unit

1511...電極1511. . . electrode

1512...導電層1512. . . Conductive layer

152...第二電極單元152. . . Second electrode unit

1521...電極1521. . . electrode

1522...導電層1522. . . Conductive layer

153...絕緣層153. . . Insulation

16...斜面單元16. . . Bevel unit

Claims (13)

一種發光二極體晶片,包含:一基板,具有一表面及一底面;一磊晶層單元,位於該基板的表面;二斜面單元,各該斜面單元係由該磊晶層單元朝該基板的底面方向往下並往外傾斜,各包括位於該磊晶層單元之一傾斜側壁,及位於該基板之一基板傾斜壁;及二電極單元,各該電極單元包括一設於該磊晶層單元之電極,及一由該電極沿相對應的該斜面單元延伸至該基板傾斜壁的導電層。A light-emitting diode wafer comprising: a substrate having a surface and a bottom surface; an epitaxial layer unit located on a surface of the substrate; and two inclined surface units each facing the substrate by the epitaxial layer unit The bottom surface is downwardly and outwardly inclined, and includes an inclined sidewall on one of the epitaxial layer units and an inclined wall of the substrate on the substrate; and two electrode units, each of the electrode units including a layer disposed on the epitaxial layer unit An electrode, and a conductive layer extending from the corresponding bevel unit to the inclined wall of the substrate. 依據申請專利範圍第1項所述之發光二極體晶片,其中,各該導電層還延伸至該基板的底面。The light-emitting diode wafer according to claim 1, wherein each of the conductive layers further extends to a bottom surface of the substrate. 依據申請專利範圍第1或2項所述之發光二極體晶片,其中,該二電極單元其中之一之導電層與對應的該傾斜側壁之間還設有一絕緣層。The illuminating diode chip according to claim 1 or 2, wherein an insulating layer is further disposed between the conductive layer of one of the two electrode units and the corresponding inclined sidewall. 依據申請專利範圍第1或2項所述之發光二極體晶片,其中,該磊晶層單元包括一第一型半導體層、一發光層及一第二型半導體層,該第一型半導體層位於該基板表面,且該發光層位於該第一型半導體層與該第二型半導體層之間;該二電極單元分別為一與該第一型半導體層電性連接之第一電極單元,以及一與該第二型半導體層電性連接之第二電極單元,而且該第二電極單元之導電層與對應的該傾斜側壁之間還設有一絕緣層。The illuminating diode chip according to claim 1 or 2, wherein the epitaxial layer unit comprises a first type semiconductor layer, a light emitting layer and a second type semiconductor layer, the first type semiconductor layer Located on the surface of the substrate, and the light emitting layer is located between the first type semiconductor layer and the second type semiconductor layer; the two electrode units are respectively a first electrode unit electrically connected to the first type semiconductor layer, and And a second electrode unit electrically connected to the second type semiconductor layer, and an insulating layer is further disposed between the conductive layer of the second electrode unit and the corresponding inclined sidewall. 依據申請專利範圍第4項所述之發光二極體晶片,其中,各該傾斜側壁還包括一由該第二型半導體層側往下延伸至部分該第一型半導體層側的第一斜面及一相鄰該基板的第二斜面,而該第一斜面與該第二斜面之間由一平台相連接。 The illuminating diode chip according to claim 4, wherein each of the slanting sidewalls further includes a first slope extending from the second semiconductor layer side to a portion of the first semiconductor layer side and a second inclined surface adjacent to the substrate, and the first inclined surface and the second inclined surface are connected by a platform. 依據申請專利範圍第1或2項所述之發光二極體晶片,其中,各該基板傾斜壁的傾斜角介於40-60度。 The light-emitting diode wafer according to claim 1 or 2, wherein each of the inclined walls of the substrate has an inclination angle of 40 to 60 degrees. 依據申請專利範圍第1或2項所述之發光二極體晶片,其中,該基板傾斜壁與其相鄰的傾斜側壁為同向傾斜。 The light-emitting diode wafer according to claim 1 or 2, wherein the inclined wall of the substrate is inclined in the same direction as the adjacent inclined side wall. 依據申請專利範圍第1或2項所述之發光二極體晶片,其中,該二斜面單元分別位於兩相對側邊。 The illuminating diode chip according to claim 1 or 2, wherein the two slanting units are respectively located on opposite sides. 一種發光二極體晶片的製法,步驟包含:提供一基板;形成一磊晶層於該基板之表面上;蝕刻該磊晶層,於該磊晶層的兩側邊形成往下並往外傾斜的傾斜側壁,並使該基板的部分表面裸露;蝕刻該裸露基板表面,形成一基板凹槽,各該基板凹槽具有一基板傾斜壁;形成二電極單元,其中各該電極單元包括一設於該磊晶層單元之電極,及一由該電極沿各該傾斜側壁延伸至相鄰的該基板傾斜壁的第一導電層;及研磨該基板之底面,使該第一導電層露出該底面。 A method for manufacturing a light-emitting diode wafer, the method comprising: providing a substrate; forming an epitaxial layer on a surface of the substrate; etching the epitaxial layer, forming a downward direction on both sides of the epitaxial layer and tilting outward Slanting the sidewalls and exposing a portion of the surface of the substrate; etching the surface of the exposed substrate to form a substrate recess, each of the substrate recesses having a substrate inclined wall; forming a two-electrode unit, wherein each of the electrode units includes a An electrode of the epitaxial layer unit, and a first conductive layer extending from the inclined sidewall to the adjacent inclined wall of the substrate; and grinding the bottom surface of the substrate to expose the first conductive layer to the bottom surface. 依據申請專利範圍第9項所述之發光二極體晶片的製法,還包含一步驟:形成一第二導電層於研磨後的該基板之底面,用以連接該第一導電層。 The method for fabricating a light-emitting diode according to claim 9 further comprises the step of forming a second conductive layer on the bottom surface of the polished substrate for connecting the first conductive layer. 依據申請專利範圍第9或10項所述之發光二極體晶片的製法,其中需使得該基板傾斜壁與其相鄰的該傾斜側壁為同向傾斜。 A method of fabricating a light-emitting diode wafer according to claim 9 or claim 10, wherein the inclined wall of the substrate is inclined in the same direction as the adjacent inclined side wall. 依據申請專利範圍第9或10項所述之發光二極體晶片的製法,其中,該磊晶層單元依序包括一第一型半導體層、一發光層及一第二型半導體層;在該磊晶層蝕刻步驟中更包括以下步驟:蝕刻該第二型半導體層、該發光層與該第一型半導體層,使該第一型半導體層部分裸露,以形成各該傾斜側壁中由該第二型半導體層側往下延伸至部分該第一型半導體層側的一第一斜面;及蝕刻該第一型半導體層的部分裸露表面至該基板,使該基板的部分表面裸露,以形成各該傾斜側壁中相鄰該基板的一第二斜面及一連接於該第一斜面與該第二斜面的平台。 The method for fabricating a light-emitting diode according to claim 9 or 10, wherein the epitaxial layer unit comprises a first type semiconductor layer, a light emitting layer and a second type semiconductor layer in sequence; The epitaxial layer etching step further includes the steps of: etching the second type semiconductor layer, the light emitting layer and the first type semiconductor layer, and partially exposing the first type semiconductor layer to form each of the inclined sidewalls by the first Extending the second semiconductor layer side downward to a portion of the first bevel of the first type semiconductor layer; and etching a portion of the exposed surface of the first type semiconductor layer to the substrate to expose a portion of the surface of the substrate to form each a second inclined surface adjacent to the substrate and a platform connected to the first inclined surface and the second inclined surface. 依據申請專利範圍第9或10項所述之發光二極體晶片的製法,其中形成該對電極單元的步驟前,更包含一步驟:形成一絕緣層於該第一導電層與對應的該傾斜側壁之間。 The method for fabricating a light-emitting diode according to claim 9 or 10, wherein before the step of forming the pair of electrode units, the method further comprises the step of: forming an insulating layer on the first conductive layer and corresponding the tilt Between the side walls.
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