CN204216092U - A kind of flip LED chips - Google Patents
A kind of flip LED chips Download PDFInfo
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- CN204216092U CN204216092U CN201420740155.4U CN201420740155U CN204216092U CN 204216092 U CN204216092 U CN 204216092U CN 201420740155 U CN201420740155 U CN 201420740155U CN 204216092 U CN204216092 U CN 204216092U
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Abstract
The utility model provides a kind of flip LED chips, adopt the DBR reflector being formed with the first through hole and the second through hole, the first pad on first substrate is by the first metal function layer, contact layer on first through hole and p type semiconductor layer is electrically connected with p type semiconductor layer, the second pad on second substrate is by the second metal function layer, contact layer in second through hole and groove is electrically connected with n type semiconductor layer, specular layer is done without the need to adopting precious metals silver, and DBR is more stable compared with silver, DBR reflector is adopted to replace silver to eliminate passivation layer, barrier layer, the processing step that protective layer etc. are loaded down with trivial details, the production cost of LED is reduced while the technical barrier solving chip manufacturing end.
Description
Technical field
The utility model belongs to semiconductor optoelectronic chip manufacturing field, particularly relates to a kind of flip LED chips.
Background technology
Since early 1990s commercialization, through the development of twenties years, GaN base LED has been widely used in the fields such as indoor outer display screen, Projection Display lighting source, backlight, view brightening illumination, advertisement, traffic instruction, and is described as 21st century the most competitive solid light source of new generation.But for light emitting semiconductor device LED, replace conventional light source, enter high-end lighting field, three problems must be solved simultaneously: one is to solve luminosity Upgrade Problem, two is to solve heat dissipation problem, and three is the reduction problems that will solve production cost.
In recent years, in the excitation of the various policy of government with under promoting, the various technology for improving LED luminosity is arisen at the historic moment, such as patterned substrate technology, high-voltage chip, vertical stratification, DBR technology etc.
Wherein patterned substrate technology most effect, between 2010 to 2012, the dry method patterned substrate of cone structure that front and back occur and the wet method pattern substrate of Pyramid instead of the main flow substrate that the smooth Sapphire Substrate in surface becomes LED chip completely, make the crystal structure of LED and luminosity be obtained for revolutionary raising.But the main flow substrate that patterned substrate replaces the smooth Sapphire Substrate in surface to become LED chip adds the production cost of LED undoubtedly, although the cost increased can slowly reduce along with the raising of patterned substrate manufacturing technology level, cannot eliminate completely.
Along with the high speed development of semiconductor integration technology, a kind ofly be called that the LED structure of high-voltage chip is arisen at the historic moment, the LED of this kind of structure is generally after epitaxial loayer is formed, isolation channel is formed by lithographic etch process, fill insulant in isolation channel again, finally makes electrode and forms cascaded structure on the epitaxial loayer of each insulated separation; Although this structure can improve the luminosity of LED, but the technical process of formation isolation channel, fill insulant considerably increases the manufacturing cost of chip, moreover, also reduce the reliability of LED chip to a certain extent, the deep etching such as caused because existing etching homogeneity does not reach requirement is unclean, finally can cause electric leakage, reduce the breakdown characteristics etc. of LED chip.
It is the heat dissipation problem that patterned substrate technology or high-voltage chip all do not solve LED chip well, formal dress flip-chip is connected on the good substrate of an electrical and thermal conductivity performance by vertical stratification and flip chip technology (fct), make to generate heat relatively more concentrated light emitting epitaxial layer closer to the hot dirt of heat radiation, most of heat is derived by substrate, instead of derive from the sapphire growth substrate that heat radiation is bad, this alleviates the heat dissipation problem of LED chip to a certain extent.But vertical stratification and face-down bonding technique again increase the production cost of LED chip undoubtedly, the expense etc. of such as upside-down mounting expense, precious metal specular layer.
The LED chip of vertical stratification does not need etching N district material, this reduces the part producing cost of LED to a certain extent, and different from the current flowing mode of the LED chip of other structure, it is more suitable for the injection of big current, improves the luminosity of LED chip further.But the same with high-voltage chip, the LED of vertical stratification also needs to form isolation channel, and this again improves the production cost of LED, moreover, the chip of vertical stratification also needs to peel off growth substrates, so this improves the production cost of LED chip again.Compared with the LED of vertical stratification, the LED chip of inverted structure may more be preponderated in production cost.
In order to make LED play the part of prior role at lighting field as early as possible, a kind of LED structure of above-mentioned three problems and preparation method thereof that can solve urgently is researched and developed.
Utility model content
For solving the problem, the utility model provides a kind of flip LED chips.
The utility model provides a kind of flip LED chips, comprising:
Substrate, described substrate comprises first area, second area and the 3rd region between described first area and second area;
Be formed at the epitaxial loayer on all regions of described substrate, described epitaxial loayer comprises the n type semiconductor layer, active layer and the p type semiconductor layer that are formed at successively on described substrate;
Be formed at groove and the recess channels of the some array arrangements in described epitaxial loayer, described groove and recess channels expose described n type semiconductor layer, are communicated with in the groove of described some array arrangements with the groove in a line by recess channels;
Be formed at the barrier layer in the presumptive area of described p type semiconductor layer;
Be formed at the protective layer on described groove and recess channels sidewall;
Be formed at the contact layer in described barrier layer and groove and recess channels, described contact layer exposes protective layer;
Be formed at the DBR reflector on described contact layer and protective layer, the first through hole is formed in DBR reflector on described first area, described first through hole exposes the contact layer on described barrier layer, be formed with the second through hole in DBR reflector on described second area, described second through hole exposes the contact layer in groove;
Be formed on DBR reflector and metal function layer in the first through hole and the second through hole, described metal function layer comprises the first metal function layer be positioned on described first area and the second metal function layer be positioned on described second area, the gap that described first metal function layer is corresponding with having the one and the 3rd region between the second metal function layer; And
With the flip-chip substrate of described substrate face-down bonding, described flip-chip substrate comprises first substrate, second substrate, is arranged between first substrate and second substrate in order to the insulation described first substrate of isolation and the insulation isolation fixed head of second substrate, the second pad of being arranged at the first pad on first substrate and being arranged on second substrate, described first metal function layer corresponds to described first substrate, described second metal function layer corresponds to described second substrate, and described edge isolation fixed head inserts the gap between described first metal function layer and the second metal function layer.
Optionally, in described flip LED chips, described protective layer also extends to the edge of described p type semiconductor layer.
Optionally; in described flip LED chips; the material of described barrier layer and protective layer is silicon dioxide; the material of described contact layer is ITO; described DBR reflector is at least two kinds in SiO, SiO2, TiO2, Ti3O5 oxide material; being formed according to λ/4n thickness alternating growth, growth cycle is 3-20.Described first metal function layer and the second metal function layer include the metal contact layer of stacked setting, metal barrier layer and metal electrode layer, the material of described metal contact layer is chromium or nickel, the material of described metal barrier layer is titanium or nickel, and the material of described metal electrode layer is aluminium.
A kind of flip LED chips of the utility model has following beneficial effect:
1, flip LED chips manufacture method provided by the utility model adopts DBR reflector, the first through hole is formed in DBR reflector on the first area of substrate, the second through hole is formed in DBR reflector on the second area of substrate, the first pad on first substrate is by the first metal function layer, contact layer on first through hole and p type semiconductor layer is electrically connected with p type semiconductor layer, the second pad on second substrate is by the second metal function layer, contact layer in second through hole and groove is electrically connected with n type semiconductor layer, finally, first pad is formed with all p type semiconductor layers and is electrically connected, second pad is formed with all n type semiconductor layers and is electrically connected, avoid the use that precious metals silver does specular layer, compared with silver, DBR is more stable, so adopt the DBR reflector being formed with the first through hole and the second through hole to replace silver to eliminate passivation layer, barrier layer, the processing step that protective layer etc. are loaded down with trivial details, the production cost of LED is reduced while the technical barrier solving chip manufacturing end,
2, flip LED chips manufacture method provided by the utility model is provided with low-cost metal function layer on DBR reflector, reduces the production cost of LED while solving luminance raising problem and heat dissipation problem;
3, the utility model forms flip-chip LED structure, to compare the making without the need to being carried out isolation channel by lithographic etch process, more need not use filling insulating material isolation channel again with traditional high-voltage chip with vertical stratification.
Accompanying drawing explanation
With reference to accompanying drawing, clearly the utility model can be understood according to detailed description below.For the sake of clarity, in figure, the relative thickness of each layer and the relative size of given zone are not drawn in proportion.In the accompanying drawings:
Fig. 1 is the cross-sectional view of substrate in the utility model one embodiment;
Fig. 2 is the cross-sectional view after forming epitaxial loayer in the utility model one embodiment;
Fig. 3 A is the cross-sectional view after forming groove in the utility model one embodiment;
Fig. 3 B is the vertical view of Fig. 3 A;
Fig. 4 A is the cross-sectional view after forming barrier layer and protective layer in the utility model one embodiment;
Fig. 4 B is the vertical view of Fig. 4 A;
Fig. 5 A is the cross-sectional view after forming contact layer in the utility model one embodiment;
Fig. 5 B is the vertical view of Fig. 5 A;
Fig. 6 is the cross-sectional view after forming DBR reflector in the utility model one embodiment;
Fig. 7 A is the cross-sectional view after forming through hole in the utility model one embodiment in DBR reflector;
Fig. 7 B is the vertical view of Fig. 7 A;
Fig. 7 C is the distribution schematic diagram of through hole in the utility model one embodiment;
Fig. 8 is the cross-sectional view after forming metal function layer in the utility model one embodiment
Fig. 9 is the cross-sectional view of flip-chip substrate in the utility model one embodiment;
Figure 10 is the cross-sectional view in the utility model one embodiment after face-down bonding;
Figure 11 is the schematic flow sheet of flip LED chips manufacture method in the utility model one embodiment.
Embodiment
Various exemplary embodiment of the present utility model is described in detail now with reference to accompanying drawing.
As shown in figure 11, flip LED chips manufacture method of the present utility model, comprises the steps:
S1 a: substrate is provided, described substrate comprises first area, second area and the 3rd region between first area and second area;
S2: form epitaxial loayer on all regions of described substrate, described epitaxial loayer comprises the n type semiconductor layer, active layer and the p type semiconductor layer that are formed at successively on described substrate;
S3: the groove and the recess channels that form some array arrangements on said epitaxial layer there, described groove and recess channels expose n type semiconductor layer, are communicated with in the groove of described some array arrangements with the groove in a line by recess channels;
S4: form barrier layer in the presumptive area of described p type semiconductor layer, and synchronously on the sidewall of each groove and recess channels, form protective layer;
S5: form contact layer on described barrier layer and in groove and recess channels, described contact layer exposes described protective layer;
S6: form DBR reflector on described contact layer and protective layer, the first through hole is formed in DBR reflector on described first area, described first through hole exposes the contact layer on described barrier layer, be formed with the second through hole in DBR reflector on described second area, described second through hole exposes the contact layer in described groove;
S7: form metal function layer on described DBR reflector and in the first through hole and the second through hole, described metal function layer comprises the first metal function layer be positioned on described first area and the second metal function layer be positioned on described second area, the gap that described first metal function layer is corresponding with having the one and the 3rd region between the second metal function layer;
S8 a: flip-chip substrate is provided, described flip-chip substrate comprises first substrate, second substrate, is arranged between first substrate and second substrate in order to the insulation described first substrate of isolation and the insulation isolation fixed head of second substrate, the second pad of being arranged at the first pad on first substrate and being arranged on second substrate;
S9: by described substrate face-down bonding on described flip-chip substrate, described first metal function layer corresponds to described first substrate, described second metal function layer corresponds to described second substrate, described edge isolation fixed head inserts in the gap between described first metal function layer and the second metal function layer, forms flip LED chips.
Flip LED chips manufacture method provided by the utility model is illustrated in greater detail below in conjunction with Fig. 1-11.It should be noted that, accompanying drawing all adopts the form that simplifies very much and all uses non-ratio accurately, only in order to object that is convenient, aid illustration the utility model embodiment lucidly.
As shown in Figure 1, perform step S1, provide a substrate 1, described substrate 1 comprises first area 11, second area 12 and the 3rd region 13 between first area 11 and second area 12.Described substrate 1 is preferably Sapphire Substrate, preferred, and described substrate 1 is patterned Sapphire Substrate.
As shown in Figure 2, perform step S2, described substrate 1 forms epitaxial loayer 2, and described epitaxial loayer 2 comprises the n type semiconductor layer 21, active layer 22 and the p type semiconductor layer 23 that are formed at successively on described substrate 1.Certainly, other known retes can also be formed before the described n type semiconductor layer 21 of formation.
As shown in Figure 3 A and Figure 3 B, perform step S3, in the presumptive area one of described epitaxial loayer 2, some grooves 3 and recess channels 3 ' is formed by lithographic etch process, described groove 3 and recess channels 3 ' expose n type semiconductor layer 21, that is, the degree of depth of described groove 3 and recess channels 3 ' is greater than the summation of described p type semiconductor layer 23 and described active layer 22 thickness and is less than the thickness of described epitaxial loayer 2, namely the p type semiconductor layer 23 in groove 3 and recess channels 3 ' and active layer 22 are removed completely, and n type semiconductor layer 21 layers is removed a part.Some groove 3 array distribution in described epitaxial loayer 2, wherein be communicated with by recess channels 3 ' with the some grooves 3 in a line, Fig. 3 B only schematically represents the groove that two row are arranged in parallel, but will be appreciated that, the distribution form of described groove 3 is not limited to upper figure.
As shown in Figure 4 A and 4 B shown in FIG.; perform step S4, in the presumptive area two of epitaxial loayer 2, form barrier layer 4 by deposition, photoetching, etching technics, and synchronously on the sidewall of each groove 3, form protective layer 5; in preferred version, described protective layer 5 also extends to the edge of p type semiconductor layer 23.The material of described barrier layer 4 and protective layer 5 is such as silicon dioxide.
As fig. 5 a and fig. 5b, perform step S5, on described barrier layer 4 and on the p type semiconductor layer 23 exposed, form contact layer 6 by evaporation, sputtering or spraying coating process, the material of described contact layer 6 is ITO.Specifically, described contact layer 6 comprises the first contact layer 61 be arranged on described barrier layer 4 and the second contact layer 62 being positioned at described groove 3 and recess channels 3 ', and described protective layer 5 is exposed.
As shown in Fig. 6 and Fig. 7 A-7C; perform step S6; described contact layer 6 and protective layer 5 form DBR reflector 7; the first through hole 71 is formed in DBR reflector 7 on described first area 11; described first through hole 71 exposes the first contact layer 61 on described barrier layer 4; be formed with the second through hole 72 in DBR reflector 7 on described second area 12, described second through hole 72 exposes the second contact layer 62 in described groove 3.
Concrete, first, on described contact layer 6, form DBR reflector 7 by evaporation, sputtering or spraying coating process.Described DBR reflector 7 is at least two kinds in the oxide materials such as SiO, SiO2, TiO2, Ti3O5, formed according to λ/4n thickness alternating growth, and growth cycle is 3-20, and wherein λ is wavelength, and n is refraction coefficient.Then, by chemical etching technique, selectivity perforate is carried out to described DBR reflector 7, namely in described DBR reflector 7, form the first through hole 71 and the second through hole 72, described first through hole 71 exposes the first contact layer 61 on described barrier layer 4, and described second through hole 72 exposes the second contact layer 62 in described groove 3.Fig. 7 C is the distribution schematic diagram of the first through hole 71 and the second through hole 72 in the utility model one embodiment, is understandable that, in the present embodiment, all cross-section structures are all obtained along AA ' direction in vertical view.
As shown in Figure 8, perform step S7, on described DBR reflector 7, metal function layer 8 is formed by evaporation, sputtering or spraying coating process, described metal function layer comprises the first metal function layer 81 be positioned on described first area 11 and the second metal function layer 82 be positioned on described second area 12, have a gap 83 between described first metal function layer 81 and the second metal function layer 82, the position in described gap 83 is corresponding with the position in described 3rd region 13.Further, described first metal function layer 81 and the second metal function layer 82 include the metal contact layer of stacked setting, metal barrier layer and metal electrode layer, the material of described metal contact layer is chromium or nickel, the material of described metal barrier layer is titanium or nickel, and the material of described metal electrode layer is aluminium.
As shown in Figure 9, perform step S8, one flip-chip substrate 9 is provided, described flip-chip substrate 9 comprises the first substrate 91 of insulated separation and second substrate 92, be arranged at insulation isolation fixed head 93 between first substrate 91 and second substrate 92, be arranged at the first pad 911 of first substrate 91 and be arranged at the second pad 921 of second substrate 92, and described insulation isolates fixed head 93 for by described first substrate 91 and second substrate 92 insulated separation.
As shown in Figure 10, perform step S9, by above-mentioned substrate 1 face-down bonding on described flip-chip substrate 9, described first metal function layer 81 corresponds to described first substrate 91, described second metal function layer 82 corresponds to described second substrate 92, described edge isolation fixed head 93 is inserted in the gap 83 between described first metal function layer 81 and the second metal function layer 82, forms flip LED chips described in the utility model.
Preferably, before above-mentioned substrate 1 face-down bonding is on described flip-chip substrate 9, can also form adhesive layer respectively at the contact-making surface of the two, the material of described adhesive layer is gold.After above-mentioned substrate 1 face-down bonding is on described flip-chip substrate 9, also comprise step thinning for substrate 1.
As shown in figure 11, composition graphs 1 to Figure 10, the utility model also provides a kind of flip LED chips, and utilize method as above to be formed, described flip LED chips comprises:
Substrate 1, described substrate 1 comprises first area 11, second area 12 and the 3rd region 13 between first area 11 and second area 12;
Be formed at the epitaxial loayer 2 on described substrate 1, described epitaxial loayer comprises the n type semiconductor layer 21, active layer 22 and the p type semiconductor layer 23 that are formed at successively on described substrate 1;
Be formed at groove 3 and the recess channels 3 ' of the some array arrangements on described epitaxial loayer 2, described groove 3 and recess channels 3 ' expose n type semiconductor layer 21, are communicated with in the groove of described some array arrangements with the groove 3 in a line by recess channels 3 ';
Be formed at the barrier layer 4 in the presumptive area of described p type semiconductor layer 23;
Be formed at the protective layer 5 on described groove 3 and recess channels 3 ' sidewall;
Be formed on described barrier layer 4 and contact layer 6 in groove 3 and recess channels 3 ', described contact layer 6 exposes protective layer 5;
Be formed at the DBR reflector 7 on described contact layer 6 and protective layer 5, the first through hole 71 is formed in DBR reflector on described first area 11, described first through hole 71 exposes the contact layer 61 on described barrier layer 4, be formed with the second through hole 72 in DBR reflector on described second area 12, described second through hole 72 exposes the contact layer 62 in described groove 3;
Be formed on DBR reflector 7 and metal function layer 8 in the first through hole 71 and the second through hole 72, described metal function layer 8 comprises the first metal function layer 81 be positioned on described first area 11 and the second metal function layer 82 be positioned on described second area 12, the gap 83 that described first metal function layer 81 is corresponding with having the one and the 3rd region 13 between the second metal function layer 82; And
With the flip-chip substrate 9 of described substrate 1 face-down bonding, described flip-chip substrate 9 comprises first substrate 91, second substrate 92, be arranged at the insulation isolation fixed head 93 in order to the insulation described first substrate 91 of isolation and second substrate 92 between first substrate 91 and second substrate 92, the second pad 921 being arranged at the first pad 911 on first substrate 91 and being arranged on second substrate 92, described first metal function layer 81 corresponds to described first substrate 91, described second metal function layer 82 corresponds to described second substrate 92, described edge isolation fixed head 93 inserts the gap 83 between described first metal function layer 81 and the second metal function layer 82.
As from the foregoing, the first through hole 71 position in DBR reflector 7 on first area 11 and barrier layer 4 one_to_one corresponding, thus the first pad 911 on first substrate 91 is by the first metal function layer 81, contact layer 61 on first through hole 71 and p type semiconductor layer 23 is electrically connected with p type semiconductor layer 23, the second through hole 72 position in DBR reflector 7 on second area 12 and groove 3 one_to_one corresponding, thus the second pad 911 on second substrate 92 is by the second metal function layer 82, contact layer 62 in second through hole 72 and groove 3 is electrically connected with n type semiconductor layer 21, finally, first pad 911 is formed with all p type semiconductor layers 23 and is electrically connected, second pad 921 is formed with all n type semiconductor layers 21 and is electrically connected.
Wherein, described substrate 1 is Sapphire Substrate, is preferably patterned Sapphire Substrate; The material of described contact layer 6 is such as ITO.Described DBR reflector 7 is at least two kinds in the oxide materials such as SiO, SiO2, TiO2, Ti3O5, formed according to λ/4n thickness alternating growth, and growth cycle is 3-20.Described first metal function layer 81 and the second metal function layer 82 include the metal contact layer of stacked setting, metal barrier layer and metal electrode layer, the material of described metal contact layer is chromium or nickel, the material of described metal barrier layer is titanium or nickel, and the material of described metal electrode layer is aluminium.Described protective layer 5 also extends to the edge of p type semiconductor layer 23.Between described flip-chip substrate 9 and described metal function layer 8, be also provided with adhesive layer (not shown), the material of described adhesive layer is gold.
In sum, adopt the DBR reflector being formed with the first through hole and the second through hole, the first pad on first substrate is by the first metal function layer, contact layer on first through hole and p type semiconductor layer is electrically connected with p type semiconductor layer, the second pad on second substrate is by the second metal function layer, contact layer in second through hole and groove is electrically connected with n type semiconductor layer, specular layer is done without the need to adopting precious metals silver, and DBR is more stable compared with silver, DBR reflector is adopted to replace silver to eliminate passivation layer, barrier layer, the processing step that protective layer etc. are loaded down with trivial details, the production cost of LED is reduced while the technical barrier solving chip manufacturing end, in addition, flip LED chips manufacture method provided by the utility model is provided with low-cost metal function layer on DBR reflector, reduces the production cost of LED while solving luminance raising problem and heat dissipation problem, in a word, the utility model forms flip-chip LED structure, to compare the making without the need to being carried out isolation channel by lithographic etch process with vertical stratification with traditional high-voltage chip, more need not use filling insulating material isolation channel again, promote luminosity, solve heat dissipation problem while reduce production cost.
Claims (4)
1. a flip LED chips, comprising:
Substrate, described substrate comprises first area, second area and the 3rd region between described first area and second area;
Be formed at the epitaxial loayer on all regions of described substrate, described epitaxial loayer comprises the n type semiconductor layer, active layer and the p type semiconductor layer that are formed at successively on described substrate;
Be formed at groove and the recess channels of the some array arrangements in described epitaxial loayer, described groove and recess channels expose described n type semiconductor layer, are communicated with in the groove of described some array arrangements with the groove in a line by recess channels;
Be formed at the barrier layer in the presumptive area of described p type semiconductor layer;
Be formed at the protective layer on described groove and recess channels sidewall;
Be formed at the contact layer in described barrier layer, groove and recess channels, described contact layer exposes protective layer;
Be formed at the DBR reflector on described contact layer and protective layer, the first through hole is formed in DBR reflector on described first area, described first through hole exposes the contact layer on described barrier layer, be formed with the second through hole in DBR reflector on described second area, described second through hole exposes the contact layer in groove;
Be formed on DBR reflector and metal function layer in the first through hole and the second through hole, described metal function layer comprises the first metal function layer be positioned on described first area and the second metal function layer be positioned on described second area, the gap that described first metal function layer is corresponding with having the one and the 3rd region between the second metal function layer; And
With the flip-chip substrate of described substrate face-down bonding, described flip-chip substrate comprises first substrate, second substrate, is arranged between first substrate and second substrate in order to the insulation described first substrate of isolation and the insulation isolation fixed head of second substrate, the second pad of being arranged at the first pad on first substrate and being arranged on second substrate, described first metal function layer corresponds to described first substrate, described second metal function layer corresponds to described second substrate, and described edge isolation fixed head inserts the gap between described first metal function layer and the second metal function layer.
2. flip LED chips as claimed in claim 1, it is characterized in that, described protective layer also extends to the edge of described p type semiconductor layer.
3. flip LED chips as claimed in claim 1 or 2, it is characterized in that, the material of described barrier layer and protective layer is silicon dioxide, and the material of described contact layer is ITO.
4. flip LED chips as claimed in claim 1 or 2, it is characterized in that, described first metal function layer and the second metal function layer include the metal contact layer of stacked setting, metal barrier layer and metal electrode layer, the material of described metal contact layer is chromium or nickel, the material of described metal barrier layer is titanium or nickel, and the material of described metal electrode layer is aluminium.
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| CN201420740155.4U CN204216092U (en) | 2014-11-28 | 2014-11-28 | A kind of flip LED chips |
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| CN201420740155.4U CN204216092U (en) | 2014-11-28 | 2014-11-28 | A kind of flip LED chips |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104409617A (en) * | 2014-11-28 | 2015-03-11 | 杭州士兰明芯科技有限公司 | Flip LED chip and manufacturing method thereof |
| CN105449084A (en) * | 2015-12-22 | 2016-03-30 | 浙江师范大学 | Inversed high-voltage light emitting diode (LED) chip electrode and chip fabrication method |
| CN109860365A (en) * | 2019-02-11 | 2019-06-07 | 厦门乾照光电股份有限公司 | A kind of flip chip structure and production method of concave electrode formula |
| CN110212062A (en) * | 2019-06-20 | 2019-09-06 | 合肥彩虹蓝光科技有限公司 | A kind of inverted light-emitting diode (LED) and its manufacturing method |
-
2014
- 2014-11-28 CN CN201420740155.4U patent/CN204216092U/en not_active Withdrawn - After Issue
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104409617A (en) * | 2014-11-28 | 2015-03-11 | 杭州士兰明芯科技有限公司 | Flip LED chip and manufacturing method thereof |
| CN104409617B (en) * | 2014-11-28 | 2017-02-22 | 杭州士兰明芯科技有限公司 | Flip LED chip and manufacturing method thereof |
| CN105449084A (en) * | 2015-12-22 | 2016-03-30 | 浙江师范大学 | Inversed high-voltage light emitting diode (LED) chip electrode and chip fabrication method |
| CN105449084B (en) * | 2015-12-22 | 2018-06-29 | 浙江师范大学 | A kind of upside-down mounting high voltage LED chip electrode and manufacturing method of chip |
| CN109860365A (en) * | 2019-02-11 | 2019-06-07 | 厦门乾照光电股份有限公司 | A kind of flip chip structure and production method of concave electrode formula |
| CN110212062A (en) * | 2019-06-20 | 2019-09-06 | 合肥彩虹蓝光科技有限公司 | A kind of inverted light-emitting diode (LED) and its manufacturing method |
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