200950132 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種的發光元件的封裝結構及其製 造方法’特別係有關於一種小尺寸、低熱阻的發光元件 . 的封裝結構及其製造方法。 【先前技術】 發光二極體（light emitted diode，以下簡稱LED)在照 〇 明或顯示應用中扮演重要的角色。LED與傳統光源相比 較具有許多優勢，例如體積小、發光效應佳、操作反應 速度快。早期LED已廣泛地應用於手機、小型裝置如遙 控盗等，到近年因高亮度、高功率；lED出現，應用範圍 擴大至汽車、照明、戶外大型顯示器等產品。由於LED 的党度、功率皆積極提升，並開始用於背光與電子照明 等應用後，LED的封裝散熱問題日趨嚴重。習知的led 打線封裝結構的散熱效率不佳，會讓LED產生的熱無法 排解，進而使LED的工作溫度上升，因而使發光亮度減 弱、封裝材質劣化，進而造成使用壽命衰減。 第1圖為習知的LED封裝結構1〇〇，其中LED晶片 31係經由焊接或利用導熱膏與矽鑲嵌晶片（silic〇n sub-mount chip)30 連接，經由打線（wire b〇nding)方式使 LED晶片31經由金線32電性連接至導線架34。矽鑲嵌 曰曰片30可再在下連接散熱塊（heat_sinking siUg)37。石夕密 封膠36係用以固定LED晶片31，而透鏡35係設置於矽 9002-A33414TWF/X07-053/ianchen 5 200950132 密封膠36上。而塑膠外罩38(plastic case)係與導線架 34、散熱塊37和石夕密封膠36結合，以完成封裝，生產 速度無法提升。當發光元件構成晝素陣列以作為照明或 顯示用途時，習知的LED封裝結構會因為導線架或外罩 (housing)的面積龐大，使每個發光元件的間距無法縮 小，因而晝素的連續性差，晝面目視效果不佳。 在此技術領域中，有需要一種小尺寸、低熱阻的發 光元件的晶圓級封裝結構及其製造方法。 ❹ 【發明内容】 本發明之一實施例提供一種發光元件的封裝結構， 包括：一發光元件晶片；一第一電極層，設置於上述發 光元件晶片的第一表面上；一第二電極層，設置於上述 發光元件晶片的第二表面上；一蓋板，覆蓋上述發光元 件晶片之發光面；一絕緣層，包覆上述發光元件晶片的 側面和背面；一第一導線層，電性連接上述第一電極層， ® 並沿著上述絕緣層延伸至上述發光元件晶片的背面；及 一第二導線層，電性連接上述第二電極層，其中上述第 二導、線層位於上述絕緣層上，並沿著上述絕緣層延伸至 上述發光元件晶片的背面。 本發明之另一實施例提供一種發光元件的封裝結構 的製造方法，包括下列步驟：提供一晶圓，其包括複數 個發光元件晶片；一第一電極層，設置於上述發光元件 晶片的一表面上；一第二電極層，設置於上述發光元件 9002-A33414TWF/X07-053/ianchen 6 200950132 晶片的另一表面上；於上述晶圓之上述發光元 發光面上覆蓋一蓋板；至少移除上述晶圓 a曰片的 以形成一溝槽，並露出上述第一電極層及上述第 層的接觸面；以及噸應性形成至少二條導線層，复電極 述溝槽的側壁延伸至上述晶圓的背面，並分別電^自上 至上述弟一電極層和上述第二電極層的接觸面。 接 【實施方式】 以下以各實施例詳細說明並伴隨著圖式說明之松 例，做為本發明之參考依據。在圖式或說明書描述中乾 相似或相同之部分皆使用相同之圖號。且在圖式中，麻 施例之形狀或是厚度可擴大，並以簡化或是方便標示^ 再者，圖式中各元件之部分將以分別描述說明之，值得 注意的是，圖中未繪示或描述之元件，為所屬技術領域 中具有通常知識者所知的形式，另外，特定之實施例僅 為揭示本發明使用之特定方式，其並非用以限定本發明。 第2a至2c圖為本發明一實施例之發光元件的晶圓 級封裳的製程剖面圖。本發明實施例係利用晶圓級封裝 (wafer level chip scale package，WLCSP)製程，封裝例如 發光二極體（light emitted diode, LED)或雷射二極體（laser diode，LD)等發光元件。其中晶圓級封裝製程主要係指在 晶圓階段完成封裝步驟後’再予以切割成獨立的封裝 體，然而，在一特定實施例中，例如將已分離的發光元 件重新分布在一承載晶圓上，再進行封裝製程，亦可稱 9002-A33414TWF/X07-053/ianchen 7 200950132 之為晶圓級封裝製程。 請參考第2a圖，提供一晶圓200，其具有複數個發 光元件晶片300,每一個發光元件晶片300彼此係以切割 道A!和A2區隔。晶圓200的材質可包括透明半導體或 介電材料。其中透明半導體材料可包括第三族氮化物半 導體（group III nitride semiconductors)(例如 GaN)、第三 族磷化物半導體（group III phosphide semiconductors)(例 如GaP)、第三族石申化物半導體（group III arsenide il w semiconductors)(例如AlGaAs)、三-五族半導體（例如 ZnS、ZnSe、CdSe或CdTe)、碳化石夕、鍺、石夕或其合金。 而介電材料可包括鑽石（dimond)、纪紹石權石（yttrium aluminium garnet, YAG)、金屬氧化物（metal oxide)、金屬 氟化物（metal fluoride)、光學玻璃（optical glass)、硫系玻 璃（chalcogenide glass)。舉例來說，金屬氧化物（metal oxide)可包括氧化紹（aluminum oxide(藍寶石， sapphire))、氧化鶴（tungsten oxide)、氧化碲（tellurium oxide)、氧化鈦(titanium oxide)、氧化鎳（nickel oxide)、 氧化錯（zirconium oxide，方晶錯石，cubic zirconia)、氧化 銦（indium oxide)、氧化錫（tin oxide)、氧化把（barium oxide)、氧化錄（strontium oxide)、氧化妈（calcium oxide)、 氧化鋅（zinc oxide)、氧化鎵（gallium oxide)、氧化錄 (antimony oxide)、氧 4匕在目（molybdenum oxide)、氧 4匕絡 (chromium oxide)、氧化鉛（lead oxide)或氧化祕（bismuth oxide)等。舉例來說，金屬氟化物可包括氟化转（caicium 9002-A33414TWF/X07-053/ianchen 8 200950132 fluoride)或氟化錤（magnesium fluoride)等。舉例來說，光 學玻璃可包括德國首德玻璃（Schott Glass)之型號為 SF57、SF59、SFL56、LaSF、LaSFN9、LaSFN18 或 LaSFN30 的光學玻璃’以及日本小原玻璃（Ohara glass)之型號為 PBH71的光學玻璃。而硫系玻璃可包括鍺-叙^鎵_硫_砸玻 璃（(Ge，Sb，Ga)(S，Se) glass)。在本發明實施例中，晶圓 200的材質可包括氧化鋁（A1203)、砷化鎵（GaAs)、矽（Si) 或碳化石夕（SiC)等。每一個發光元件晶片300可包括一半 ❿ 導體層202、一第一電極層206和一第二電極層204。半 導體層202係形成於晶圓200上。半導體層202可為一 具有p型-η型接面（pn junction)的半導體層，其包括至少 兩個電性連接的p型區域和η型區域。一第一電極層 206,設置於半導體層202上，並電性連接至半導體層202 的一表面。舉例來說，第一電極層206可電性連接至半 導體層202的ρ型區域。一第二電極層204，設置於晶圓 200的背面201上’並藉晶圓200電性連接至半導體層 202的另一表面。舉例來說，第二電極層204可電性連接 至半導體層202的η型區域。在一實施例中，上述第一 電極層206和第二電極層204係分別電性連接至半導體 層202的不同導電類型區域，因此可分別做為發光元件 晶片300的ρ型電極和η型電極。在其他實施例中，也 可於半導體層202中設置一反射層（reflector)(圖未顯示） 以增加其發光效率。另外，也可於發光元件晶片300中 設置光二極體(photo diode)等電子元件（圖未顯示），且電 9002-A33414TWF/X07-053/ianchen 9 200950132 鸚 性連接至半導體層202，以控制半導體層202的發光亮 度。在本發明實施例中，用於發光二極體(LED)或雷射二 極體(LD)之半導體層202,其材質可包括第三族氮化物半 導體（group III nitride semiconductors)、第三族鱗化物半 導體(group III phosphide semiconductors)、第三族神化物 半導體（group III arsenide semiconductors)、三-五族元素 與磷的化合物或其他類似的材料。舉例來說，半導體層 202可包括氮化鎵（GaN)、氮化鋁（A1N)、氮化銦（InN)、 ❹ 氮化硼（BN)、氮化鋁銦（AlInN)、氮化銦鎵（GalnN)、氮化 鋁鎵（AlGaN)、氮化硼鋁（BA1N)、氮化硼銦（BInN)、氮化 硼鎵（BGaN)、氮化硼鋁鎵銦（BAlGalnN)、磷化鋁（A1P)、 磷化鎵（GaP)、磷化銦（InP)、鋁磷化鎵（AlGaP)、磷化銦 鎵（GalnP)、磷化砷鎵（GaAsP)、磷化鋁鎵銦（InGaAlP)、 氣填化（GalnPN)、填珅化銦鎵（GalnAsP)、碎化紹（AlAs)、 砷化鎵（GaAs)、砷化銦（InAs)、砷化鋁鎵（GaAlAs)、砷 化鎵銦（GalnAs)、石申化在呂鎵銦（AlGalnAs)、氮珅化銦鎵 W (GalnAsN)、砷銻化鎵（GaAsSb)等。 然後’於發光元件晶片300上形成一覆有蓋板212 之空穴213，覆蓋發光元件晶片300之發光面（例如為半 導體層202的上表面），例如可先於發光元件晶片300的 周圍及切割道入】和A2上形成一黏著層208a，再於黏著 層上形成一支撐層（dam) 210。接著，黏結發光元件晶片 300與一蓋板212，其中支撐層210介於第一電極層206 與蓋板212之間，以於發光元件晶片300與蓋板212之 9002-A33414TWF/X07-053/ianchen 10 200950132 間形成一空穴213。在本發明實施例中，黏著層2〇8a可 包括例如環氧樹脂（epoxy)、石夕樹脂（silicone)或苯環丁稀 (benzocyclobutene, BCB)等絕緣材料。支撐層210可包括 環氧樹脂（epoxy)、石夕樹脂（silicone)或苯環丁稀 (benzocyclobutene，BCB)等絕緣材料。蓋板212可使半導 體層202產生的光通過而出射至外界，其材質可包括鏡 片級玻璃或石英等透明材質（transparent material)，如此 可以避免習知發光元件中之傳統封裝膠會因長時間使用 ® 而使材質劣化的缺點。 接著，請參考第2b圖，逐步沿切割道A!和A2分離 各發光元件晶片300並予以絕緣。例如可利用微影和蝕 刻製程等選擇性移除步驟，從晶圓200的背面201移除 部分晶圓200,直到露出半導體層202為止，以於切割道 Aj和A2處先形成溝槽（圖未顯示）。接著，順應性地於晶 圓200的背面201和上述溝槽的側面203形成一絕緣層 214。例如可利用化學氣相沉積法（CVD)、物理氣相沉積 ❹ 法(PVD)、藏鐘法、印刷法’噴墨法、浸鐘法、喷塗法（Spray coating)或旋轉塗佈法形成絕緣層214。在本發明實施例 中，絕緣層214的材質可包括環氧樹脂、聚亞醯胺、樹 脂、氧化梦、金屬氧化物或氮化石夕。 然後，露出位於晶片上方之第一電極層206的一側 面207及露出位於晶片下方之第二電極層204的部份下 表面。例如可再利用例如微影和蝕刻製程等選擇性移除 步驟，移除位於上述溝槽底部的部分絕緣層214、部分支 9002-A33414TWF/X〇7-053/ianchen 11 200950132 撐層210、部分黏著層208a以及部分蓋板2i2 割道A〗和A?處形成溝槽220a，並露出第—電 乂於切 的侧面207。如第2b圖所示，溝槽22〇a係從晶^層2〇6 背面201延伸至晶圓200、半導體層2〇2、支的 黏著層208a以及部分蓋板212中。 牙3 2l〇， 直到 之後，可再利用例如微影和蝕刻製程等選壬 步驟，從晶圓200的背面201移除部分絕緣層性移除 ❹200950132 IX. Description of the Invention: [Technical Field] The present invention relates to a package structure of a light-emitting element and a method of manufacturing the same, and particularly relates to a package structure of a small-sized, low-thermal resistance light-emitting element. method. [Prior Art] A light emitting diode (LED) plays an important role in a lighting or display application. Compared with conventional light sources, LEDs have many advantages, such as small size, good luminescence effect, and fast operation response. Early LEDs have been widely used in mobile phones and small devices such as remote control and piracy. In recent years, due to high brightness and high power, lED has appeared, and its application range has expanded to such products as automobiles, lighting, and outdoor large-scale displays. Since the party's party and power are actively improved, and it has been used in applications such as backlighting and electronic lighting, the problem of heat dissipation in LED packaging has become increasingly serious. The poor heat dissipation efficiency of the conventional LED wire-wrapping structure will cause the heat generated by the LED to be unresolved, thereby increasing the operating temperature of the LED, thereby reducing the luminance of the LED and degrading the package material, thereby causing a decay in service life. FIG. 1 is a conventional LED package structure in which an LED chip 31 is connected to a silic 〇n sub-mount chip 30 via soldering or using a thermal paste, via wire b〇nding. The LED chip 31 is electrically connected to the lead frame 34 via the gold wire 32. The cymbal inlay 30 can be connected to the heat sink (heat_sinking siUg) 37. The Shi Xi Mi sealant 36 is used to fix the LED chip 31, and the lens 35 is disposed on the 矽 9002-A33414TWF/X07-053/ianchen 5 200950132 sealant 36. The plastic case 38 is combined with the lead frame 34, the heat sink block 37, and the Shishi sealant 36 to complete the package, and the production speed cannot be improved. When the light-emitting elements constitute a pixel array for illumination or display purposes, the conventional LED package structure may have a large area of the lead frame or the housing, so that the pitch of each light-emitting element cannot be reduced, and thus the continuity of the element is poor. The visual effect of the face is not good. There is a need in the art for a wafer level package structure of a small size, low thermal resistance luminescent element and a method of fabricating the same. An embodiment of the present invention provides a package structure for a light-emitting element, comprising: a light-emitting element wafer; a first electrode layer disposed on the first surface of the light-emitting element wafer; and a second electrode layer, And a cover plate covering the light emitting surface of the light emitting device chip; an insulating layer covering the side surface and the back surface of the light emitting device chip; and a first wire layer electrically connected to the above a first electrode layer, extending along the insulating layer to the back surface of the light emitting device chip; and a second wire layer electrically connected to the second electrode layer, wherein the second conductive layer is on the insulating layer And extending along the insulating layer to the back surface of the light-emitting element wafer. Another embodiment of the present invention provides a method of fabricating a package structure for a light emitting device, comprising the steps of: providing a wafer including a plurality of light emitting device wafers; and a first electrode layer disposed on a surface of the light emitting device wafer a second electrode layer disposed on the other surface of the light-emitting element 9002-A33414TWF/X07-053/ianchen 6 200950132; covering a light-emitting surface of the light-emitting element of the wafer with a cover; at least removing Forming a trench of the wafer to form a trench and exposing a contact surface of the first electrode layer and the first layer; and forming at least two wire layers by a ton, the sidewall of the trench extending to the wafer The back surface is electrically connected to the contact surface of the electrode layer and the second electrode layer. [Embodiment] The following is a detailed description of the embodiments and the accompanying drawings are intended to be a reference for the present invention. The same drawing numbers are used for similar or identical parts in the drawings or the description of the specification. In the drawings, the shape or thickness of the linen can be enlarged and simplified or conveniently marked. Furthermore, the parts of the various elements in the drawings will be described separately. It is worth noting that The components shown or described are those of ordinary skill in the art, and the specific embodiments are merely illustrative of the specific ways in which the invention is used, and are not intended to limit the invention. 2a to 2c are cross-sectional views showing a process of wafer level sealing of a light-emitting element according to an embodiment of the present invention. In the embodiment of the present invention, a light level component such as a light emitting diode (LED) or a laser diode (LD) is packaged by a wafer level chip scale package (WLCSP) process. The wafer level packaging process mainly refers to 'cutting into a separate package after the packaging step is completed in the wafer stage. However, in a specific embodiment, for example, the separated light emitting elements are redistributed on a carrier wafer. In addition, the packaging process can also be called 9002-A33414TWF/X07-053/ianchen 7 200950132 for the wafer level packaging process. Referring to Figure 2a, a wafer 200 is provided having a plurality of light-emitting element wafers 300, each of which is separated from each other by a scribe line A! and A2. The material of the wafer 200 may include a transparent semiconductor or a dielectric material. The transparent semiconductor material may include group III nitride semiconductors (for example, GaN), group III phosphide semiconductors (for example, GaP), and third group of stone-based semiconductors (group III). Arsenide il w semiconductors) (for example, AlGaAs), tri-five semiconductors (such as ZnS, ZnSe, CdSe or CdTe), carbonized carbide, bismuth, stellite or alloys thereof. The dielectric material may include diamond (dimond), yttrium aluminium garnet (YAG), metal oxide, metal fluoride, optical glass, chalcogenide Glass). For example, metal oxide may include aluminum oxide (sapphire), tungsten oxide, tellurium oxide, titanium oxide, nickel oxide (nickel). Oxide), zirconium oxide (cubic zirconia), indium oxide, tin oxide, barium oxide, strontium oxide, oxidation Oxide), zinc oxide, gallium oxide, antimony oxide, oxygenated molybdenum oxide, oxygen oxide, lead oxide or Bismuth oxide and the like. For example, the metal fluoride may include fluorinated (caicium 9002-A33414TWF/X07-053/ianchen 8 200950132 fluoride) or magnesium fluoride or the like. For example, the optical glass may include the optical glass of the model SF57, SF59, SFL56, LaSF, LaSFN9, LaSFN18 or LaSFN30 of Schott Glass, Germany, and the optical type PBH71 of Ohara glass of Japan. glass. The chalcogenide glass may include bismuth-sulphide_sulfur_砸 glass ((Ge, Sb, Ga) (S, Se) glass). In the embodiment of the present invention, the material of the wafer 200 may include aluminum oxide (A1203), gallium arsenide (GaAs), germanium (Si), or carbon carbide (SiC). Each of the light-emitting element wafers 300 may include a half-turn conductor layer 202, a first electrode layer 206, and a second electrode layer 204. The semiconductor layer 202 is formed on the wafer 200. The semiconductor layer 202 can be a semiconductor layer having a p-type-n-type pn junction including at least two electrically connected p-type regions and n-type regions. A first electrode layer 206 is disposed on the semiconductor layer 202 and electrically connected to a surface of the semiconductor layer 202. For example, the first electrode layer 206 can be electrically connected to the p-type region of the semiconductor layer 202. A second electrode layer 204 is disposed on the back surface 201 of the wafer 200 and electrically connected to the other surface of the semiconductor layer 202 by the wafer 200. For example, the second electrode layer 204 can be electrically connected to the n-type region of the semiconductor layer 202. In one embodiment, the first electrode layer 206 and the second electrode layer 204 are respectively electrically connected to different conductive type regions of the semiconductor layer 202, and thus can be respectively used as the p-type electrode and the n-type electrode of the light-emitting element wafer 300. . In other embodiments, a reflector (not shown) may also be disposed in the semiconductor layer 202 to increase its luminous efficiency. In addition, an electronic component such as a photo diode (not shown) may be disposed in the light-emitting element wafer 300, and the electric 9002-A33414TWF/X07-053/ianchen 9 200950132 is connected to the semiconductor layer 202 to control The luminance of the semiconductor layer 202. In the embodiment of the present invention, the semiconductor layer 202 for a light emitting diode (LED) or a laser diode (LD) may be made of a group III nitride semiconductors, a third group. Group III phosphide semiconductors, group III arsenide semiconductors, compounds of tri-five elements and phosphorus, or other similar materials. For example, the semiconductor layer 202 may include gallium nitride (GaN), aluminum nitride (A1N), indium nitride (InN), germanium boron nitride (BN), aluminum indium nitride (AlInN), indium gallium nitride. (GalnN), aluminum gallium nitride (AlGaN), aluminum nitride nitride (BA1N), boron nitride indium (BInN), boron nitride gallium (BGaN), boron nitride aluminum gallium indium (BAlGalnN), aluminum phosphide ( A1P), gallium phosphide (GaP), indium phosphide (InP), aluminum gallium phosphide (AlGaP), indium gallium phosphide (GalnP), gallium arsenide phosphide (GaAsP), aluminum gallium indium phosphide (InGaAlP), Gas filling (GalnPN), filling indium gallium nitride (GalnAsP), crushing Al (AlAs), gallium arsenide (GaAs), indium arsenide (InAs), aluminum gallium arsenide (GaAlAs), gallium indium arsenide ( GalnAs), Shi Shenhua in Lu-Gallium Indium (AlGalnAs), Indium Bismuth Indium Gallium W (GalnAsN), Arsenic Telluride Gallium (GaAsSb). Then, a hole 213 covering the light-emitting element wafer 300 is formed on the light-emitting element wafer 300 to cover the light-emitting surface of the light-emitting element wafer 300 (for example, the upper surface of the semiconductor layer 202), for example, before the light-emitting element wafer 300 and An adhesive layer 208a is formed on the scribe line and A2, and a support layer (dam) 210 is formed on the adhesive layer. Next, the light-emitting device wafer 300 and a cover plate 212 are bonded, wherein the support layer 210 is interposed between the first electrode layer 206 and the cover plate 212, so as to be 9002-A33414TWF/X07-053/ of the light-emitting element wafer 300 and the cover plate 212. A hole 213 is formed between ianchen 10 200950132. In the embodiment of the present invention, the adhesive layer 2A8a may include an insulating material such as epoxy, silicone or benzocyclobutene (BCB). The support layer 210 may include an insulating material such as epoxy, silicone or benzocyclobutene (BCB). The cover plate 212 can pass the light generated by the semiconductor layer 202 to the outside, and the material thereof can include a transparent material such as lens-grade glass or quartz, so that the conventional encapsulant in the conventional light-emitting component can be prevented from being long-term. The disadvantage of using ® to degrade the material. Next, referring to Fig. 2b, the light-emitting element wafers 300 are separated stepwise along the scribe lines A! and A2 and insulated. For example, a portion of the wafer 200 may be removed from the back surface 201 of the wafer 200 by a selective removal step such as a lithography and an etching process until the semiconductor layer 202 is exposed to form a trench at the scribe lines Aj and A2 (Fig. Not shown). Next, an insulating layer 214 is formed conformally to the back surface 201 of the wafer 200 and the side surface 203 of the trench. For example, it can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), Tibetan clock method, printing method, inkjet method, dip clock method, spray coating method or spin coating method. Insulation layer 214. In the embodiment of the present invention, the material of the insulating layer 214 may include epoxy resin, polyamine, resin, oxidized dream, metal oxide or nitride. Then, a side surface 207 of the first electrode layer 206 above the wafer and a portion of the lower surface of the second electrode layer 204 under the wafer are exposed. For example, a selective removal step such as a lithography and an etching process may be reused to remove a portion of the insulating layer 214 at the bottom of the trench, a portion of the 9002-A33414TWF/X〇7-053/ianchen 11 200950132 layer 210, a portion The adhesive layer 208a and the partial cover 2i2 form a groove 220a at the cutting lanes A and A?, and expose the first side to the cut side 207. As shown in Fig. 2b, the trenches 22a extend from the back surface 201 of the crystal layer 2〇6 to the wafer 200, the semiconductor layer 2, the adhesion layer 208a of the support, and the partial cover 212. After the tooth is removed, a portion of the insulating layer can be removed from the back surface 201 of the wafer 200 by using an optional step such as a lithography and etching process.
的侧面 以電鍍 (electric plating)或化學氣相沉積（CVD)等方式八“ 中填入導電材料如金屬，以於每一個發光元件晶^層孔 之第一電極層206的下表面形成一介層孔插塞 發明實施例中，介層孔插塞222係做為第二電極在本 對外的電性連結。 204 形成硌出第一電極層204下表面之介層孔為止 接著’製作可分別電性連接第—電極層2〇6 207和第二電極層204下表面的導電結構。例如 接著，順應性於晶圓200的背面2〇1與溝槽22如、 内壁形成一導電層（圖未顯示），而在另一實施例中，上= 介層插塞222可和導電層一起形成。其次，執行圖案$ 導電層的步驟’利用例如微影和蝕刻製程等選擇性移☆ 步驟’移除部分位於晶圓200的背面201之塞带昆 〜子电層，以 同時形成複數個導線216和複數個圖案化導電層218。其 中導線216係用以提供半導體層2〇2的輸胃入/輪/出 (mPut/cmtput,IO)之電性連接，其中上述導線216係=括 第一導線216a和第二導線216b以分別電性連接晶片上 9002-A33414TWF/X07-053/ianchen 12 200950132 方之第一電極層206和晶片下方之第二電極層204。在另 一實施例中，於順應性形成導電層於溝槽220a的内壁 時，該導電層可包覆整個晶片之一侧面或甚至延伸至相 鄰的另一側面，以在不互相短路的情形下幾乎完全包覆 整個晶片的侧面週圍，因此當使用如鋁之金屬材料時， 除了可增加散熱效果外，亦可反射來自晶片的光線，有 助於提高發光效率。 其中介層孔插塞222的位置以避開第一導線216a為 ❹ 原則，舉例來說，如第2b圖所示，由於第一電極層206 係形成於發光元件晶片300上方之一侧邊，而第一導線 216a則從同一侧邊延伸至晶片下方，因此介層孔插塞222 可形成於發光元件晶片300下方之另一侧。 之後，於晶圓200下方之導線216和圖案化導電層 218表面形成銲球。例如可於晶圓200的背面201與溝槽 220a 的内壁順應性形成一防鮮層（solder mask layer)224，並覆蓋部分導線216和圖案化導電層218，露 出預留的終端接觸區域。接著，於露出的終端接觸區域 上形成包括銲球226a、226b和226c的球栅陣列（ball grid array)，其中導電用銲球226a和226c係形成於導線 216a、216b上，以分別經由導線216a、216b電性連接至 第一電極層206和第二電極層204，導熱用銲球226b則 形成於圖案化導電層218上，圖案化導電層218的面積 可稍大於焊球226b的面積，而鲜球226a、226b和226c 係共平面。 9002-A33414TWF/X07-053/ianchen 13 200950132 接著，請參考第2c圖，沿切割道A]和A2切割上述 晶圓200,使其分離成多個獨立的發光元件的晶圓級封裝 結構500a 〇 在以下各實施例中，各元件如有與第2a至2c圖所 示相同或相似的部分，則可參考前面的相關敍述，在此 不做重複說明。 第3a至3c圖為本發明另一實施例之發光元件的晶 圓級封裝的製程剖面圖。 © 請參考第3a圖，於晶圓200與蓋板212之間填充一 黏著層208b，其中黏著層208b可先附著於半導體層202 或蓋板212上，再予以重疊固化。 接著，請參考第3b圖，形成導電用銲球226a和226c 於導線216a、216b上，及導熱用銲球226b於圖案化導 電層218上。然後，請參考第3c圖，沿切割道入！和A2 切割上述晶圓2 0 0，使其分離成多個獨立的發光元件的晶 圓級封裝結構500b。 發光元件的封裝結構500a和500b的不同處為封裝 結構500b的發光元件晶片300與蓋板212係經由黏著層 208b緊密貼合而無空穴。另外，封裝結構500a和500b 的銲球226b與銲球226a、226c為同時形成的球栅陣列 (ball grid array)，但銲球226b並未電性連接至導線216 〇 在本發明實施例中，銲球226b可視為散熱銲球226b，其 數目並無限制，可依製程而定。當發光元件的封裝結構 500a或500b操作時，半導體層202所產生的熱可經由散 9002-A33414TWF/X07-053/ianchen 14 200950132 熱銲球226b導至發光元件的封裝結構500a或500b外。 在本發明實施例之發光元件的封裝結構中，由於半導體 層202與封裝結構500a或500b外側的距離遠小於習知 發光元件的打線型封裝結構，再加上散熱銲球226b直接 位於晶圓200背面201之薄絕緣層214下方，而未被印 刷電路板隔開，因此可迅速將半導體層202產生的熱導 至外界，封裝結構的熱阻可大為降低，因而得以提升發 光元件的封裝結構500a和500b的散熱效率和發光元件 © 的可靠度。 此外，在不同實施例中，可以經過改變晶圓200的 材質或發光元件晶片300幾何結構以提高發光元件晶片 300的發光效率，且降低遮蔽、增加光透率，或強化光折 射、反射的利用率。 第4a至4b圖為本發明其他實施例之具有不同發光 元件晶片300幾何結構的封裝結構400a和400b的剖面 圖。請參考第4a圖，由於半導體層202 —般係由多層磊 晶層形成，且包括p型蟲晶層和η型遙晶層，因此可經 由移除部份半導體層202例如ρ型磊晶層而露出部分η 型磊晶層表面，以使封裝結構400a的第一電極層206和 第二電極層204a可同時位於晶圓200的同一側（朝上）， 且分別電性連接半導體層202的p型區域和η型區域（圖 未顯示），並經由發光元件晶片300的側面203之導線216 分別電性連接至焊球226a和226c。在本實施例中，晶圓 200的材質可包括或半導體材料或金屬氧化物（metal 9002-A33414TWF/X07-053/ianchen 15 200950132 oxide)，其中半導體材料可包括碎（Si)，而金屬氧化物 (metal oxide)可包括氧化銘（alumimim oxide(藍寶石， sapphire))、氧化鶴（tungsten oxide)、氧化蹄（tellurium oxide)、氧化欽(titanium oxide)、氧化鎳（nickel oxide)、 氧化結（zirconium oxide，方晶錯石，cubic zirconia)、氧化 銦（indium oxide)、氧化錫（tin oxide)、氧化妃（barium oxide)、氧化勰（strontium oxide)、氧化鈣（calcium oxide)、 氧化鋅（zinc oxide)、氧化鎵（gallium oxide)、氧化銻 ❹（antimony oxide)、氧化鉬（molybdenum oxide)、氧化鉻 (chromium oxide)、氧化錯（lead oxide)或氧化錢(bisnmth oxide)等。如第4a圖所示，由於封裝結構4〇〇a的第一電 極層206和第二電極層204a不位於同一平面，可經由填 充黏著層208c使其平坦化，便於與蓋板212連接而無空 隙。 弟4b圖係顯示以覆晶（flip_chip)方式形成的封裝結 構400b。如第4b圖所示，封裝結構4〇〇b的晶圓2〇〇的 背面201朝上，可利用一黏著層2〇8(1和支撐層21〇黏结 晶圓200的背面201與蓋板212，其中支撐層21〇介於晶 圓200與盍板212之間，以於晶圓2〇〇與蓋板212之間 形成空穴213a。封裝結構400b的第一電極層2〇6和第二 電極層204a位於晶圓200的同一侧（朝上），且分別電性 連接半導體層202的p型區域和n型區域，並經由發光 兀件晶片300的側面203之導線216分別電性連接至焊 球226a和226c。在本實施例中，晶圓2〇〇的材質可包括 9002-A33414TWF/X07-053/ianchen 16 200950132 或半導體材料或金屬氧化物（metal oxide)，其中半導體材 料可包括石夕（Si)，而金屬氧化物（metal oxide)可包括氧化 紹（aluminum oxide(藍寶石，sapphire))、氧化鶴（tungsten oxide)、氧化碲（tellurium oxide)、氧化鈦（titanium oxide)、 氧化鎳（nickel oxide)、氧化錄（zirconium oxide，方晶鍅石， cubic zirconia)、氧化銦（indium oxide)、氧化錫（tin oxide)、氧化把（barium oxide)、氧化銀（strontium oxide)、 氧化妈（calcium oxide)、氧化鋅（zinc oxide)、氧化鎵 (gallium oxide)、氧化銻（antimony oxide)、氧化麵 (molybdenum oxide)、氧化絡（chromium oxide)、氧化錯 (lead oxide)或氧化祕（bismuth oxide)等。另外，如第 4b 圖所示，由於封裝結構400b的第一電極層206和第二電 極層204b不位於同一平面，可經由填充絕緣層215使其 平坦化，使後續形成之焊球226a、226b、226c仍能位於 同一平面上。 在其他實施例中’另外也可於晶片300下方製作不 同形狀的散熱結構，以達到散熱的目的。 第5a至5b圖為本發明其他實施例之具有散熱焊墊 230b的發光元件的封裝結構500c和500d的剖面圖。第 6a至6d圖為本發明其他實施例之具有散熱介層孔插塞 232的發光元件的封裝結構5〇〇e、500f、500g和500h的 剖面圖。第7a至7d圖為本發明其他實施例之具有内嵌 式散熱材料層234的發先元件的封裝結構500i、500j、 500k和5001的剖面圖。請參考第5a至5b圖，其顯示以 9002-A33414TWF/X07-053/ianchen 17 200950132 第2c和3c圖之發光元件晶片300的幾何結構為實施例 的封裝結構50〇c和500d，可於第一導線216a和第二導 線216b形成之後，利用塗佈方式於晶圓2〇〇的背面201 的部分第一導線216a、第二導線216b和圖案化導電層 218上形成例如錫之導電材料的焊塾230a、. 23..0b和 230c，其中焊墊230a和230c係電性連接至第一導線216a 和第二導線216b’而焊墊230b係形成於圖案化導電層 218上’而銲墊230a、230b和230c係共平面。在本發明 ❹ 實施例中，焊墊230b可視為散熱焊墊230b。散熱焊墊 230b的數目並無限制’由於其總面積可較散熱銲球226b 的總面積大，以提供更大的散熱面積及更好的散熱效 率。富發光元件的封裝結構500c和500d操作時，半導 體層202所產生的熱可經由散熱焊墊230b導至發光元件 的封裝結構500c和500d外。在本發明實施例之發光元 件的封裝結構中，由於半導體層202與封裝結構5〇〇c或 500d外側的距離遠小於習知發光元件的打線型封裝結 ® 構’再加上散熱銲球226b直接位於晶圓200的背面201 之薄絕緣層214下方，而未被印刷電路板隔開，因此可 迅速將半導體層202產生的熱導至外界，封裝結構的熱 阻可大為降低，因而得以提升發光元件的封裝結構5〇〇c 和500d的散熱效率和發光元件的可靠度。舉例來說，根 據ANSYS公司的ICE PAK分析軟體模擬分析發光元件 的封裝結構500d的散熱行為，並以高功率發光二極體（發 光功率大於1W)做為半導體層202，可推知熱阻(thermal 9002-A33414TWF/X07-053/ianchen 18 200950132 resistance)值約為0.08 κ/W，其值遠小於目前習知具有導 線架之發光元件的打線封裝結構5K/W之熱阻值。由上 述模擬可知’本發明實施例的發光元件的封裝結構具有 良好的散熱特性。 第6a至6b圈為本發明其他實施例之具有散熱介層 孔插塞232的發光元件的封裝結構500e和500f的剖面 圖。請參考第6a至6b圖，其顯示以第4a圖之發光元件 晶片300的幾何結構為實施例的封裝結構5〇〇(；和500d， ❿可於導線216和圖案化導電層218形成之前，以例如雷 射鑽孔等方式，從晶圓200的背面201移除部分絕緣層 214和部分晶圓200，以於晶圓2〇〇中形成複數個介層孔 (圖未顯示）。之後，再以例如電鍍（electric plating)或化學 氣相沉積（CVD)等方式於介層孔中填入導電金屬，以於晶 圓200a中形成介層孔插塞232。在本發明實施例中，介 層孔插塞232可視為散熱介層孔插塞232，其係從晶圓 ❹ 200的背面201延伸至該晶圓200中，並連接至銲球 226a、226b、226c 或焊墊 230a、230b、230c，可提供另 一種從晶圓200中至發光元件的封裝結構500e、500f、 500g和500h外的散熱路徑，可更快速地將半導體層202 所產生的熱經由散熱介層孔插塞232至銲球226a、226b、 226c或焊墊230a、230b、230c導至發光元件的封裝結構 500e和500f外。在本發明實施例之發光元件的封裝結構 中’由於半導體層202與封裝結構500e或500f外侧的距 離遠小於習知發光元件的打線型封裝結構，再加上散熱 9002-A33414TWF/X07-053/ianchen 19 200950132 介層孔插塞232、銲球226a、226b、226c或焊墊230a、 230b、230c直接位於晶圓200的背面201之薄絕緣層214 下方’而未被印刷電路板隔開，因此可迅速將半導體層 202產生的熱導至外界，封裝結構的熱阻可大為降低，因 而得以提升發光元件的封裝結構50〇e和500f的散熱效率 和發光元件的可靠度。 第7a至7d圖為本發明其他實施例之具有内嵌式散 熱材料層234的發光元件的封裝結構500i、500j、500k ❹ 和5001的剖面圖。請參考第7a至7d圖，其顯示以第2c 和3c圖之發光元件晶片300的幾何結構為實施例的封裝 結構500i、500j、500k和50(Π，可於形成絕緣層214之 前，於第二電極層204的下方形成一散熱材料層234。可 利用電鐘（electric plating)或物理氣相沉積等方式形成例 如金屬之散熱材料層234。散熱材料層234内嵌於發光元 件的封裝結構500i、500j、500k和5001中，且介於第二 電極層204與絕緣層214之間，可提供另一種從晶圓200a 至發光元件的封裝結構500i、500j、500k和5001外的散 熱路徑，當發光元件的封裝結構500i、500j、500k和5001 操作時，半導體層202所產生的熱可經由散熱材料層234 至散熱銲球226b或散熱焊墊230b導至發光元件的封裝 結構500i、500j、500k和5001外。由於半導體層202與 封裝結構500e或500f外侧的距離遠小於習知發光元件的 打線型封裝結構，再加上散熱材料層234、散熱銲球226b 或散熱焊墊230b直接位於晶圓200的背面201之薄絕緣 9002-A33414TWF/X07-053/ianchen 20 200950132 層214下方，而未被印刷電路板隔開，因此可迅速將半 導體層202產生的熱導至外界，封裝結構的熱阻可大為 降低，因而得以提升發光元件的封裝結構500i、500j、500k 和5001的散熱效率和發光元件的可靠度。 其中當散熱材料層234亦為導電材料時，導電插塞 222可停止於散熱材料層234表面而不必接觸下電極 204 ° 第8a至8d圖為本發明其他實施例之具有螢光層 ❹ 236a和236b的發光元件的封裝結構500m、500η、500〇 和500ρ的剖面圖，其可為白色或其他彩色之發光二極體 的封裝結構，使上述發光二極體產生白光或其他彩色 光。請參考第8a至8d圖，其顯示以第2c和3c圖之發光 元件晶片300的幾何結構為實施例的封裝結構500m、 500η、500〇和500p，可於黏結晶圓200與蓋板212之前， 於發光元件晶片300與蓋板212之間形成一螢光層236a 或236b。如第8a和8c圖所示，可利用塗佈（coating)等 方式，將例如磷之螢光粉覆蓋於蓋板212面對於發光元 件晶片300的表面上，以形成螢光層236a，再黏結晶圓 200與蓋板212，以形成具有空穴213之發光元件的封裝 結構500m和500〇,其中螢光層236a係連接於蓋板212, 且與發光元件晶片300相隔一距離。甚至，在其他實施 例中，也可將螢光粉均勻分佈於支撐層210中，使支撐 層210也具有螢光層的功能，以增加發光元件的封裝結 構的發光效率。或者，如第8b和8d圖所示，可將例如 90.02-A33414TWF/X07-053/ianchen 21 200950132 磷之螢光粉與例如環氧樹脂（e p 〇 x y)或矽樹脂之光學膠混 合，使螢光粉均勻分佈於光學膠中。接著可利用塗佈 (coating)等方式，將上述具有螢光粉之光學膠覆蓋於發光 元件晶片300上，以形成螢光層236b，再黏結晶圓200a 與蓋板212，以形成不具有空穴之發光元件的封裝結構 500η和500p，其中螢光層236b係填充於發光元件晶片 300與蓋板212之間。在如第8b和8d圖所示之實施例中， 由於螢光層236b係為包含螢光粉之一膠體層（glue ❹ layer)，也可直接取代黏著層208b而用以黏結發光元件 晶片300與蓋板212。上述具有螢光層的發光元件的封裝 結構中的散熱結構也可如第6a至6b圖或第7a至7d圖 所示之介層孔插塞232或散熱材料層234。 第9圖為本發明其他實施例之具有微透鏡結構238a 的發光元件的封裝結構500q的剖面圖。請參考第9圖， 其顯示以第2c圖之發光元件晶片300的幾何結構為實施 例的封裝結構500q，可於黏結晶圓200與蓋板212之前， 於發光元件晶片300上形成一微透鏡結構238a，且介於 發光元件晶片300與蓋板212之間，藉此可增加導引或 聚焦來自發光元件晶片300之光線的功能，因此亦通用 於發光元件晶片陣列之設計。如第9圖所示之微透鏡結 構238a係位於空穴213中，且對應發光元件晶片300。 上述微透鏡結構238a可依客製化要求而設置。上述具有 微透鏡結構238a的發光元件的封裝結構中的散熱結構也 可搭配如第6a至6b圖或第7a至7d圖所示之介層孔插 9002-A33414TWF/X07-053/ianchen 22 200950132 塞232或散熱材料層234。另外，上述具有微透鏡陣列 238a的發光元件的封裝結構，也可於發光元件晶片300 與蓋板212之間設置如第8a至8d圖所示螢光層236a， 或直接設覆蓋於微透鏡結構238a之上。 第10a至10d圖為本發明其他實施例之具有透鏡結 構240的發光元件的封裝結構500u、500v、500w和500x 的剖面圖。請參考第l〇a至10d圖，其顯示以第2c和3c 圖之發光元件晶片300的幾何結構為實施例的封裝結構 ❹ 500u、500v、500w和500x，可於形成封裝結構500u、 500v、500w和500x之後，於蓋板212上選擇性地形成 透鏡結構240。上述透鏡結構240可依客製化要求而設 置。上述具有透鏡結構240的發光元件的封裝結構中的 散熱結構也可搭配如第6a至6b圖或第7a至7d圖所示 之介層孔插塞232或散熱材料層234。另外，上述具有透 鏡結構240的發光元件的封裝結構，也可於於發光元件 晶片300與蓋板212之間設置如第8a至8d圖所示之螢 光層236a或236b。 第11a和lib圖為本發明其他實施例之具有反光元 件242的發光元件的封裝結構500y和500z的剖面圖， 其係應用於具有空穴213之發光元件的封裝結構。請參 考第11a和lib圖，其顯示以第2c圖之發光元件晶片300 的幾何結構為實施例的封裝結構500y和500z，可於黏結 晶圓200與蓋板212之前，於支撐層210上覆蓋一層例 如金屬或介電質之反射層，以於鄰近空穴213的側壁上 9002-A33414TWF/X07-053/ianchen 23 200950132 形成一反光元件242，其中，反光元件242亦可傾斜一既 定的角度。由於反光元件242可擋住半導體層202原本 可能射入支撐層210的的部分光線（如第11a和lib圖的 箭頭所示），並反射至半導體層202正上方的區域，再穿 過蓋板212出射到外界，因此上述反光元件242可提升 半導體層202的發光效率。或者，在其他實施例中，也 可於支撐層210中摻入介電材料或利用上述介電材料做 為支撐層210,藉由支撐層210和空穴213之間之不同介 ® 電係數差而具有反光功能，同樣也可提升半導體層202 的發光效率。 本發明實施例之發光元件的封裝結構包括一發光元 件晶片300，其包括一半導體層202 ; —介電層204，覆 蓋於上述半導體層202; —電極層206,設置於上述介電 層204上，並電性連接至上述半導體層202; —蓋板212， 設置於上述發光元件晶片300上；一導線216，順應性設 置於上述發光元件晶片300的側面203和背面201上， 慮1 並電性連接至上述電極層206。 本發明實施例之發光元件的封裝結構係具有以下優 點。發光元件係搭配封裝結構製程，封裝結構尺寸遠小 於習知發光元件打線(wire bond, WB)型封裝結構。當發 光元件構成晝素陣列以作為照明或顯示用途時，本發明 實施例之發光元件的封裝結構可使每個發光元件的間距 縮小，可增加晝素的連續性，使畫面目視效果更佳。本 發明實施例之發光元件的封裝結構可一次完成多個發光 9002-A33414TWF/X07-053/ianchen 24 200950132 凡件晶片之導線 ❹ ❹ , · 散熟結構、榮光層、微透鏡陣列等元件製作再切割為多個獨立的發光元件的封裝結構，不須4知發光元件打線型封裝結構外加之導線架 Geadframe)或打金線，可較習知製程簡單且快速，其生產^度相對而言較快’元件測S(testing)製程速度也可大為 ，升。本發明實施例之發光元件的封裝結構中，由於發 “元件阳片至封裝結構外側的距離遠小於習知發光元裝結構，再加上散熱材料層、散熱銲球或散結構直接㈣晶圓的f面下方，而未被印 板㈣’因此可迅逹將發光元件晶片產生的熱導 至外界，封裝結構的熱 …、， 光元件的封p槿的：：降低’因而得以提升發 t裝…構的散熱效率和發光元雖然本發明已以各實_揭露如上 限定本發明，任何熟悉此項技 非用以 精神和範圍内，當可做些許更二:不：離本發明之保護範圍當視後附之中請專·圍所界定者為此準本發明之 9002-A33414TWF/X〇7-〇53/ianchen 25 200950132 【圖式簡單說明】 1圖為習知的LED封裝結構。 第2a至2(；圖為本發明_， Λ„ 貫施例之發光元件的曰Ρ1 級封裝的製程剖面圖。 仟的日日Η 第3a至3c圖為本發明 圓級封裝的製程剖面圖。 另—實施例之發光元件的晶The side surface is filled with a conductive material such as a metal by electric plating or chemical vapor deposition (CVD) to form a via layer on the lower surface of the first electrode layer 206 of each of the light-emitting element hole layers. In the embodiment of the aperture plug, the via plug 222 is used as the external electrical connection of the second electrode. 204 is formed to form a via hole on the lower surface of the first electrode layer 204, and then can be separately fabricated. The conductive structure of the lower surface of the first electrode layer 2〇6 207 and the second electrode layer 204 is connected. For example, compliant with the back surface 2〇1 of the wafer 200 and the trench 22, for example, the inner wall forms a conductive layer (Fig. Displayed, while in another embodiment, the upper = via plug 222 can be formed with the conductive layer. Second, the step of performing the pattern $ conductive layer 'selectively shifts ☆ step by using, for example, lithography and etching processes A plurality of wires 216 and a plurality of patterned conductive layers 218 are formed at the same time, except for a portion of the back surface 201 of the wafer 200. The wires 216 are used to provide the input of the semiconductor layer 2〇2. /round / out (mPut / cmtput, IO) electrical Connecting, wherein the wire 216 is included with the first wire 216a and the second wire 216b to electrically connect the first electrode layer 206 on the wafer and the second electrode under the wafer, respectively, on the wafer 9002-A33414TWF/X07-053/ianchen 12 200950132 Layer 204. In another embodiment, when the conductive layer is formed on the inner wall of the trench 220a in compliance, the conductive layer may cover one side of the entire wafer or even extend to the adjacent other side so as not to each other In the case of a short circuit, almost completely wraps around the side of the entire wafer, so when a metal material such as aluminum is used, in addition to increasing the heat dissipation effect, light from the wafer can also be reflected, which contributes to an improvement in luminous efficiency. The position of the plug 222 is based on the principle of avoiding the first wire 216a. For example, as shown in FIG. 2b, the first electrode layer 206 is formed on one side of the light-emitting element wafer 300, and the first wire is formed. The 216a extends from the same side to the underside of the wafer, so the via plug 222 can be formed on the other side below the light emitting device wafer 300. Thereafter, the conductive line 216 and the patterned conductive layer 21 under the wafer 200. 8 is formed on the surface of the solder ball. For example, a solder mask layer 224 may be formed on the back surface 201 of the wafer 200 and the inner wall of the trench 220a, and a portion of the conductive trace 216 and the patterned conductive layer 218 may be covered to expose the recess. a terminal contact region. Next, a ball grid array including solder balls 226a, 226b, and 226c is formed on the exposed terminal contact region, wherein conductive solder balls 226a and 226c are formed on the wires 216a, 216b. The conductive balls 226b are formed on the patterned conductive layer 218 by electrically connecting the conductive balls 226b to the first electrode layer 206 and the second electrode layer 204 via wires 216a and 216b, respectively. The area of the patterned conductive layer 218 may be slightly larger than the solder balls. The area of 226b, while the fresh balls 226a, 226b, and 226c are coplanar. 9002-A33414TWF/X07-053/ianchen 13 200950132 Next, referring to FIG. 2c, the wafer 200 is cut along the scribe lines A] and A2 to separate the wafer-level package structure 500a into a plurality of independent light-emitting elements. In the following embodiments, if the components have the same or similar parts as those shown in FIGS. 2a to 2c, reference may be made to the related description above, and the description thereof will not be repeated. 3a to 3c are cross-sectional views showing a process of a wafer-level package of a light-emitting element according to another embodiment of the present invention. © Referring to Fig. 3a, an adhesive layer 208b is filled between the wafer 200 and the cover 212. The adhesive layer 208b may be attached to the semiconductor layer 202 or the cover 212 first and then cured by overlap. Next, referring to FIG. 3b, conductive solder balls 226a and 226c are formed on the wires 216a and 216b, and the heat transfer solder balls 226b are formed on the patterned conductive layer 218. Then, please refer to Figure 3c, along the cutting path! And A2 dicing the wafer 250 to separate the wafer-level package structure 500b into a plurality of independent light-emitting elements. The difference in the package structures 500a and 500b of the light-emitting elements is that the light-emitting element wafer 300 and the cover plate 212 of the package structure 500b are closely adhered via the adhesive layer 208b without voids. In addition, the solder balls 226b and the solder balls 226a, 226c of the package structures 500a and 500b are simultaneously formed ball grid arrays, but the solder balls 226b are not electrically connected to the wires 216. In the embodiment of the present invention, The solder balls 226b can be regarded as the heat-dissipating solder balls 226b, and the number thereof is not limited and can be determined according to the process. When the package structure 500a or 500b of the light-emitting element operates, the heat generated by the semiconductor layer 202 can be conducted to the outside of the package structure 500a or 500b of the light-emitting element via the heat transfer ball 226b of the 9002-A33414TWF/X07-053/ianchen 14 200950132. In the package structure of the light-emitting device of the embodiment of the present invention, since the distance between the semiconductor layer 202 and the outer side of the package structure 500a or 500b is much smaller than that of the conventional light-emitting device, the heat-dissipating solder ball 226b is directly located on the wafer 200. The thin back insulating layer 214 of the back surface 201 is not separated by the printed circuit board, so that the heat generated by the semiconductor layer 202 can be quickly guided to the outside, and the thermal resistance of the package structure can be greatly reduced, thereby improving the package structure of the light emitting element. The heat dissipation efficiency of the 500a and 500b and the reliability of the light-emitting element ©. In addition, in different embodiments, the material of the wafer 200 or the geometry of the light-emitting element wafer 300 may be changed to improve the luminous efficiency of the light-emitting element wafer 300, and to reduce shielding, increase light transmittance, or enhance utilization of light refraction and reflection. rate. 4a through 4b are cross-sectional views of package structures 400a and 400b having different illuminating element wafer 300 geometries in accordance with other embodiments of the present invention. Referring to FIG. 4a, since the semiconductor layer 202 is generally formed of a plurality of epitaxial layers and includes a p-type silicon layer and an n-type crystal layer, a portion of the semiconductor layer 202 such as a p-type epitaxial layer can be removed. The surface of the portion of the n-type epitaxial layer is exposed such that the first electrode layer 206 and the second electrode layer 204a of the package structure 400a can be simultaneously located on the same side of the wafer 200 (upward), and electrically connected to the semiconductor layer 202, respectively. The p-type region and the n-type region (not shown) are electrically connected to the solder balls 226a and 226c via wires 216 of the side surface 203 of the light-emitting device wafer 300, respectively. In this embodiment, the material of the wafer 200 may include a semiconductor material or a metal oxide (metal 9002-A33414TWF/X07-053/ianchen 15 200950132 oxide), wherein the semiconductor material may include shredded (Si), and the metal oxide (metal oxide) may include alumimim oxide (sapphire), tungsten oxide, tellurium oxide, titanium oxide, nickel oxide, zirconium Oxide, cubic zirconia, indium oxide, tin oxide, barium oxide, strontium oxide, calcium oxide, zinc oxide Oxide, gallium oxide, antimony oxide, molybdenum oxide, chromium oxide, lead oxide or bisnmth oxide. As shown in FIG. 4a, since the first electrode layer 206 and the second electrode layer 204a of the package structure 4A are not in the same plane, they can be flattened via the filling adhesive layer 208c, facilitating connection with the cover 212 without Void. The 4b diagram shows a package structure 400b formed in a flip-chip manner. As shown in FIG. 4b, the back surface 201 of the wafer 2 of the package structure 4〇〇b faces upward, and an adhesive layer 2〇8 (1 and the support layer 21 may be used to adhere the back surface 201 of the crystal circle 200 to the cover plate. 212, wherein the support layer 21 is interposed between the wafer 200 and the yoke 212 to form a cavity 213a between the wafer 2 and the cover 212. The first electrode layer 2 〇 6 and the first portion of the package structure 400b The two electrode layers 204a are located on the same side of the wafer 200 (upward), and are electrically connected to the p-type region and the n-type region of the semiconductor layer 202, respectively, and are electrically connected via the wires 216 of the side surface 203 of the light-emitting element wafer 300, respectively. To the solder balls 226a and 226c. In this embodiment, the material of the wafer 2〇〇 may include 9002-A33414TWF/X07-053/ianchen 16 200950132 or a semiconductor material or a metal oxide, wherein the semiconductor material may include Shi Xi (Si), and metal oxide may include aluminum oxide (sapphire), tungsten oxide, tellurium oxide, titanium oxide, oxidation Nickel oxide, zirconium oxide , cubic zirconia), indium oxide, tin oxide, barium oxide, strontium oxide, calcium oxide, zinc oxide, gallium oxide Gallium oxide), an antimony oxide, a molybdenum oxide, a chromium oxide, a lead oxide or a bismuth oxide, etc. Further, as shown in Fig. 4b, The first electrode layer 206 and the second electrode layer 204b of the package structure 400b are not in the same plane, and can be planarized by filling the insulating layer 215, so that the subsequently formed solder balls 226a, 226b, 226c can still be on the same plane. In other embodiments, different shapes of heat dissipation structures may be fabricated under the wafer 300 to achieve heat dissipation. FIGS. 5a to 5b illustrate a package structure 500c of a light-emitting element having a heat dissipation pad 230b according to another embodiment of the present invention. Fig. 6a to Fig. 6d are cross-sectional views showing package structures 5〇〇e, 500f, 500g and 500h of a light-emitting element having a heat dissipation via plug 232 according to another embodiment of the present invention. 7a through 7d are cross-sectional views of package structures 500i, 500j, 500k, and 5001 having the first component of the in-cell heat sink layer 234 in accordance with other embodiments of the present invention. Please refer to the figures 5a to 5b, which show the package structures 50〇c and 500d of the embodiment of the light-emitting element wafer 300 of the 9002-A33414TWF/X07-053/ianchen 17 200950132 sections 2c and 3c. After a wire 216a and a second wire 216b are formed, a portion of the first wire 216a, the second wire 216b, and the patterned conductive layer 218 of the back surface 201 of the wafer 2 are formed by soldering to form a conductive material such as tin.塾230a, . 23..0b and 230c, wherein pads 230a and 230c are electrically connected to the first wire 216a and the second wire 216b' and the pad 230b is formed on the patterned conductive layer 218' and the pad 230a 230b and 230c are coplanar. In the embodiment of the present invention, the pad 230b can be regarded as a heat dissipation pad 230b. There is no limit to the number of thermal pads 230b' because the total area can be larger than the total area of the thermal solder balls 226b to provide a larger heat dissipation area and better heat dissipation efficiency. When the package structures 500c and 500d of the light-rich components are operated, the heat generated by the semiconductor layer 202 can be conducted to the outside of the package structures 500c and 500d of the light-emitting elements via the heat-dissipating pads 230b. In the package structure of the light-emitting device of the embodiment of the present invention, since the distance between the semiconductor layer 202 and the outer side of the package structure 5〇〇c or 500d is much smaller than that of the conventional light-emitting device, the heat-dissipating solder ball 226b Directly under the thin insulating layer 214 of the back surface 201 of the wafer 200, and not separated by the printed circuit board, the heat generated by the semiconductor layer 202 can be quickly guided to the outside, and the thermal resistance of the package structure can be greatly reduced, thereby enabling The heat dissipation efficiency of the package structures 5〇〇c and 500d of the light emitting element and the reliability of the light emitting element are improved. For example, according to the ICE PAK analysis software of ANSYS, the heat dissipation behavior of the package structure 500d of the light-emitting element is analyzed, and the high-power light-emitting diode (the light-emitting power is greater than 1 W) is used as the semiconductor layer 202, and the thermal resistance can be inferred. The value of the 9002-A33414TWF/X07-053/ianchen 18 200950132 resistance) is about 0.08 κ/W, which is much smaller than the thermal resistance of the wire-wound package structure of the conventional light-emitting element having a lead frame. As is apparent from the above simulation, the package structure of the light-emitting element of the embodiment of the present invention has good heat dissipation characteristics. 6a to 6b are cross-sectional views of package structures 500e and 500f of a light-emitting element having a heat dissipation via plug 232 according to another embodiment of the present invention. Please refer to FIGS. 6a to 6b, which show the package structure 5〇〇 (; and 500d) of the structure of the light-emitting element wafer 300 of FIG. 4a before the formation of the wire 216 and the patterned conductive layer 218. A portion of the insulating layer 214 and a portion of the wafer 200 are removed from the back surface 201 of the wafer 200 by, for example, laser drilling or the like to form a plurality of via holes in the wafer 2 (not shown). Then, a conductive metal is filled in the via hole by, for example, electric plating or chemical vapor deposition (CVD) to form a via plug 232 in the wafer 200a. In the embodiment of the present invention, The via plug 232 can be viewed as a thermal via plug 232 that extends from the back side 201 of the wafer cassette 200 into the wafer 200 and is connected to the solder balls 226a, 226b, 226c or pads 230a, 230b, 230c, another heat dissipation path from the wafer 200 to the package structures 500e, 500f, 500g, and 500h of the light emitting element can be provided, and the heat generated by the semiconductor layer 202 can be more quickly plugged into the heat dissipation via hole 232 to Solder balls 226a, 226b, 226c or pads 230a, 230b, 230c lead to light In the package structure of the light-emitting element of the embodiment of the present invention, the distance between the semiconductor layer 202 and the outer side of the package structure 500e or 500f is much smaller than that of the conventional light-emitting element, plus Heat dissipation 9002-A33414TWF/X07-053/ianchen 19 200950132 via plug 232, solder balls 226a, 226b, 226c or pads 230a, 230b, 230c are directly under the thin insulating layer 214 of the backside 201 of the wafer 200' They are not separated by the printed circuit board, so that the heat generated by the semiconductor layer 202 can be quickly guided to the outside, and the thermal resistance of the package structure can be greatly reduced, thereby improving the heat dissipation efficiency and illumination of the package structures 50 〇e and 500 f of the light-emitting elements. The reliability of the components. Figures 7a to 7d are cross-sectional views showing package structures 500i, 500j, 500k ❹ and 5001 of a light-emitting element having an in-line heat dissipation material layer 234 according to another embodiment of the present invention. Please refer to Figures 7a to 7d. , which shows the package structures 500i, 500j, 500k, and 50 having the geometry of the light-emitting element wafer 300 of FIGS. 2c and 3c as an embodiment, before the insulating layer 214 is formed, on the second electrode layer 204. A heat dissipating material layer 234 is formed underneath. A heat dissipating material layer 234 such as a metal may be formed by electric plating or physical vapor deposition, etc. The heat dissipating material layer 234 is embedded in the package structure 500i, 500j, 500k of the light emitting element. And 5001, and between the second electrode layer 204 and the insulating layer 214, another heat dissipation path from the wafer 200a to the light emitting elements of the package structures 500i, 500j, 500k and 5001 can be provided, when the light emitting device is packaged When the structures 500i, 500j, 500k, and 5001 are in operation, heat generated by the semiconductor layer 202 may be conducted to the outside of the package structures 500i, 500j, 500k, and 5001 of the light emitting elements via the heat dissipation material layer 234 to the heat dissipation solder balls 226b or the heat dissipation pads 230b. Since the distance between the semiconductor layer 202 and the outer side of the package structure 500e or 500f is much smaller than that of the conventional light-emitting device, the heat dissipation material layer 234, the heat dissipation solder ball 226b or the heat dissipation pad 230b are directly located on the back surface 201 of the wafer 200. The thin insulation 9002-A33414TWF/X07-053/ianchen 20 200950132 is below the layer 214, and is not separated by the printed circuit board, so that the heat generated by the semiconductor layer 202 can be quickly guided to the outside, and the thermal resistance of the package structure can be greatly reduced. Therefore, the heat dissipation efficiency of the package structures 500i, 500j, 500k, and 5001 of the light-emitting elements and the reliability of the light-emitting elements can be improved. When the heat dissipation material layer 234 is also a conductive material, the conductive plug 222 can stop on the surface of the heat dissipation material layer 234 without contacting the lower electrode 204. FIGS. 8a to 8d are diagrams showing the phosphor layer 236a and other embodiments of the present invention. A cross-sectional view of the package structures 500m, 500n, 500A and 500p of the light-emitting elements of 236b, which may be a package structure of white or other colored light-emitting diodes, such that the light-emitting diodes generate white light or other colored light. Please refer to FIGS. 8a to 8d, which show the package structures 500m, 500n, 500A and 500p of the embodiment of the light-emitting element wafer 300 of FIGS. 2c and 3c, which can be before the crystallized circle 200 and the cover 212. A phosphor layer 236a or 236b is formed between the light emitting element wafer 300 and the cap plate 212. As shown in FIGS. 8a and 8c, a phosphor such as phosphorus may be coated on the surface of the cover member 212 on the surface of the light-emitting element wafer 300 by a coating or the like to form a fluorescent layer 236a. The crystal circle 200 and the cap plate 212 are formed to form package structures 500m and 500A having light-emitting elements having holes 213, wherein the phosphor layer 236a is connected to the cap plate 212 and spaced apart from the light-emitting element wafer 300. Even in other embodiments, the phosphor powder may be uniformly distributed in the support layer 210, so that the support layer 210 also functions as a phosphor layer to increase the luminous efficiency of the package structure of the light-emitting element. Alternatively, as shown in Figures 8b and 8d, for example, 90.02-A33414TWF/X07-053/ianchen 21 200950132 phosphorescent phosphor can be mixed with an optical glue such as epoxy resin (ep 〇xy) or enamel resin to make the firefly The light powder is evenly distributed in the optical glue. Then, the optical paste having the phosphor powder may be coated on the light-emitting element wafer 300 by coating or the like to form the fluorescent layer 236b, and the crystal circle 200a and the cap plate 212 may be adhered to form a non-empty space. The package structures 500n and 500p of the light-emitting elements of the holes, wherein the phosphor layer 236b is filled between the light-emitting element wafer 300 and the cap plate 212. In the embodiment shown in FIGS. 8b and 8d, since the phosphor layer 236b is a glue layer including one of the phosphors, the adhesive layer 208b may be directly substituted for bonding the light-emitting element wafer 300. With the cover plate 212. The heat dissipation structure in the package structure of the above-described light-emitting element having a fluorescent layer may also be a via plug 232 or a heat dissipation material layer 234 as shown in Figures 6a to 6b or 7a to 7d. Figure 9 is a cross-sectional view showing a package structure 500q of a light-emitting element having a microlens structure 238a according to another embodiment of the present invention. Referring to FIG. 9, a package structure 500q having the geometry of the light-emitting element wafer 300 of FIG. 2c as an embodiment is shown, and a microlens is formed on the light-emitting element wafer 300 before the crystallized circle 200 and the cover 212 are adhered. The structure 238a is interposed between the light-emitting element wafer 300 and the cap plate 212, whereby the function of guiding or focusing the light from the light-emitting element wafer 300 can be increased, and thus is also common to the design of the light-emitting element wafer array. The microlens structure 238a as shown in Fig. 9 is located in the cavity 213 and corresponds to the light-emitting element wafer 300. The microlens structure 238a described above can be provided in accordance with customization requirements. The heat dissipation structure in the package structure of the above-mentioned light-emitting element having the microlens structure 238a can also be matched with the interlayer hole insertion 9002-A33414TWF/X07-053/ianchen 22 200950132 as shown in Figures 6a to 6b or 7a to 7d. 232 or a layer of heat dissipating material 234. In addition, the package structure of the light-emitting element having the microlens array 238a may be disposed between the light-emitting element wafer 300 and the cover 212, such as the phosphor layer 236a shown in FIGS. 8a to 8d, or directly disposed on the microlens structure. Above 238a. 10a to 10d are cross-sectional views showing package structures 500u, 500v, 500w, and 500x of a light-emitting element having a lens structure 240 according to another embodiment of the present invention. Please refer to FIGS. 10a to 10d, which show the package structures ❹ 500u, 500v, 500w and 500x of the embodiment of the light-emitting element wafer 300 of FIGS. 2c and 3c, which can form the package structure 500u, 500v, After 500w and 500x, lens structure 240 is selectively formed on cover plate 212. The lens structure 240 described above can be provided in accordance with customization requirements. The heat dissipating structure in the package structure of the above-described light emitting element having the lens structure 240 can also be matched with the via plug 232 or the heat dissipating material layer 234 as shown in Figs. 6a to 6b or 7a to 7d. Further, the package structure of the light-emitting element having the lens structure 240 may be provided with a phosphor layer 236a or 236b as shown in Figs. 8a to 8d between the light-emitting element wafer 300 and the cap plate 212. 11a and lib are cross-sectional views showing package structures 500y and 500z of a light-emitting element having a light-reflecting element 242 according to another embodiment of the present invention, which are applied to a package structure of a light-emitting element having holes 213. Please refer to the 11a and lib diagrams, which show the package structures 500y and 500z of the embodiment of the light-emitting element wafer 300 of FIG. 2c as an embodiment, which can be covered on the support layer 210 before the crystallized circle 200 and the cover 212 are adhered. A reflective layer, such as a metal or dielectric, is formed on the sidewalls adjacent to the cavity 213 by a reflective element 242 formed on the sidewall of the cavity 213, wherein the retroreflective element 242 can also be tilted by a predetermined angle. Since the light reflecting element 242 can block part of the light that the semiconductor layer 202 may inject into the support layer 210 (as indicated by the arrows in FIGS. 11a and 11b), and reflect to the area directly above the semiconductor layer 202, pass through the cover 212. The light-emitting element 242 can elevate the light-emitting efficiency of the semiconductor layer 202. Alternatively, in other embodiments, a dielectric material may be incorporated into the support layer 210 or the dielectric material may be used as the support layer 210, and the difference between the support layer 210 and the cavity 213 may be different. With the reflective function, the luminous efficiency of the semiconductor layer 202 can also be improved. The package structure of the light-emitting device of the embodiment of the present invention includes a light-emitting device wafer 300 including a semiconductor layer 202, a dielectric layer 204 covering the semiconductor layer 202, and an electrode layer 206 disposed on the dielectric layer 204. And electrically connected to the semiconductor layer 202; a cover plate 212 is disposed on the light-emitting element wafer 300; a wire 216 is compliantly disposed on the side surface 203 and the back surface 201 of the light-emitting element wafer 300, and is electrically connected The electrode layer 206 is connected to the above. The package structure of the light-emitting element of the embodiment of the present invention has the following advantages. The light-emitting component is matched with the package structure process, and the package structure size is much smaller than the conventional wire bond (WB) type package structure. When the light-emitting elements constitute a pixel array for illumination or display purposes, the package structure of the light-emitting elements of the embodiments of the present invention can reduce the pitch of each light-emitting element, thereby increasing the continuity of the pixels and making the screen visually better. The package structure of the light-emitting element of the embodiment of the invention can complete a plurality of light-emitting devices 9002-A33414TWF/X07-053/ianchen 24 200950132, and the components of the wafers, the fused layer, the lenticular layer, the microlens array, etc. The package structure is cut into a plurality of independent light-emitting elements, and it is not necessary to know the wire-type package structure of the light-emitting element and the wire frame (Gadframe) or the gold wire, which is simpler and faster than the conventional process, and the production degree is relatively relatively simple. Fast 'component test' (testing) process speed can also be large, l. In the package structure of the light-emitting component of the embodiment of the invention, the distance between the component positive film and the outer side of the package structure is much smaller than that of the conventional light-emitting device, and the heat dissipation material layer, the heat dissipation solder ball or the bulk structure direct (four) wafer The lower side of the f-plane, but not the printed board (four) 'so can quickly guide the heat generated by the light-emitting element wafer to the outside, the heat of the package structure..., the sealing of the optical element:: 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 Scope of the scope of the attached please please define the scope of the 9002-A33414TWF/X〇7-〇53/ianchen 25 200950132. [Illustration of the diagram] 1 is a conventional LED package structure. 2a to 2(; Fig. 3 is a cross-sectional view showing a process of a 曰Ρ1 package of a light-emitting element according to the present invention. 日的日日Η 3a to 3c are process cross-sectional views of the circular package of the present invention Another embodiment of the crystal of the light-emitting element
一第4a至4b圖為本發明其他實施例 凡件晶片幾何結構的封裝結構的剖面圖 之具有不同發光 第5a至5b圖為本發明其他實 的發光元件的封裝結構的剖面圖。 施例之具有散熱焊墊 第6a至6b圖為本發明其他實施例之具有散熱介声 孔插塞的發光元件的封裝結構的剖面圖。 a 第7a至7d圖為本發明其他實施例之具有内嵌式散 熱材料層的發光元件的封裝結構的剖面圖。 ❹ 第8a至8d圖為本發明其他實施例之具有螢光層的 發光元件的封裝結構的剖面圖。 第9圖為本發明其他實施例之具有微透鏡陣列的發 光元件的封裝結構的剖面圖。 第l〇a至l〇d圖為本發明其他實施例之具有透鏡結 構的發光元件的封裝結構的剖面圖。 第11a至lib圖為本發明其他實施例之具有反光元 件的發光元件的封裝結構的剖面圖。 9002-A33414TWF/X07-053/ianchen 200950132 ❹ ⑩ 主要元件符號說明】 100〜LED封裝結構 30〜矽鑲嵌晶片； 34〜導線架； 56〜矽密封膠； 38〜塑膠外罩； 201〜背面； 203、 207〜侧面； 204、 204a、204b〜第二電極層； 206〜第一電極層； 208a > 208b > 208c 210〜支撐層； 213、213a〜空穴； 216〜導線； 216b〜第二導線； 220a、220b 〜溝槽； 226a、226b、226c 〜焊球； 230a、230b、230c 〜散熱墊 222、232〜介層孔插塞； 234〜散熱材料層； 238a、238b〜微透鏡結構； 242〜反光元件； 400a、400b、500a、500b 31〜LED晶片； 3.2〜金線； 37~散熱塊； 35〜透鏡； 200〜晶圓； 202〜半導體層； 208d〜黏著層； 212〜蓋板； 214、215〜絕緣層； 216a〜第一導線； 218〜圖案化導電層； 224〜防焊層； 236a、236b〜螢光層； 240〜透鏡結構； 300〜發光元件晶片； 500c、500d、500e、500f 500i、500j、500k、500卜 500m、500η、500ο、500p、500q 9002-A33414TWF/X07-053/ianchen 27 200950132 500u、500v、500w、500χ、500y、500z〜發光元件的封裝 結構； A!、A2〜切割道。A fourth embodiment of the present invention is a cross-sectional view of a package structure of a wafer structure having different illuminations. Figs. 5a to 5b are cross-sectional views showing a package structure of other actual light-emitting elements of the present invention. Embodiments of the heat-dissipating solder pads. Figs. 6a to 6b are cross-sectional views showing a package structure of a light-emitting element having a heat-dissipating acoustic hole plug according to another embodiment of the present invention. a Figures 7a through 7d are cross-sectional views showing a package structure of a light-emitting element having an in-line heat dissipating material layer according to another embodiment of the present invention. ❹ Figs. 8a to 8d are cross-sectional views showing a package structure of a light-emitting element having a fluorescent layer according to another embodiment of the present invention. Figure 9 is a cross-sectional view showing a package structure of a light-emitting element having a microlens array according to another embodiment of the present invention. 1a to 1D are cross-sectional views showing a package structure of a light-emitting element having a lens structure according to another embodiment of the present invention. 11a to lib are cross-sectional views showing a package structure of a light-emitting element having a light-reflecting element according to another embodiment of the present invention. 9002-A33414TWF/X07-053/ianchen 200950132 ❹ 10 Main component symbol description] 100~LED package structure 30~矽 inlay wafer; 34~ lead frame; 56~矽 sealant; 38~plastic cover; 201~back; 203, 207 to the side; 204, 204a, 204b to the second electrode layer; 206 to the first electrode layer; 208a > 208b > 208c 210~ support layer; 213, 213a~hole; 216~ wire; 216b~ second wire 220a, 220b ~ trench; 226a, 226b, 226c ~ solder ball; 230a, 230b, 230c ~ heat sink pad 222, 232 ~ via plug; 234 ~ heat sink material layer; 238a, 238b ~ microlens structure; ~ Reflective element; 400a, 400b, 500a, 500b 31~LED wafer; 3.2~ gold wire; 37~ heat sink block; 35~ lens; 200~ wafer; 202~ semiconductor layer; 208d~ adhesive layer; 214, 215~ insulating layer; 216a~first wire; 218~ patterned conductive layer; 224~ solder resist layer; 236a, 236b~fluorescent layer; 240~ lens structure; 300~ light emitting element wafer; 500c, 500d, 500e , 500f 500i, 500j, 500k, 500, 500m, 500n, 5 00ο, 500p, 500q 9002-A33414TWF/X07-053/ianchen 27 200950132 500u, 500v, 500w, 500χ, 500y, 500z~ package structure of light-emitting components; A!, A2~ cutting track.
9002-A33414TWF/X07-053/ianchen 289002-A33414TWF/X07-053/ianchen 28