CN102237478B - 在基板中安装器件的方法、安装有器件的基板结构和电子装置 - Google Patents
在基板中安装器件的方法、安装有器件的基板结构和电子装置 Download PDFInfo
- Publication number
- CN102237478B CN102237478B CN201110100274.4A CN201110100274A CN102237478B CN 102237478 B CN102237478 B CN 102237478B CN 201110100274 A CN201110100274 A CN 201110100274A CN 102237478 B CN102237478 B CN 102237478B
- Authority
- CN
- China
- Prior art keywords
- wiring layer
- metal wiring
- substrate
- resin bed
- described metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 104
- 238000000034 method Methods 0.000 title claims abstract description 67
- 238000009434 installation Methods 0.000 title claims abstract description 18
- 229910052751 metal Inorganic materials 0.000 claims abstract description 108
- 239000002184 metal Substances 0.000 claims abstract description 108
- 239000011347 resin Substances 0.000 claims abstract description 96
- 229920005989 resin Polymers 0.000 claims abstract description 96
- 239000011248 coating agent Substances 0.000 claims description 37
- 238000000576 coating method Methods 0.000 claims description 37
- 238000009713 electroplating Methods 0.000 claims description 17
- 229920001187 thermosetting polymer Polymers 0.000 claims description 14
- 238000000016 photochemical curing Methods 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 238000007711 solidification Methods 0.000 claims description 6
- 230000008023 solidification Effects 0.000 claims description 6
- 238000003825 pressing Methods 0.000 claims description 3
- 238000001723 curing Methods 0.000 claims 1
- 238000007747 plating Methods 0.000 abstract description 27
- 239000010410 layer Substances 0.000 description 96
- 239000004065 semiconductor Substances 0.000 description 13
- 238000003475 lamination Methods 0.000 description 10
- 239000000463 material Substances 0.000 description 10
- 238000012546 transfer Methods 0.000 description 8
- 230000008901 benefit Effects 0.000 description 7
- 230000008569 process Effects 0.000 description 7
- 239000000126 substance Substances 0.000 description 7
- 229910002601 GaN Inorganic materials 0.000 description 6
- 230000005540 biological transmission Effects 0.000 description 6
- 230000008021 deposition Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 230000008859 change Effects 0.000 description 4
- 239000011247 coating layer Substances 0.000 description 4
- 238000004020 luminiscence type Methods 0.000 description 4
- 230000003287 optical effect Effects 0.000 description 4
- 230000000052 comparative effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 238000003776 cleavage reaction Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 230000007017 scission Effects 0.000 description 2
- 239000004634 thermosetting polymer Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000008187 granular material Substances 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 230000008676 import Effects 0.000 description 1
- 230000001976 improved effect Effects 0.000 description 1
- 238000011900 installation process Methods 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000000088 plastic resin Substances 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 238000005381 potential energy Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
- H05K3/305—Affixing by adhesive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/2401—Structure
- H01L2224/24011—Deposited, e.g. MCM-D type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/2405—Shape
- H01L2224/24051—Conformal with the semiconductor or solid-state device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/2499—Auxiliary members for HDI interconnects, e.g. spacers, alignment aids
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
- H01L2224/251—Disposition
- H01L2224/2512—Layout
- H01L2224/25175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73217—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
- H01L2224/82001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving a temporary auxiliary member not forming part of the bonding apparatus
- H01L2224/82002—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving a temporary auxiliary member not forming part of the bonding apparatus being a removable or sacrificial coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
- H01L2224/821—Forming a build-up interconnect
- H01L2224/82101—Forming a build-up interconnect by additive methods, e.g. direct writing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
- H01L2224/8212—Aligning
- H01L2224/82136—Aligning involving guiding structures, e.g. spacers or supporting members
- H01L2224/82138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
- H01L2224/8212—Aligning
- H01L2224/82143—Passive alignment, i.e. self alignment, e.g. using surface energy, chemical reactions, thermal equilibrium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
- H01L2224/82986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83193—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
- H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
- H01L2224/83871—Visible light curing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/9205—Intermediate bonding steps, i.e. partial connection of the semiconductor or solid-state body during the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00013—Fully indexed content
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1203—Rectifying Diode
- H01L2924/12036—PN diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09909—Special local insulating pattern, e.g. as dam around component
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10007—Types of components
- H05K2201/10106—Light emitting diode [LED]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0703—Plating
- H05K2203/072—Electroless plating, e.g. finish plating or initial plating
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/15—Position of the PCB during processing
- H05K2203/1581—Treating the backside of the PCB, e.g. for heating during soldering or providing a liquid coating on the backside
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Led Device Packages (AREA)
- Wire Bonding (AREA)
- Led Devices (AREA)
Abstract
本发明涉及在基板中安装器件的方法、安装有器件的基板结构和电子装置。该安装有器件的基板结构包括:基板;金属布线层,其位于所述基板上,所述金属布线层中具有开口;树脂层,其至少位于所述基板的与所述金属布线层的所述开口重叠的一部分上;及器件,其位于所述树脂层上,并且所述器件位于所述金属布线层的所述开口的上方并通过所述树脂层固定到所述基板。本发明能够使用电镀在布线基板和器件电极之间获得稳定的结合。
Description
相关申请的交叉参考
本申请要求2010年4月28日向日本专利局提交的日本专利申请JP2010-103142的优先权,在这里将该在先申请的全部内容以引用的方式并入本文。
技术领域
本发明涉及在基板中安装器件的方法和安装有器件的基板结构,其中,在该方法和基板结构中,将基板的布线用作晶种金属(seedmetal),通过使用电镀(electrolyticplating)来连接器件的端子,本发明还涉及包括该安装有器件的基板结构的电子装置。
背景技术
为了将诸如半导体芯片或个别部件之类的器件安装在由半导体或树脂制成的布线基板上,可如同在普通印刷布线基板中一样将器件安装在单个布线基板的一个表面或两个表面中,或者可以安装在多层布线基板中。
其中,为了制造多层布线基板,已知的方法(积层,build-up)是:在形成在基座基板(basesubstrate)的一个表面上的导电层上安装器件,并通过在单侧上重复进行层间绝缘层的形成、布线的形成和器件安装来积层多层基板。另外,还存在如下已知方法:该方法在核心基板(coresubstrate)的两个表面都形成布线、形成层间绝缘层和进行器件安装。
还有一种积层方法:在半导体基板(基座芯片)上堆叠其它裸片并进行端子间的连接。
在将器件安装到布线基板上的情况下,尤其是在被安装的器件极小且数量较多的情况下,对于在布线基板上共同布置(转印)多个器件的技术来说,具有高精确度十分重要。
例如,日本专利文献JP-A-2004-273596公开了这类器件转印技术。在这个专利文献中,在第一基板上的树脂层中保持器件,通过保持有器件的树脂层侧将第一基板结合到第二布线,并且在树脂层和第一基板之间的界面处进行剥离,从而将器件共同转印到第二分离基板。
在基板面积极大时,这类器件转印方法特别有效。另外,当极大量的器件高精度地规则布置时,将器件保持在树脂层中并将器件共同转印到不同基板的方法更加有效。
为此,日本专利文献JP-A-2004-273596披露了一种具有发光LED器件的LED显示器的制造方法。
然而,不限于将这类器件共同转印的情况,不论是将器件安装在单层基板中还是安装在多层基板中,在将器件布置在布线基板中之后,期望在器件的电极焊盘和布线之间提供既机械稳定又电气稳定的结合。
为此,日本专利文献No.3956955和JP-A-2005-311109披露了一种化学镀方法作为连接器件和布线基板的方法。
日本专利文献JP-A-2004-273596在其示例中披露了一种使用化学镀方法连接布线基板和被安装器件之间的端子的方法。
另外,根据日本专利文献JP-A-2005-311109,使用微量分液器(micro-dispenser)等类似器件将被称作底部填充胶(under-fill)的材料涂覆在布线基板上,并将器件(半导体激光器)结合在底部填充胶材料上。使用诸如倒装芯片接合器之类的能够实现对准的装置来布置器件。在这种情况下,在器件焊盘和布线之间形成几微米至十微米(μm)的间隙,并在这个状态下进行化学镀处理。
如日本专利文献No.3956955所披露,当使用化学镀方法连接布线基板和布线基板上所布置的器件的上表面上的电极时,布线上的化学镀沉积和电极焊盘上的化学镀沉积同时生长。在这个过程中,随着镀层从两侧靠近,最终获得难以导入化学镀溶液的结构。因此,随后进行沉积增加厚度。于是,在这些部分中产生所谓的微隙(micro-gap)。如果不将镀层生长成为10~30μm的厚度以填充间隙,则难以适当地连接两个导电层(包括布线和电极焊盘)。另外,即使临时填充间隙,仍会产生机械强度弱的部分。
根据日本专利文献JP-A-2005-311109,两个导电层(包括布线和器件的电极焊盘)面对面地相对,它们之间的间隙窄至几微米到十微米(μm)。因此,相对难以产生间隙。即使在这种情况下,由于使用化学镀从两个方向进行沉积,所以仍产生不具有足够机械强度的间断沉积界面。
然而,在由上述积层方法形成的连接结构中,需要在安装器件之后形成层间绝缘膜并形成贯通孔等。因此,器件需要具有耐热性。另外,绝缘膜自身的成本也较高。
另外,在器件极小且在其上表面和下表面上均形成电极焊盘的情况下,在普通积层连接中需要以下过程。
首先,在基板上安装器件,在器件的表面上形成电极焊盘。然后,另一基板与形成有电极焊盘的表面结合,从而将器件置入其中。接着,除去最初安装有器件的基板,以便在与器件的形成有电极焊盘的表面面对的另一表面上形成电极焊盘。
在这类积层连接方法中,步骤多,因此降低了产品产率。
如果器件是发光器件且是朝基板的前表面侧发光的顶部发光型器件,则积层中所使用的材料需要有耐光性。另外,在朝基板的后表面侧发光的底部发光型器件的情况下,则安装中所使用的材料需要有耐光性。因此,难以实现同时满足两个条件的材料。尤其是,在其光密度高于其它显示器的光密度100倍以上的微LED显示器中,仅较少数量的有限材料满足这些条件。
发明内容
本发明公开了多个实施例,其中,在实施例中,提供了在基板中安装器件的方法和安装有器件的基板结构,其中,通过使用电镀作为取代上述积层连接方法的新方法在布线基板和器件电极之间获得稳定的结合。
在一个实施例中,提供了一种安装有器件的基板结构,所述安装有器件的基板结构包括:基板;金属布线层,其位于所述基板上,所述金属布线层中具有开口;树脂层,其至少位于所述基板的与所述金属布线层的所述开口重叠的一部分上;及器件,其位于所述树脂层上,所述器件布置在所述金属布线层的所述开口的上方并通过所述树脂层结合到所述基板。
在另一实施例中,所述树脂层在所述器件的周围还包括光固化区域。
在另一实施例中,所述安装有器件的基板结构包括在所述金属布线层上的镀层,所述镀层电连接所述金属布线层和所述器件。
在另一实施例中,提供了一种在基板中安装器件的方法,所述方法包括以下步骤:设置其一个表面上具有金属布线层的基板,所述金属布线层中具有开口;至少在所述基板的与所述金属布线层的所述开口重叠的一部分上形成热固树脂层;将器件放置在所述树脂层上,使得所述器件位于所述金属布线层的所述开口上方;及移除未曝光的所述树脂层。
在另一实施例中,所述方法还包括以下步骤:加热所述树脂层。
在另一实施例中,所述方法还包括以下步骤:通过使所述树脂层的至少一部分曝光于固化能量来固化所述树脂,所述曝光从基板的与具有所述金属布线层的表面相背对的表面开始。
在另一实施例中,所述方法包括以下步骤:通过使所述树脂层的至少一部分曝光于固化能量来部分地固化所述热固树脂层的区域,于是在所述器件的周围形成光固化区域。
在另一实施例中,所述方法包括以下步骤:通过使用电流电镀所述金属布线层,在所述金属布线层上形成镀层,所述镀层电连接所述金属布线层和所述器件。
在另一实施例中,提供了一种电子装置,所述电子装置包括组件。所述组件包括:基板;金属布线层,其位于所述基板上,所述金属布线层中具有开口;树脂层,其至少位于所述基板的与所述金属布线层的所述开口重叠的一部分上;及器件,其位于所述树脂层上,所述器件布置在所述金属布线层的所述开口的上方并通过所述树脂层结合到所述基板。
在另一实施例中,所述组件在所述器件的周围还包括光固化区域。
在另一实施例中,所述组件还包括在所述金属布线层上的镀层,所述镀层电连接所述金属布线层和所述器件。
附图说明
图1A~图1G是表示本发明的在基板中安装器件的方法的横剖面图。
图2是表示本发明的金属布线层和P电极之间的连接的外形的图。
图3是表示本发明的三合一芯片(triochip)的结构图。
图4A是表示本发明的三合一芯片的平面图,图4B是表示安装三合一芯片之后的平面基板的横剖面结构图。
图5A~图5G是表示本发明的在基板中安装器件的方法的横剖面图。
图6是表示通过SIM拍摄的发明的图5A~图5G的矩形所包围的区域的照片的图。
图7A是表示本发明的三合一芯片的平面图,图7B是表示安装该三合一芯片之后的平面基板的横剖面结构图。
图8是表示在不存在任何气隙的情况下直接将三合一芯片安装在三合一基板上的比较示例的横剖面图。
图9A~图9E是表示本发明的外延结构与半导体的芯片端面上的逐渐的电镀生长(creep-upplatinggrowth)之间关系的图。
图10是表示本发明的传递曝光系统的示意图。
具体实施方式
下文将参照附图详细说明本发明的优选实施例。尽管下文使用各种技术性的优选限定说明了优先实施例,但权利要求所述的本发明的范围不限于此,除非下文另有说明。
本发明的优选实施例涉及如下技术:该技术通过将布线基板上的晶种金属用作供电层来进行电镀。优选实施例公开了结构和方法,该方法使用电镀在晶种金属与位于晶种金属的向上方向上的器件的电极焊盘之间获得电连接。
将器件保持在树脂中,并去除树脂中除必要部分之外的部分,器件从而被临时固定到布线基板上。此后,通过电镀获得连接。
下列优选实施例包括在电镀期间固定器件的方法,具体包括电极和晶种金属之间的位置关系、临时固定方法、去除不必要部分的方法、适合电镀的器件结构等。下文将从这些方面进行说明。
图1A~图1G是表示本发明的在基板中安装器件的方法的横剖面图。
首先,参照图1G说明安装有器件的基板结构。
在LED显示器中,作为彩色像素发光单元的多个LED芯片(例如,红色、绿色和蓝色(RGB)半导体LED芯片)预先安装到平面基板中。例如,根据全高清(HD)规范,大约安装两百万个LED芯片。下文将这种彩色像素发光单元称作“三合一芯片”。三合一芯片对应于本发明实施例的“彩色像素芯片”的示例。
图1G表示在形成三合一芯片时安装在三合一芯片基板中的单个单色发光二极管(LED)半导体芯片的外形。在与图示的安装结构类似的结构中,添加发出其它两种颜色光的半导体芯片,以便并排布置三个半导体芯片。
虽然通过将半导体芯片(LED芯片3)安装到诸如石英玻璃之类的透明基板(称作三合一基板2或芯片布置基板)中来获得图1G所示的三合一芯片1,但在说明安装过程之前简要说明三合一芯片1的形成。
RGBLED芯片3是优选实施例中的“器件”的示例,LED芯片3是发光二极管器件,其包括诸如氮化镓之类的以氮化物半导体为基础的材料。
例如,LED芯片3具有双异质结构(double-heterostructure),在该结构中,有源层置于p披覆层和n披覆层之间。另外,这里所示的LED芯片3具有近乎平坦的平面形状,LED芯片3的有源层和披覆层在与基板的主表面平行的用于生长LED芯片3的有源层和披覆层的平面上延伸,该基板由蓝宝石(sapphire)制成。通过沉积氮化镓晶体层等形成这类层。
在这类半导体层中,需要至少部分地改变发光波长,因此难以在同一个基板上同时形成红色、绿色和蓝色三个LED芯片3。LED芯片3的尺寸非常小,以至其高度为几个微米或者一边或直径为数十个微米。通过半导体工艺在每个颜色的外延生长晶片上形成与这类芯片相对应的部分,以便实现非常薄的晶片厚度,接着将该部分转印到在接收侧的另一基板,以具有大于形成于晶片上的间距的布置间距。在这个转印过程中,使用激光冲孔(laserpunching)方法。
通过对每种颜色进行这类芯片转印操作来排列所谓的颜色布置。在这类颜色布置中,RGBLED芯片并排相邻地布置。将包含LED芯片3的基板转印到或移除到另一基板,以形成另一电极,从而在两个表面上形成不同的电极(对应于阳极的P电极和对应于阴极的N电极),其中,按这类颜色布置将彩色像素单元并排地重复布置,从而LED芯片3并排布置在基板上。
以此方式,预先制备器件的待安装在三合一基板2中的一侧。
在图1G中,例如,通过P电极3P侧将LED芯片3放置在三合一基板2的安装表面上。同时,在LED芯片3的表面上形成N电极3N。
在三合一基板2的安装表面上,预先形成在电镀期间充当晶种金属的布线层4R和4L(在下文中,如果没有具体说明,则将其称作金属布线层4)。尽管附图分开示出了布线层4R和4L,但它们至少具有相同的电位。可将布线层4R和4L连接并构造成平面图案。
金属布线层4是由例如Ti/Au等制成的布线,通过包括沉积、光刻(包括曝光和显影)和蚀刻等现有方法形成布线层4。
通过在LED芯片3和金属布线层4之间布置电镀层5以将LED芯片3结合到金属布线层4。电镀层5从金属布线层4的曝露表面的整个区域开始生长,且电镀层5的一部分逐渐生长到LED芯片3的侧表面的边缘部分。作为特征点,电镀层5填充在金属布线层4和LED芯片3的P电极3P之间面对的间隙中,或大致填充相应间隙。
另外,虽然在图1G中电镀层5逐渐生长到LED芯片3的侧面上,但根据电镀层的厚度等,并非必需逐渐生长到那里。
为了形成这种结构,在图1A中,通过依次进行例如溅镀、抗蚀剂形成、曝光、显影和蚀刻,在三合一基板2的一个主表面上形成布线层4R和4L。
参照图1A的横剖面图,布线层4R和4L在将要安装有LED芯片3的部分中相互分开。例如,布线层4R和4L是单个金属布线层的一部分,在该金属布线层中形成尺寸大约为4x4μm的开口。
参照图1B,在已形成的金属布线层4(包括4R和4L)上涂覆厚度例如大约为1.5μm的树脂(优选为感光树脂)。该树脂是由诸如加热或光照等外部因素固化的塑料树脂。这里,使用热固感光树脂6。可通过结合片状的树脂形成热固感光树脂6,或通过旋转涂覆等涂覆树脂并在预烘干中挥发溶剂等方式形成热固感光树脂6。另外,虽然可采用通过另一基板进行转印并移除的方法,但由于热固感光树脂6的厚度相对较薄,且不需要掩埋器件或凸凹部分,所以通过片结合或旋转涂覆足以形成热固感光树脂6。
这里,如图1C所示,对LED芯片3周围的部分进行部分曝光,以在该部分中形成光固化区域6A。除使用掩模的普通方法之外,也可使用离子束等进行部分曝光。
参照图1C,在热固感光树脂6上布置预先制备的LED芯片3。在这种情况下,不特别限制抵靠金属布线层4的位置。
参照图1D,对这个状态下的整个三合一芯片在例如50℃的温度下持续加热大约30分钟。可在适合树脂特性的范围内确定加热温度和时间。通过加热,降低了树脂的黏性,树脂逐渐生长到LED芯片3的侧壁,从而形成嵌边(fillet)。由于被加热树脂的分子易于稳定在最低能级状态,所以树脂施加一个力以将整个LED芯片3按压在嵌边中。如果向下按压LED芯片3,则P电极3P正下方的树脂被挤出到P电极3P的外侧,于是P电极3P趋近于金属布线层4。
借助这个力,P电极3P和金属布线层4之间的间隙降低至0~0.3μm,从而抵消在最初布置RGP芯片时上述间隙在RGP芯片之间存在的0.2~1.5μm的偏差。
然而,随着P电极3P靠近金属布线层4附近的某个点,由于完全移除树脂需要大量能量,所以难以进一步靠近这个点。由于这个原因,P电极3P和金属布线层4稳定成具有细的间隙。另外,即使P电极3P和金属布线层4实现相互接触,也难于在整个表面上紧靠,于是它们仅最大程度地部分相互靠近。
于是,虽然能够实现对布线的器件自对准,但优选地设置光固化区域6A,以便防止软化的树脂逸出到外部,于是改善了效果。虽然光固化区域6A优选地形成为围绕LED芯片3的周围,但也可间断地分成多片。
另外,如果光固化区域6A高精度地与金属布线层4相对准,则热固感光树脂6也相对金属布线层4的连接在xy方向上自对准。
参照图1E,优选地,从光学透明的三合一基板2的后表面曝光热固感光树脂6。在这种情况下,金属布线层4充当自对准掩模层,从而固化布线层4R和4L之间的区域处的树脂部分。固化的树脂部分用作“临时固定部分”。
另外,当由金属布线层4所获得的自对准掩模不充分时,会限制掩模路径或诸如6B等曝光区域。尤其是,为了在下文所述的传递期间进行后表面曝光,优选地,仅将金属布线层4用作掩模层。
参照图1F,通过显影来移除未曝光部分。在这种情况下,P电极3P和金属布线层4之间的间隙中的树脂被金属布线层4阻挡,从而未曝光。因此,溶解显影液,于是移除这个位置中的未曝光的树脂部分。由于器件保持在高强度的临时固定部分中,所以保留了这个间隙。
另外,如图1G所示,进行电镀。在电镀期间,例如通过向对应于负电极的金属布线层4和具有正电极的电镀溶液施加0.5~1.0V的电压,使10mA/cm2的电流在电镀溶液中流动。于是,如图1G所示,开始电镀生长,于是最终形成例如0.5μm厚的电镀层5。因此,电稳定地且机械稳定地连接金属布线层4和P电极3P。
图2是通过对真实示例进行SIM拍摄所获得的示意图,其表示金属布线层4和P电极3P之间的连接的外形。
参照图2,可以看到,在圆圈所围绕的部分中存在有连续的颗粒。因此,获得了稳定的结合。
根据这个方法,对应于电镀的两个结合对象的金属布线层4与P电极3P最初并不电连接。而且,P电极3P位于金属布线层4的向上的方向(电镀的主方向)上。根据这个实施例,P电极3P位于金属布线层4的向上的方向(电镀的主方向)上,使得它们几乎面对面。
由于它们不电连接,电镀开始从金属布线层4上生长。然而,由于电镀的生长顶面通常呈圆形,所以最初与电极焊盘接触的部分只限于点或非常有限的区域。
由于电接触,电镀在金属布线层4和与金属布线层4接触的P电极3P上生长,于是接触表面逐渐扩大。
以此方式,如果电镀从某个狭小范围逐渐扩大,则抑制了空隙的产生,且易于获得更具有整体性的组合颗粒。由于这个原因,与在开始镀层时两个结合目标是相互接触的电镀或化学镀相比,能够获得既机械稳定又电稳定的结合。
另外,通过在室温下进行电镀而获得结合的另一优点在于没有将热损害或机械损害施加到器件上。
除上述电镀外,还能够获得以下优点。
由于在器件的上表面上形成功能性器件,且能够在下表面上形成端子,所以能够使器件小型化并降低成本。
对于从器件的上表面发光的器件的情况,由于不同于积层连接,没有在器件的上表面上形成布线,所以发光器件的发光区域不受限于器件的端子和布线。另外,没有使发光器件的输出功率或诸如视角等发光特性劣化。
由于在器件的下表面上实现连接,所以,不同于积层连接,不需要用于减缓器件厚度的台阶的绝缘层。因此,能够降低绝缘膜形成过程所带来的热历程或应力,并能够降低成本,能够改善器件的可靠性。另外,能够降低器件所需的耐热温度。
尤其是,当使用普通树脂绝缘膜来固定诸如具有1~10W/cm2的高发光密度的LED等器件时,由于光使树脂绝缘膜劣化,于是降低了器件的可靠性。在本实施例中,能够以足够的强度将器件固定到布线基板,并获得不包括树脂的电连接。
另外,由于在器件的z方向上进行自对准,所以基板和器件之间的间隙保持不变,从实际意义上说,充分降低了镀层厚度。于是,能够使用电镀整体连接数百万个器件。
图3是表示本发明的三合一芯片1A的结构图。
图3所示的三合一芯片1A与图1G所示的芯片的相同点在于:在三合一基板2上形成金属布线层4,使用热固感光树脂6将LED芯片3的电极结合到金属布线层4。
另外,图3所示的三合一芯片1A与图1G所示的芯片的相同点在于:作为热固感光树脂6的保留部分的临时固定部分6B存在于金属布线层4的开口中。
这个实施例在LED芯片3的结构以及与LED芯片3的结构相对应的布线的配置方面不同于前述实施例。
图3所示的LED芯片3包括在下表面上并排布置的P电极3P和N电极3N。在内部结构中,在基板的主要部分的下表面上形成有源层31,并在有源层31上形成内部P电极32。同时,在与设置有高度差的一侧相对的另一侧中形成内部N电极33。内部P电极32和内部N电极33通过不同高度的插头分别连接到P电极3P和N电极3N。
具有这种结构的LED芯片3B是向上发光的顶部发光型LED芯片。在顶部发光型LED芯片中,临时固定部分6B不必具有透光性和耐光性。因此,其优点在于能够选择各种各样的材料。第一实施例同样具有这种优点。
另外,由于其安装方法与前述实施例相同,所以省略了相关说明。在这个实施例中,P电极3P和N电极3N以与金属布线层4几乎面对的方式布置在金属布线层4的向上方向上,并独立地连接到相面对的布线6P和6N。
因此,在这种连接中,完成了P侧和N侧的电连接,并完成了三合一芯片1A内的电连接。
本发明的另一实施例提供了一种在平面基板中安装三合一芯片(彩色像素结构的基本单元)的方法,在该方法中,能够使用第一或第二实施例的方法将内部LED芯片3安装在三合一基板2中。
图4A是表示三合一芯片10的平面图,图4B是表示安装三合一芯片10之后的平面基板的横剖面结构图。
图4A所示的三合一芯片10对应于本发明实施例的器件的示例。另外,图1A~图1G中的附图标记“1”所表示的器件以及图4A和图4B中的附图标记“10”所表示的器件均同样称作“三合一芯片”。然而,例如,通过透视图4B的内侧所获得的内部结构对应于图1A~图1G所示的内部结构。参照图4B,作为举例,由于在三合一基板2上形成LED芯片3,且从LED芯片3的两侧引出电镀层5,所以假定在图3的下表面中设置两个电极。
在本实施例中,三合一芯片的外表面上的电极焊盘结合到显示装置的平面基板20。
本示例的三合一芯片10是向上发光的顶部发光型芯片。在该顶部发光型芯片中,由于临时固定部6B不必具有透光性或耐光性,所以其优点在于能够选择各种各样的材料。
另外,由于该实施例的安装方法与第一实施例相同,所以省略了相关说明。
在这里,三合一芯片10的通过电镀连接的电极焊盘不同于图1A~图1G所示的内部连接焊盘。
在三合一芯片10中,主框架部分11和位于其侧壁下的外围部分12以与基板表面平行的方式突出。用于RGB颜色的负电极的电极焊盘3Nr、3Nb和3Ng并排设置在外围部分12的上表面上。在这种情况下,以如下方式布置焊盘:电极的侧表面的位置与外围部分12的突出的顶部表面相对准。优选地需要对准这个端面的位置,以易于使从外围部分12生长的电镀层与电极焊盘接触,接着对电极焊盘的整个表面进行电镀。
另外,本发明不排除不完全对准的情况,但电极的端面可从外围部分12的突出的端面更靠近器件的主框架,或者相反地,可从外围部分12更加突出。
在电极的端面从外围部分的突出的端面更靠近器件的主框架的情况下,电镀层22的厚度可优选地设定成大于外围部分12的端面与电极焊盘3N和3P的顶部表面之间的距离。
另外,这个实施例例示了如下情况:P电极3P和N电极3N的每个端面位于金属布线层4的向上方向上,并且几乎垂直于金属布线层4地隔开。
由于电镀层从金属布线层21的上表面生长,所以能够在电镀层的高度变成等于外围部分12的高度之后获得电极焊盘和电镀层之间的电连接。由于这个原因,在上述过程之后,在电极焊盘上也进行电镀。
即使当电极以这种方式布置在器件的后表面之外的其它部分时,如果电极位于晶种金属(金属布线层4)的向上方向上,仍能够获得优异的稳定电连接。
图5A~图5G是表示本发明实施例的在基板中安装器件的方法的横剖面图。
本示例的安装方法基本上与第一实施例所述的方法相同。然而,在图5E所示的用于曝光热固感光树脂6的一部分的过程中,通过设置在顶部侧上的掩模M的路径从顶部实现该曝光。从掩模M的开口穿过三合一芯片10的内侧的光(如,UV光)到达位于器件的下方的热固感光树脂6,于是部分地曝光热固感光树脂6。因此,在图5F中,在显影之后,在曝光部分中形成临时固定部分6B。
另外,在本示例中,临时固定部分6B的面积小于图5A~图5G所示的临时固定部分的面积,但可根据临时固定的需要任意确定临时固定部分6B的面积。
在图5G的电镀过程中,如在第三实施例中所讨论,从电镀生长路径上来看,电极焊盘与外围部分12的突出端面在同一平面上对准。由于这个原因,随着电镀生长成与电极焊盘的高度相同,提供了电接触,于是电镀开始在电极焊盘上生长。因此,容易在电极焊盘和电镀层之间的界面处形成稳定的结合。
图6是表示通过SIM拍摄图5A~图5G的矩形所包围的区域获得的图片的图。
应看到,在图6的圆圈所包围的区域中存在连续颗粒以获得稳定的结合。
具有这种结构的三合一芯片10是向上发光的顶部发光型芯片。在该顶部发光型芯片中,由于临时固定部分6B不需要具有透光性和耐光性,所以其优点在于能够选择各种各样的材料。该优点与第一实施例相同。
另外,由于该示例的安装方法与第一实施例相同,所以省略了相关说明。
本实施例涉及第三实施例和第四实施例的变型。
在临时固定部分6B的固定力强,且即使在更小区域中仍能够充分获得临时固定的情况下,能够应用底部发光型芯片。
例如,如图7A和7B所示,从平面图可以看出,感光树脂6M布置在三合一芯片10的四个角上。因此,能够获得从三合一芯片10的下表面的发光表面到平面基板20具有空气层(气隙)的空隙结构。
于是,与使用树脂填充的情况相比,在器件与气隙之间的界面和气隙与玻璃基板(平面基板20)之间的界面处产生光折射差异。因此,在平面基板20内产生光发射角度差异。
具体地,如图8所示,光在玻璃内以40~45度角从玻璃射出到空气中,具有比上述范围浅的角度的光被全部反射,于是易于产生损耗。图8示出了如下比较示例:在该比较示例中,三合一芯片10直接安装在平面基板20中,且未设有气隙。在这种安装结构中,在器件上形成作为贯通孔和布线的电极。
如果未设有气隙,或者置入空气之外的树脂等,则穿过平面基板20的内侧的光的角度整体上变浅。与此相反,如果如同本实施例设有气隙,则反射光的总量(比率)降低。由于这个原因,能够实现高光学输出比率和低功耗的LED显示器。
另外,在发光器件的情况下,能够提供固定器件的功能和提供耐光性。由于这个原因,如果在发光位置处生长树脂并在固定器件后移除树脂,则固定树脂不需要耐光性,于是在保持空隙的同时实现了电连接。在积层型中,由于空隙结构是通过相关绝缘膜掩埋,所以难以获得这种结构。
即使在这种情况下,P电极3P和N电极3N的每个端面位于金属布线层21的向上方向上,且几乎垂直于金属布线层21地隔开。
在形成三合一芯片1的过程中,如果LED芯片3赤裸地安装在三合一基板2上,并如第一实施例所述生长电镀层5,则如图1G所示,电镀生长逐渐达到LED芯片3的端面上。这是因为增加了这个部分中的有效电场。
在图9A~图9E中,更详细地说明了这个事实。
如图9A所示,如果对GaAs基板进行台面蚀刻(mesa-etching)或解理(cleavage),则GaAs基板的端面可取决于晶体结构具有反向台面(reversed-mesa)结构。这个事实本身不重要,但也在垂直半导体表面中产生加速的电镀生长(逐渐生长)。
图9B~图9E示意性示出生长铜的过程和外延基板结构之间的关系。
在外延基板中,例如在n-GaN层和p-GaN层之间(如图中的对应于二极管的PN结的部分所示)置入最大厚度大约为200nm的用于形成多个量子阱的未掺杂多层外延结构。在对应于这个二极管的PN结的部分中存在内建电势(电势垒)差异,除非在势垒上产生电势差异,电镀层的接触不受影响。然而,如图9E所示,如果施加超过内建电势差异的电压,则也在n-GaN层中进行电镀生长。接着,二极管特性劣化,最终,二极管基本上成为短路电阻。
另外,如图9C~图9D所示,如果即使当不施加超过内建电势差的电压时仍使电镀变厚,则p-GaN和n-GaN可能通过电镀膜短路。
在本变型示例中,为了防止这种现象,优选地,半导体LED芯片形成为使得PN结的内建电势等于或高于在电镀期间施加到金属布线层4和电镀溶液的电压(例如,0.5~1V)。
或者,为了避免接触,优选地,在激光二极管的解理表面中,通过使用涂覆端面的方法预先在端面上形成薄绝缘膜。
通过选择前述方式中的至少一种方式能够防止二极管特性的劣化。另外,由于如上所述通过应用本发明能够降低电镀的厚度,所以用于电镀端面的溶液是非必需的。
下面说明适于各种前述实施例中的后部曝光的曝光系统。这个曝光系统应用到前述实施例的方法的后部曝光。
典型地,图10所示的曝光系统100集成有平面传递装置。参照图10,在大尺寸LED显示器的传递路径的中部设有线形曝光装置102。传递装置包括传递辊101,用于控制速度的传递辊101轴向旋转,于是,使用与LED显示器面板P的后表面接触的传递辊101传递LED显示器面板P。
由于这个原因,当LED显示器面板P在传递中经过线形曝光装置102时,使用线扫描方法通过后表面曝光LED显示器面板P。
另外,控制辊可设置在线形曝光装置102的上方,使得提供更细的间距。
当由于将布线等用作自对准掩模而使得曝光的分辨率不必为高或分隔掩模并非必要时,这种曝光是合适的。
另外,在器件在LED显示器面板P的表面侧发光的情况下,可仅在器件的后表面保持器件。因此,能够防止在泄露光入射到保持树脂中时所导致的光学劣化。
而且,通过进行后部曝光,不需要大尺寸的昂贵曝光装置。
而且,这里的曝光装置可应用到显示器之外的其它具有光学透明基板的装置。
本领域技术人员应当理解,依据设计要求和其它因素,可以在本发明所附的权利要求或其等同物的范围内进行各种修改、组合、次组合及改变。
Claims (13)
1.一种安装有器件的基板结构,其包括:
基板;
金属布线层,其位于所述基板上,所述金属布线层中具有开口;
树脂层,其至少位于所述基板的与所述金属布线层的所述开口重叠的一部分上;
器件,其位于所述树脂层上,并且所述器件位于所述金属布线层的所述开口的上方并通过所述树脂层固定到所述基板,其中,所述器件具有连接端子,所述连接端子面对所述金属布线层且不与所述树脂层重叠;及
电镀层,其通过电镀从所述金属布线层的曝露表面的整个区域生长,并填充在所述金属布线层和所述连接端子之间面对的间隙中,所述电镀层使所述金属布线层和所述连接端子相互电连接,其中,所述金属布线层在电镀期间充当晶种金属,所述间隙是由朝着所述基板按压所述器件的情况下的所述金属布线层与所述连接端子之间的被以预定温度加热的所述树脂层的树脂确定的,且是通过在形成所述电镀层之前移除所述金属布线层与所述连接端子之间的所述树脂形成的。
2.如权利要求1所述的安装有器件的基板结构,其中,所述树脂层是光固化树脂。
3.如权利要求2所述的安装有器件的基板结构,其中,所述树脂层被选择性地固化,由此形成不与所述器件重叠的光固化部分。
4.如权利要求3所述的安装有器件的基板结构,其中,所述光固化部分在所述器件周围延伸。
5.一种在基板中安装器件的方法,其包括以下步骤:
(a)设置基板,所述基板的一个表面上具有金属布线层,所述金属布线层中具有开口;
(b)至少在所述基板的与所述金属布线层的所述开口重叠的一部分上设置热固且光固化树脂层;
(c)在所述树脂层上布置器件,使得所述器件位于所述金属布线层的所述开口的上方;
(d)通过选择性地使所述树脂层曝光于固化能量来选择性地固化所述树脂层;及
(e)移除未固化的所述树脂层;及
(f)通过电镀从所述金属布线层的曝露表面的整个区域生长电镀层,所述电镀层填充在所述金属布线层和所述器件之间面对的间隙中,并使所述金属布线层和所述器件相互电连接,其中,所述金属布线层在电镀期间充当晶种金属。
6.如权利要求5所述的在基板中安装器件的方法,其还包括以下步骤:在选择性地固化所述树脂层之前,加热所述树脂层。
7.如权利要求5所述的在基板中安装器件的方法,其中,选择性地固化所述树脂层的步骤包括使所述树脂层的至少一部分曝光于固化能量,所述曝光从所述基板的与具有所述金属布线层的表面相背对的表面开始。
8.如权利要求5所述的在基板中安装器件的方法,其还包括以下步骤:通过使所述树脂层的至少一部分曝光于固化能量来部分地固化所述树脂层的区域,从而在所述树脂层的不与所述器件重叠的一部分中形成光固化区域。
9.如权利要求8所述的在基板中安装器件的方法,其中,所述光固化区域在所述器件周围延伸。
10.一种电子装置,其包括组件,所述组件包括:
基板;
金属布线层,其位于所述基板上,所述金属布线层中具有开口;
树脂层,其至少位于所述基板的与所述金属布线层的所述开口重叠的一部分上;
器件,其位于所述树脂层上,并且所述器件位于所述金属布线层的所述开口的上方并通过所述树脂层固定到所述基板,其中,所述器件具有连接端子,所述连接端子面对所述金属布线层且不与所述树脂层重叠;及
电镀层,其通过电镀从所述金属布线层的曝露表面的整个区域生长,并填充在所述金属布线层和所述连接端子之间面对的间隙中,所述电镀层使所述金属布线层和所述连接端子相互电连接,其中,所述金属布线层在电镀期间充当晶种金属,所述间隙是由朝着所述基板按压所述器件的情况下的所述金属布线层与所述连接端子之间的被以预定温度加热的所述树脂层的树脂确定的,且是通过在形成所述电镀层之前移除所述金属布线层与所述连接端子之间的所述树脂形成的。
11.如权利要求10所述的电子装置,其中,所述树脂层是光固化树脂。
12.如权利要求11所述的电子装置,其中,所述树脂层被选择性地固化,由此在所述树脂层的不与所述器件重叠的区域中形成光固化部分。
13.如权利要求12所述的电子装置,其中,所述光固化部分在所述器件周围延伸。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201610479177.3A CN105977232B (zh) | 2010-04-28 | 2011-04-20 | 在基板中安装器件的方法、安装有器件的基板结构和电子装置 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010-103142 | 2010-04-28 | ||
JP2010103142A JP5533199B2 (ja) | 2010-04-28 | 2010-04-28 | 素子の基板実装方法、および、その基板実装構造 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201610479177.3A Division CN105977232B (zh) | 2010-04-28 | 2011-04-20 | 在基板中安装器件的方法、安装有器件的基板结构和电子装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN102237478A CN102237478A (zh) | 2011-11-09 |
CN102237478B true CN102237478B (zh) | 2016-08-03 |
Family
ID=44857378
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201610479177.3A Active CN105977232B (zh) | 2010-04-28 | 2011-04-20 | 在基板中安装器件的方法、安装有器件的基板结构和电子装置 |
CN201110100274.4A Active CN102237478B (zh) | 2010-04-28 | 2011-04-20 | 在基板中安装器件的方法、安装有器件的基板结构和电子装置 |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201610479177.3A Active CN105977232B (zh) | 2010-04-28 | 2011-04-20 | 在基板中安装器件的方法、安装有器件的基板结构和电子装置 |
Country Status (5)
Country | Link |
---|---|
US (1) | US9119332B2 (zh) |
JP (1) | JP5533199B2 (zh) |
KR (1) | KR101839144B1 (zh) |
CN (2) | CN105977232B (zh) |
TW (1) | TWI470843B (zh) |
Families Citing this family (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014013818A (ja) | 2012-07-04 | 2014-01-23 | Sony Corp | デバイスおよび電子装置 |
WO2015053356A1 (ja) * | 2013-10-09 | 2015-04-16 | 学校法人早稲田大学 | 電極接続方法及び電極接続構造 |
JP6152816B2 (ja) * | 2014-03-26 | 2017-06-28 | ソニー株式会社 | 半導体デバイス、表示パネル、表示装置、電子装置、および、半導体デバイスの製造方法 |
GB2524791B (en) | 2014-04-02 | 2018-10-03 | At & S Austria Tech & Systemtechnik Ag | Placement of component in circuit board intermediate product by flowable adhesive layer on carrier substrate |
JP6328497B2 (ja) | 2014-06-17 | 2018-05-23 | ソニーセミコンダクタソリューションズ株式会社 | 半導体発光素子、パッケージ素子、および発光パネル装置 |
TWI814461B (zh) * | 2014-06-18 | 2023-09-01 | 愛爾蘭商艾克斯展示公司技術有限公司 | 微組裝發光二極體顯示器及照明元件 |
US10236279B2 (en) | 2014-10-31 | 2019-03-19 | eLux, Inc. | Emissive display with light management system |
US10535640B2 (en) | 2014-10-31 | 2020-01-14 | eLux Inc. | System and method for the fluidic assembly of micro-LEDs utilizing negative pressure |
US10381335B2 (en) | 2014-10-31 | 2019-08-13 | ehux, Inc. | Hybrid display using inorganic micro light emitting diodes (uLEDs) and organic LEDs (OLEDs) |
US9825202B2 (en) | 2014-10-31 | 2017-11-21 | eLux, Inc. | Display with surface mount emissive elements |
US10381332B2 (en) | 2014-10-31 | 2019-08-13 | eLux Inc. | Fabrication method for emissive display with light management system |
US10520769B2 (en) | 2014-10-31 | 2019-12-31 | eLux, Inc. | Emissive display with printed light modification structures |
US10543486B2 (en) | 2014-10-31 | 2020-01-28 | eLux Inc. | Microperturbation assembly system and method |
US10242977B2 (en) | 2014-10-31 | 2019-03-26 | eLux, Inc. | Fluid-suspended microcomponent harvest, distribution, and reclamation |
US10319878B2 (en) | 2014-10-31 | 2019-06-11 | eLux, Inc. | Stratified quantum dot phosphor structure |
US10446728B2 (en) | 2014-10-31 | 2019-10-15 | eLux, Inc. | Pick-and remove system and method for emissive display repair |
US10418527B2 (en) | 2014-10-31 | 2019-09-17 | eLux, Inc. | System and method for the fluidic assembly of emissive displays |
JP6786781B2 (ja) * | 2015-09-25 | 2020-11-18 | 日亜化学工業株式会社 | 発光装置の製造方法 |
JP2017183458A (ja) | 2016-03-30 | 2017-10-05 | ソニー株式会社 | 発光素子組立体及びその製造方法、並びに、表示装置 |
CN108307591A (zh) * | 2017-01-13 | 2018-07-20 | 奥特斯奥地利科技与系统技术有限公司 | 通过在安装于部件承载件材料之前用附着物覆盖部件制造的部件承载件 |
KR102605339B1 (ko) * | 2018-07-18 | 2023-11-27 | 삼성디스플레이 주식회사 | 표시 장치 및 표시 장치 제조 방법 |
KR102116393B1 (ko) * | 2019-02-27 | 2020-05-28 | (주) 글로우원 | 양면 전극을 구비한 투명 led 디스플레이 |
CN114746988A (zh) * | 2019-12-04 | 2022-07-12 | 3M创新有限公司 | 包括微图案并使用部分固化以粘附管芯的电路 |
CN114902435A (zh) * | 2019-12-24 | 2022-08-12 | 日亚化学工业株式会社 | 发光装置的制造方法和发光装置 |
TWI738433B (zh) * | 2020-01-09 | 2021-09-01 | 致伸科技股份有限公司 | 光源模組以及具有光源模組的電子裝置 |
JP7007607B2 (ja) * | 2020-04-16 | 2022-01-24 | 日亜化学工業株式会社 | 発光装置の製造方法 |
WO2022054943A1 (ja) | 2020-09-14 | 2022-03-17 | Agc株式会社 | Led素子用基板および画像表示装置 |
JP7398036B2 (ja) | 2021-06-23 | 2023-12-14 | 日亜化学工業株式会社 | 発光モジュール及びその製造方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5071787A (en) * | 1989-03-14 | 1991-12-10 | Kabushiki Kaisha Toshiba | Semiconductor device utilizing a face-down bonding and a method for manufacturing the same |
CN1441613A (zh) * | 2002-02-26 | 2003-09-10 | 京瓷株式会社 | 高频组件 |
US6981317B1 (en) * | 1996-12-27 | 2006-01-03 | Matsushita Electric Industrial Co., Ltd. | Method and device for mounting electronic component on circuit board |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55156482U (zh) * | 1979-04-26 | 1980-11-11 | ||
US5151776A (en) * | 1989-03-28 | 1992-09-29 | General Electric Company | Die attachment method for use in high density interconnected assemblies |
US5089440A (en) * | 1990-03-14 | 1992-02-18 | International Business Machines Corporation | Solder interconnection structure and process for making |
DE4126913A1 (de) * | 1991-08-14 | 1993-02-18 | Siemens Ag | Verfahren zum beloten und montieren von leiterplatten mit bauelementen |
EP0591862B1 (en) * | 1992-10-02 | 1999-05-26 | Matsushita Electric Industrial Co., Ltd. | A semiconductor device, an image sensor device, and methods for producing the same |
JP3297177B2 (ja) * | 1993-12-22 | 2002-07-02 | 株式会社東芝 | 半導体装置の製造方法 |
JP2561039B2 (ja) * | 1994-11-22 | 1996-12-04 | 日本電気株式会社 | 半導体チップおよび回路基板の接続方法 |
JPH0917913A (ja) * | 1995-06-29 | 1997-01-17 | Toshiba Corp | 電子回路装置 |
JP2806348B2 (ja) * | 1996-03-08 | 1998-09-30 | 日本電気株式会社 | 半導体素子の実装構造及びその製造方法 |
JP3685585B2 (ja) * | 1996-08-20 | 2005-08-17 | 三星電子株式会社 | 半導体のパッケージ構造 |
JP3702788B2 (ja) * | 1998-07-01 | 2005-10-05 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
US6445589B2 (en) * | 1999-07-29 | 2002-09-03 | Delphi Technologies, Inc. | Method of extending life expectancy of surface mount components |
DE10164494B9 (de) * | 2001-12-28 | 2014-08-21 | Epcos Ag | Verkapseltes Bauelement mit geringer Bauhöhe sowie Verfahren zur Herstellung |
JP2004304161A (ja) * | 2003-03-14 | 2004-10-28 | Sony Corp | 発光素子、発光装置、画像表示装置、発光素子の製造方法及び画像表示装置の製造方法 |
TWI245597B (en) * | 2003-06-30 | 2005-12-11 | Siliconware Precision Industries Co Ltd | Printed circuit boards and method for fabricating the same |
JP2005311109A (ja) * | 2004-04-22 | 2005-11-04 | Seiko Epson Corp | 光デバイスの実装方法及び光モジュール |
TWI243462B (en) * | 2004-05-14 | 2005-11-11 | Advanced Semiconductor Eng | Semiconductor package including passive component |
TWI243440B (en) * | 2004-09-07 | 2005-11-11 | Siliconware Precision Industries Co Ltd | Nickel/gold pad structure of semiconductor package and fabrication method thereof |
JP4356581B2 (ja) * | 2004-10-12 | 2009-11-04 | パナソニック株式会社 | 電子部品実装方法 |
JP2008124376A (ja) * | 2006-11-15 | 2008-05-29 | Canon Inc | 素子基板の接続方法 |
US8318595B2 (en) * | 2009-11-24 | 2012-11-27 | The United States Of America As Represented By The Secretary Of The Army | Self-assembled electrical contacts |
-
2010
- 2010-04-28 JP JP2010103142A patent/JP5533199B2/ja active Active
-
2011
- 2011-04-11 US US13/084,252 patent/US9119332B2/en active Active
- 2011-04-19 TW TW100113577A patent/TWI470843B/zh active
- 2011-04-20 KR KR1020110036639A patent/KR101839144B1/ko active IP Right Grant
- 2011-04-20 CN CN201610479177.3A patent/CN105977232B/zh active Active
- 2011-04-20 CN CN201110100274.4A patent/CN102237478B/zh active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5071787A (en) * | 1989-03-14 | 1991-12-10 | Kabushiki Kaisha Toshiba | Semiconductor device utilizing a face-down bonding and a method for manufacturing the same |
US6981317B1 (en) * | 1996-12-27 | 2006-01-03 | Matsushita Electric Industrial Co., Ltd. | Method and device for mounting electronic component on circuit board |
CN1441613A (zh) * | 2002-02-26 | 2003-09-10 | 京瓷株式会社 | 高频组件 |
Also Published As
Publication number | Publication date |
---|---|
US9119332B2 (en) | 2015-08-25 |
JP2011233733A (ja) | 2011-11-17 |
TW201212304A (en) | 2012-03-16 |
US20110266039A1 (en) | 2011-11-03 |
TWI470843B (zh) | 2015-01-21 |
KR20110120218A (ko) | 2011-11-03 |
JP5533199B2 (ja) | 2014-06-25 |
CN105977232B (zh) | 2019-05-10 |
CN102237478A (zh) | 2011-11-09 |
CN105977232A (zh) | 2016-09-28 |
KR101839144B1 (ko) | 2018-03-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN102237478B (zh) | 在基板中安装器件的方法、安装有器件的基板结构和电子装置 | |
CN108987412B (zh) | 显示设备及其形成方法 | |
US11282820B2 (en) | Display device and method for manufacturing the same | |
US10886257B2 (en) | Micro LED display device and method for manufacturing same | |
EP3422827B1 (en) | Display device and method for fabricating the same | |
US7683539B2 (en) | Light emitting device package and method for manufacturing the same | |
TW202209714A (zh) | 發光顯示單元及顯示裝置 | |
CN110429097B (zh) | 一种显示面板、显示装置和显示面板的制备方法 | |
CN101859730A (zh) | 半导体发光器件、其组件制造方法以及电子设备 | |
EP3726576B1 (en) | Method for forming a display device | |
CN111149225A (zh) | 一种tft结构、发光件、显示器及其制备方法 | |
US20220384698A1 (en) | Method of manufacturing light emitting device and light emitting device | |
JP2008118161A (ja) | 素子転写方法 | |
CN217903134U (zh) | 显示面板及电子设备 | |
CN114975504A (zh) | 微发光二极管显示装置的制备方法及电子设备 | |
KR20110132729A (ko) | Led를 구비한 백라이트 유닛 및 그 제조방법 | |
WO2021196008A1 (zh) | 无机发光二极管芯片及其制造方法 | |
JP2012064676A (ja) | 照明装置 | |
CN116565105B (zh) | 发光芯片的转移方法、发光结构和显示面板 | |
WO2023137713A1 (zh) | 一种微型led芯片检测结构及其制备方法 | |
US20240072218A1 (en) | Display device and method for fabricating the same | |
CN116598411A (zh) | 一种Micro-LED器件及其制备方法 | |
CN117832356A (zh) | 发光二极管芯片、显示基板及其制备方法和显示装置 | |
CN116190526A (zh) | 发光元件、发光元件及显示面板的制备方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant |