TWI456754B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TWI456754B
TWI456754B TW101105749A TW101105749A TWI456754B TW I456754 B TWI456754 B TW I456754B TW 101105749 A TW101105749 A TW 101105749A TW 101105749 A TW101105749 A TW 101105749A TW I456754 B TWI456754 B TW I456754B
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substrate
isolation elements
semiconductor device
fin
disposed
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TW201301508A (zh
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Dal Mark Van
Gerben Doornbos
Georgios Vellianitis
Tsung Lin Lee
Feng Yuan
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Taiwan Semiconductor Mfg
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025Channel region of field-effect devices
    • H01L29/1029Channel region of field-effect devices of field-effect transistors
    • H01L29/1033Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
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    • H01ELECTRIC ELEMENTS
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/785Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • HELECTRICITY
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    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Recrystallisation Techniques (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Claims (10)

  1. 一種半導體裝置,包括:一基板,包括至少兩個隔離元件設於該基板之一表面上;一鰭基板,設置於該至少兩個隔離元件之間及上方,其中該鰭基板自該基板之該表面延伸至高於該至少兩個隔離元件之高度;及一磊晶層,設置於該鰭基板暴露的部分上方。
  2. 如申請專利範圍第1項所述之半導體裝置,其中該鰭基板或該磊晶層具有一單軸壓縮應變,形成一P型金氧半導體裝置、或其中該鰭基板或該磊晶層具有一單軸抗拉應變,形成一N型金氧半導體裝置。
  3. 如申請專利範圍第1項所述之半導體裝置,其中該鰭基板包括一第一部分及一第二部分,其中該第一部分自該基板之該表面延伸至低於該至少兩個隔離元件之高度,該第二部分設於該第一部分上且延伸至一大抵全部位於該至少兩個隔離元件上方的垂直高度。
  4. 如申請專利範圍第1項所述之半導體裝置,其中該磊晶層設置於一位於該至少兩個隔離元件的蝕刻區上方及該鰭基板的一頂表面及側壁上方的垂直高度。
  5. 如申請專利範圍第1項所述之半導體裝置,其中該磊晶層為一包括矽的鈍化層。
  6. 一種半導體裝置,包括:一基板,包括至少兩個隔離元件設於該基板之一表面上; 一基板緩衝區,設置於該至少兩個隔離元件之間;一鰭基板,設置於該基板緩衝區上方、該至少兩個隔離元件之間,且自該基板之該表面延伸至一大抵完全位於該至少兩個隔離元件上方的垂直高度;及一源/汲極磊晶層,設置於該鰭基板的一頂表面及側壁上方。
  7. 如申請專利範圍第6項所述之半導體裝置,其中該鰭基板為一應變矽鍺通道層,其中該應變矽鍺通道層包括約25-50%的鍺,且具有一約100-200奈米的長度、一約10-20奈米的寬度、及一約10-40奈米的厚度。
  8. 一種半導體裝置的製造方法,該方法包括:提供一基板,其包括至少兩個隔離元件設於該基板之一表面上;形成一鰭基板於該至少兩個隔離元件之間、及一該至少兩個隔離元件上方的垂直高度,其中該鰭基板自該基板之該表面延伸至高於該至少兩個隔離元件之高度;及形成一磊晶層於該鰭基板暴露的部分上方。
  9. 如申請專利範圍第8項所述之半導體裝置的製造方法,其中沉積該鰭基板成為一應變矽鍺通道層,其中該應變矽鍺通道層包括約25-50%的鍺,且具有一約100-200奈米的長度、一約10-20奈米的寬度、及一約10-40奈米的厚度。
  10. 如申請專利範圍第8項所述之半導體裝置的製造方法,其中沉積該鰭基板或該磊晶層使其具有一單軸壓 縮應變,形成一P型金氧半導體裝置、或其中沉積該鰭基板或該磊晶層使其具有一單軸抗拉應變,形成一N型金氧半導體裝置。
TW101105749A 2011-06-16 2012-02-22 半導體裝置及其製造方法 TWI456754B (zh)

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US13/161,649 US9761666B2 (en) 2011-06-16 2011-06-16 Strained channel field effect transistor

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9614087B1 (en) 2016-05-17 2017-04-04 International Business Machines Corporation Strained vertical field-effect transistor (FET) and method of forming the same

Families Citing this family (131)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103107192B (zh) * 2011-11-10 2016-05-18 中芯国际集成电路制造(北京)有限公司 半导体装置及其制造方法
KR101805634B1 (ko) * 2011-11-15 2017-12-08 삼성전자 주식회사 Ⅲ-ⅴ족 배리어를 포함하는 반도체 소자 및 그 제조방법
WO2013095474A1 (en) * 2011-12-21 2013-06-27 Intel Corporation Methods for forming fins for metal oxide semiconductor device structures
US8659097B2 (en) * 2012-01-16 2014-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Control fin heights in FinFET structures
US9281378B2 (en) 2012-01-24 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Fin recess last process for FinFET fabrication
US9171925B2 (en) 2012-01-24 2015-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-gate devices with replaced-channels and methods for forming the same
US9466696B2 (en) 2012-01-24 2016-10-11 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs and methods for forming the same
KR101835655B1 (ko) * 2012-03-06 2018-03-07 삼성전자주식회사 핀 전계 효과 트랜지스터 및 이의 제조 방법
JP6326379B2 (ja) 2012-03-08 2018-05-16 ディー−ウェイブ システムズ,インコーポレイテッド 超伝導集積回路の製作のためのシステムおよび方法
US8836016B2 (en) 2012-03-08 2014-09-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structures and methods with high mobility and high energy bandgap materials
US8987835B2 (en) 2012-03-27 2015-03-24 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET with a buried semiconductor material between two fins
US8802535B2 (en) * 2012-05-02 2014-08-12 International Business Machines Corporation Doped core trigate FET structure and method
EP2682983B1 (en) * 2012-07-03 2016-08-31 Imec CMOS device comprising silicon and germanium and method for manufacturing thereof
US8629420B1 (en) * 2012-07-03 2014-01-14 Intel Mobile Communications GmbH Drain extended MOS device for bulk FinFET technology
US9142400B1 (en) 2012-07-17 2015-09-22 Stc.Unm Method of making a heteroepitaxial layer on a seed area
US8847281B2 (en) * 2012-07-27 2014-09-30 Intel Corporation High mobility strained channels for fin-based transistors
CN103579004B (zh) * 2012-08-10 2016-05-11 中国科学院微电子研究所 FinFET及其制造方法
US20140054646A1 (en) * 2012-08-24 2014-02-27 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and Method for Multiple Gate Transistors
US20140054705A1 (en) * 2012-08-27 2014-02-27 International Business Machines Corporation Silicon germanium channel with silicon buffer regions for fin field effect transistor device
US9564367B2 (en) * 2012-09-13 2017-02-07 Globalfoundries Inc. Methods of forming different FinFET devices with different threshold voltages and integrated circuit products containing such devices
US8765563B2 (en) * 2012-09-28 2014-07-01 Intel Corporation Trench confined epitaxially grown device layer(s)
US8497177B1 (en) * 2012-10-04 2013-07-30 Taiwan Semiconductor Manufacturing Company, Ltd. Method of making a FinFET device
US9349837B2 (en) 2012-11-09 2016-05-24 Taiwan Semiconductor Manufacturing Company, Ltd. Recessing STI to increase Fin height in Fin-first process
US9443962B2 (en) 2012-11-09 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. Recessing STI to increase fin height in fin-first process
US9299809B2 (en) * 2012-12-17 2016-03-29 Globalfoundries Inc. Methods of forming fins for a FinFET device wherein the fins have a high germanium content
US9147682B2 (en) 2013-01-14 2015-09-29 Taiwan Semiconductor Manufacturing Company, Ltd. Fin spacer protected source and drain regions in FinFETs
US9306069B2 (en) 2013-09-11 2016-04-05 Taiwan Semiconductor Manufacturing Company, Ltd. Isolation structure of fin field effect transistor
US9202917B2 (en) 2013-07-29 2015-12-01 Taiwan Semiconductor Manufacturing Co., Ltd. Buried SiGe oxide FinFET scheme for device enhancement
KR101401274B1 (ko) * 2013-02-26 2014-05-29 연세대학교 산학협력단 Ge 및/또는 III-V족 화합물 반도체를 이용한 FinFET 및 그 제조방법
US9385234B2 (en) * 2013-02-27 2016-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs with strained well regions
US9087902B2 (en) 2013-02-27 2015-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs with strained well regions
US9159824B2 (en) 2013-02-27 2015-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs with strained well regions
US9209066B2 (en) * 2013-03-01 2015-12-08 Taiwan Semiconductor Manufacturing Company, Ltd. Isolation structure of semiconductor device
CN104037083B (zh) * 2013-03-04 2017-02-22 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法
US9385198B2 (en) * 2013-03-12 2016-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. Heterostructures for semiconductor devices and methods of forming the same
US8829606B1 (en) 2013-03-13 2014-09-09 Taiwan Semiconductor Manufacturing Company, Ltd. Ditches near semiconductor fins and methods for forming the same
JP6312789B2 (ja) * 2013-03-14 2018-04-18 インテル・コーポレーション ナノワイヤトランジスタのリーク低減構造
US8859379B2 (en) * 2013-03-15 2014-10-14 International Business Machines Corporation Stress enhanced finFET devices
KR102038486B1 (ko) * 2013-04-09 2019-10-30 삼성전자 주식회사 반도체 장치 및 그 제조 방법
KR102021765B1 (ko) * 2013-06-17 2019-09-17 삼성전자 주식회사 반도체 장치
CN104241360B (zh) * 2013-06-24 2019-07-23 联华电子股份有限公司 半导体装置及其制作方法
DE112013007058B4 (de) * 2013-06-28 2023-08-24 Tahoe Research, Ltd. Herstellung einer defektfreien finnenbasierten Vorrichtung in einem lateralen Epitaxieüberwachsungsgebiet
US9496397B2 (en) * 2013-08-20 2016-11-15 Taiwan Semiconductor Manufacturing Co., Ltd. FinFet device with channel epitaxial region
EP2849219A1 (en) * 2013-09-11 2015-03-18 IMEC vzw Method for manufacturing transistors and associated substrate
CN105793967B (zh) * 2013-09-27 2019-03-12 英特尔公司 具有最大顺从性和自由表面弛豫的Ge和III-V族沟道半导体器件
WO2015047341A1 (en) 2013-09-27 2015-04-02 Intel Corporation Non-planar semiconductor devices having multi-layered compliant substrates
US20150097270A1 (en) * 2013-10-07 2015-04-09 International Business Machines Corporation Finfet with relaxed silicon-germanium fins
US9287262B2 (en) 2013-10-10 2016-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Passivated and faceted for fin field effect transistor
US9520502B2 (en) * 2013-10-15 2016-12-13 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs having epitaxial capping layer on fin and methods for forming the same
US9159833B2 (en) 2013-11-26 2015-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. Fin structure of semiconductor device
US20150162435A1 (en) * 2013-12-09 2015-06-11 Globalfoundries Inc. Asymmetric channel growth of a cladding layer over fins of a field effect transistor (finfet) device
CN105723500B (zh) * 2013-12-16 2019-11-12 英特尔公司 不具有弛豫衬底的nmos和pmos应变器件
WO2015094164A1 (en) * 2013-12-16 2015-06-25 Intel Corporation Dual strained cladding layers for semiconductor devices
US9159552B2 (en) 2013-12-27 2015-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a germanium-containing FinFET
US9324717B2 (en) 2013-12-28 2016-04-26 Texas Instruments Incorporated High mobility transistors
US9496262B2 (en) * 2013-12-28 2016-11-15 Texas Instruments Incorporated High mobility transistors
US9590090B2 (en) 2014-01-08 2017-03-07 Taiwan Semiconductor Manufacturing Company Limited Method of forming channel of gate structure
US9373706B2 (en) 2014-01-24 2016-06-21 Samsung Electronics Co., Ltd. Methods of forming semiconductor devices, including forming a semiconductor material on a fin, and related semiconductor devices
US9246005B2 (en) 2014-02-12 2016-01-26 International Business Machines Corporation Stressed channel bulk fin field effect transistor
US9634224B2 (en) * 2014-02-14 2017-04-25 D-Wave Systems Inc. Systems and methods for fabrication of superconducting circuits
US9660080B2 (en) * 2014-02-28 2017-05-23 Stmicroelectronics, Inc. Multi-layer strained channel FinFET
CN105336587B (zh) * 2014-06-17 2018-05-15 中芯国际集成电路制造(北京)有限公司 半导体器件及其制造方法
US9780216B2 (en) * 2014-03-19 2017-10-03 Taiwan Semiconductor Manufacturing Company, Ltd. Combination FinFET and methods of forming same
US9343303B2 (en) 2014-03-20 2016-05-17 Samsung Electronics Co., Ltd. Methods of forming low-defect strain-relaxed layers on lattice-mismatched substrates and related semiconductor structures and devices
MY186544A (en) 2014-03-24 2021-07-26 Intel Corp Fin sculpting and cladding during replacement gate process for transistor channel applications
CN106030812B (zh) * 2014-03-27 2019-09-24 英特尔公司 锗锡沟道晶体管
US10153372B2 (en) * 2014-03-27 2018-12-11 Intel Corporation High mobility strained channels for fin-based NMOS transistors
US9653461B2 (en) 2014-03-28 2017-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs with low source/drain contact resistance
US9698240B2 (en) 2014-03-31 2017-07-04 Taiwan Semiconductor Manufacturing Company Limited Semiconductor device and formation thereof
US9443963B2 (en) 2014-04-07 2016-09-13 International Business Machines Corporation SiGe FinFET with improved junction doping control
US9450096B2 (en) 2014-04-10 2016-09-20 Taiwan Semiconductor Manufacturing Company Limited Semiconductor device and formation thereof
US9443769B2 (en) 2014-04-21 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. Wrap-around contact
US9721955B2 (en) * 2014-04-25 2017-08-01 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for SRAM FinFET device having an oxide feature
US10700170B2 (en) 2014-04-29 2020-06-30 Globalfoundries Inc. Multiple fin finFET with low-resistance gate structure
US9230992B2 (en) * 2014-04-30 2016-01-05 International Business Machines Corporation Semiconductor device including gate channel having adjusted threshold voltage
US9312389B2 (en) * 2014-05-23 2016-04-12 Broadcom Corporation FinFET with undoped body bulk
US9196479B1 (en) 2014-07-03 2015-11-24 International Business Machines Corporation Method of co-integration of strained silicon and strained germanium in semiconductor devices including fin structures
EP2978016B1 (en) * 2014-07-25 2018-06-13 IMEC vzw A method for providing an nMOS device and a pMOS device on a silicon substrate and silicon substrate comprising an nMOS device and a pMOS device
US9293588B1 (en) 2014-08-28 2016-03-22 International Business Machines Corporation FinFET with a silicon germanium alloy channel and method of fabrication thereof
US9219150B1 (en) * 2014-09-18 2015-12-22 Soitec Method for fabricating semiconductor structures including fin structures with different strain states, and related semiconductor structures
US9564518B2 (en) * 2014-09-24 2017-02-07 Qualcomm Incorporated Method and apparatus for source-drain junction formation in a FinFET with in-situ doping
US9337196B2 (en) * 2014-09-29 2016-05-10 International Business Machines Corporation III-V FinFET CMOS with III-V and germanium-containing channel closely spaced
US9543438B2 (en) * 2014-10-15 2017-01-10 Taiwan Semiconductor Manufacturing Company, Ltd. Contact resistance reduction technique
KR20160045528A (ko) * 2014-10-17 2016-04-27 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 핀 전계 효과 트랜지스터 (FinFET) 디바이스 및 이의 형성 방법
US10164108B2 (en) * 2014-10-17 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor (FinFET) device and method for forming the same
US9362182B2 (en) 2014-11-06 2016-06-07 International Business Machines Corporation Forming strained fins of different material on a substrate
US9362405B1 (en) 2014-12-04 2016-06-07 Globalfoundries Inc. Channel cladding last process flow for forming a channel region on a FinFET device
US9953836B2 (en) 2015-01-28 2018-04-24 Taiwan Semiconductor Manufacturing Co., Ltd. Barrier layer above anti-punch through (APT) implant region to improve mobility of channel region of fin field effect transistor (FinFET) device structure
US9514997B2 (en) * 2015-03-25 2016-12-06 International Business Machines Corporation Silicon-germanium FinFET device with controlled junction
KR102351659B1 (ko) * 2015-04-03 2022-01-17 삼성전자주식회사 전계 효과 트랜지스터를 포함하는 반도체 소자
US9954107B2 (en) * 2015-05-05 2018-04-24 International Business Machines Corporation Strained FinFET source drain isolation
EP3093881B1 (en) * 2015-05-13 2020-11-11 IMEC vzw Method for manufacturing a cmos device
US10461193B2 (en) 2015-05-27 2019-10-29 Intel Corporation Apparatus and methods to create a buffer which extends into a gated region of a transistor
US9818647B2 (en) * 2015-06-03 2017-11-14 International Business Machines Corporation Germanium dual-fin field effect transistor
US9754941B2 (en) 2015-06-03 2017-09-05 Globalfoundries Inc. Method and structure to form tensile strained SiGe fins and compressive strained SiGe fins on a same substrate
US10269968B2 (en) * 2015-06-03 2019-04-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device including fin structures and manufacturing method thereof
US9805991B2 (en) * 2015-08-20 2017-10-31 International Business Machines Corporation Strained finFET device fabrication
US9660025B2 (en) * 2015-08-31 2017-05-23 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of semiconductor device structure
US9548386B1 (en) 2015-08-31 2017-01-17 International Business Machines Corporation Structure and method for compressively strained silicon germanium fins for pFET devices and tensily strained silicon fins for nFET devices
CN108028276B (zh) * 2015-09-25 2022-04-26 英特尔公司 晶体管沟道区域界面的钝化
CN106611787A (zh) * 2015-10-26 2017-05-03 联华电子股份有限公司 半导体结构及其制作方法
US9449882B1 (en) * 2015-10-29 2016-09-20 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US9627275B1 (en) 2015-10-30 2017-04-18 Taiwan Semiconductor Manufacturing Company Ltd. Hybrid semiconductor structure on a common substrate
US10115807B2 (en) * 2015-11-18 2018-10-30 Globalfoundries Inc. Method, apparatus and system for improved performance using tall fins in finFET devices
US11038057B2 (en) * 2015-12-07 2021-06-15 Institute of Microelectronics, Chinese Academy of Sciences Semiconductor device with high-quality epitaxial layer and method of manufacturing the same
US9496260B1 (en) * 2015-12-09 2016-11-15 International Business Machines Corporation Tall strained high percentage silicon germanium fins for CMOS
US10483353B2 (en) * 2015-12-24 2019-11-19 Intel Corporation Transistor including tensile-strained germanium channel
US10796924B2 (en) * 2016-02-18 2020-10-06 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof by forming thin uniform silicide on epitaxial source/drain structure
JP6855848B2 (ja) * 2016-03-18 2021-04-07 株式会社リコー 電界効果型トランジスタの製造方法、揮発性半導体メモリ素子の製造方法、不揮発性半導体メモリ素子の製造方法、表示素子の製造方法、画像表示装置の製造方法、システムの製造方法
TWI699885B (zh) 2016-03-22 2020-07-21 聯華電子股份有限公司 半導體結構與其製作方法
US10068920B2 (en) * 2016-04-14 2018-09-04 Globalfoundries Inc. Silicon germanium fins on insulator formed by lateral recrystallization
US10181526B2 (en) 2016-06-02 2019-01-15 Samsung Electronics Co., Ltd. Field effect transistor including multiple aspect ratio trapping structures
WO2018009163A1 (en) * 2016-07-02 2018-01-11 Intel Corporation Germanium transistor structure with underlap tip to reduce gate induced barrier lowering/short channel effect while minimizing impact on drive current
US11757004B2 (en) 2016-09-30 2023-09-12 Intel Corporation Transistors including source/drain employing double-charge dopants
US9947789B1 (en) * 2016-10-17 2018-04-17 Globalfoundries Inc. Vertical transistors stressed from various directions
US10381348B2 (en) 2017-01-10 2019-08-13 International Business Machines Corporation Structure and method for equal substrate to channel height between N and P fin-FETs
EP3577700B1 (en) 2017-02-01 2022-03-30 D-Wave Systems Inc. Systems and methods for fabrication of superconducting integrated circuits
CN108630604B (zh) * 2017-03-21 2020-12-18 中芯国际集成电路制造(上海)有限公司 半导体装置及其制造方法
TWI745365B (zh) * 2017-03-23 2021-11-11 聯華電子股份有限公司 半導體元件及其製作方法
WO2019005106A1 (en) * 2017-06-30 2019-01-03 Intel Corporation PROHIBITED WIDE BAND CHANNEL TRANSISTOR AND SOURCE / BAND DRAIN PROHIBITED NARROW
US10497577B2 (en) * 2017-08-31 2019-12-03 Taiwan Semiconductor Manufacturing Company, Ltd. Fin field-effect transistor device and method
US10403551B2 (en) * 2017-11-08 2019-09-03 Taiwan Semiconductor Manufacturing Co., Ltd. Source/drain features with an etch stop layer
US10629749B2 (en) 2017-11-30 2020-04-21 Taiwan Semiconductor Manufacturing Co., Ltd. Method of treating interfacial layer on silicon germanium
US10727328B2 (en) * 2017-11-30 2020-07-28 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
CN110571195B (zh) * 2018-06-05 2021-12-21 中芯国际集成电路制造(上海)有限公司 一种sram及其制造方法和电子装置
US10879131B2 (en) * 2018-07-31 2020-12-29 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method for the same
US20200152851A1 (en) 2018-11-13 2020-05-14 D-Wave Systems Inc. Systems and methods for fabricating superconducting integrated circuits
WO2020168097A1 (en) 2019-02-15 2020-08-20 D-Wave Systems Inc. Kinetic inductance for couplers and compact qubits
US20220192157A1 (en) * 2019-04-16 2022-06-23 Ezydog LLC Checking harness for pets
CN111509048A (zh) * 2020-04-28 2020-08-07 上海华力集成电路制造有限公司 N型鳍式晶体管及其制造方法
CN112530864B (zh) * 2020-11-30 2022-11-04 厦门天马微电子有限公司 可拉伸显示面板的制备方法、可拉伸显示面板及显示装置

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050224800A1 (en) * 2004-03-31 2005-10-13 Nick Lindert Bulk non-planar transistor having strained enhanced mobility and methods of fabrication

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4044276B2 (ja) * 2000-09-28 2008-02-06 株式会社東芝 半導体装置及びその製造方法
US6703271B2 (en) 2001-11-30 2004-03-09 Taiwan Semiconductor Manufacturing Company Complementary metal oxide semiconductor transistor technology using selective epitaxy of a strained silicon germanium layer
KR100458288B1 (ko) * 2002-01-30 2004-11-26 한국과학기술원 이중-게이트 FinFET 소자 및 그 제조방법
US6955952B2 (en) 2003-03-07 2005-10-18 Taiwan Semiconductor Manufacturing Company, Ltd. Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement
US7045401B2 (en) * 2003-06-23 2006-05-16 Sharp Laboratories Of America, Inc. Strained silicon finFET device
US6921982B2 (en) * 2003-07-21 2005-07-26 International Business Machines Corporation FET channel having a strained lattice structure along multiple surfaces
EP1519420A2 (en) * 2003-09-25 2005-03-30 Interuniversitaire Microelectronica Centrum vzw ( IMEC) Multiple gate semiconductor device and method for forming same
US7172943B2 (en) * 2003-08-13 2007-02-06 Taiwan Semiconductor Manufacturing Company, Ltd. Multiple-gate transistors formed on bulk substrates
US7385247B2 (en) * 2004-01-17 2008-06-10 Samsung Electronics Co., Ltd. At least penta-sided-channel type of FinFET transistor
US7244958B2 (en) 2004-06-24 2007-07-17 International Business Machines Corporation Integration of strained Ge into advanced CMOS technology
KR100674914B1 (ko) * 2004-09-25 2007-01-26 삼성전자주식회사 변형된 채널층을 갖는 모스 트랜지스터 및 그 제조방법
US20070090416A1 (en) * 2005-09-28 2007-04-26 Doyle Brian S CMOS devices with a single work function gate electrode and method of fabrication
KR100713924B1 (ko) * 2005-12-23 2007-05-07 주식회사 하이닉스반도체 돌기형 트랜지스터 및 그의 형성방법
US7525160B2 (en) * 2005-12-27 2009-04-28 Intel Corporation Multigate device with recessed strain regions
US7449373B2 (en) * 2006-03-31 2008-11-11 Intel Corporation Method of ion implanting for tri-gate devices
US7781277B2 (en) * 2006-05-12 2010-08-24 Freescale Semiconductor, Inc. Selective uniaxial stress relaxation by layout optimization in strained silicon on insulator integrated circuit
WO2008039495A1 (en) * 2006-09-27 2008-04-03 Amberwave Systems Corporation Tri-gate field-effect transistors formed by aspect ratio trapping
JP4310399B2 (ja) * 2006-12-08 2009-08-05 株式会社東芝 半導体装置及びその製造方法
US8174073B2 (en) * 2007-05-30 2012-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit structures with multiple FinFETs
CN101364545B (zh) * 2007-08-10 2010-12-22 中芯国际集成电路制造(上海)有限公司 应变硅晶体管的锗硅和多晶硅栅极结构
US7674669B2 (en) * 2007-09-07 2010-03-09 Micron Technology, Inc. FIN field effect transistor
JP5159413B2 (ja) * 2008-04-24 2013-03-06 株式会社東芝 半導体装置及びその製造方法
US8338259B2 (en) * 2010-03-30 2012-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with a buried stressor
US8207038B2 (en) * 2010-05-24 2012-06-26 International Business Machines Corporation Stressed Fin-FET devices with low contact resistance

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050224800A1 (en) * 2004-03-31 2005-10-13 Nick Lindert Bulk non-planar transistor having strained enhanced mobility and methods of fabrication

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9614087B1 (en) 2016-05-17 2017-04-04 International Business Machines Corporation Strained vertical field-effect transistor (FET) and method of forming the same

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