TWI424799B - 基板佈局與其形成方法 - Google Patents

基板佈局與其形成方法 Download PDF

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TWI424799B
TWI424799B TW099138293A TW99138293A TWI424799B TW I424799 B TWI424799 B TW I424799B TW 099138293 A TW099138293 A TW 099138293A TW 99138293 A TW99138293 A TW 99138293A TW I424799 B TWI424799 B TW I424799B
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trace
layer
substrate
ground
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TW201146107A (en
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Chin Sung Lin
Li Hua Lin
Yu Yu Lin
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Taiwan Semiconductor Mfg
Global Unichip Corp
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Description

基板佈局與其形成方法
本發明係有關於封裝基板與其製法，且為了達成電源完整性，特別是有關於一種具有可佈線層(routable layer)之封裝基板。
儘管已對積體電路或晶粒進行封裝(packaging)，為了將晶粒電性連接到其他外部元件或構件，一般而言，仍需要將晶粒接合至一外部基板。於各種應用中，類似的基板，例如印刷電路板(printed circuit boards,PCB)，已應用於半導體封裝技術上。
為了使基板上各層之使用效率達到最大化，單一層通常會包括一接地層(ground plane)作為第一電源迴圈(first power loop)與一電源供應線路(power supply trace)作為第二電源迴圈(second power loop)。這些基板可包括多種不同的電源迴圈，亦可包括具有接地層與電源供應線路(power supply traces)的各種組合，位於基板的多層之上。然而，如何將接地層與電源供應線路設置於單一層上卻可能帶來問題，例如電源迴圈的高阻抗(impedance)。
舉例而言，於單一層之第一電源迴圈中，一般的設置可包括一接地層，此接地層大體上圍繞於晶粒欲接合到基板的區域之兩側。一外層可包括球柵陣列(ball grid array,BGA)，此球柵陣列具有電源供應連線(power supply connections)位於基板的外部邊緣，其中介於該些連線與晶粒區域之間的線用於切割開接地層。從這些連線連接到接地層的接觸導通孔(vias)可將電源供應連線耦合到一線路(trace)。於一般的結構中，此線路(trace)將接地層切割成兩等份，並且於接地層所在的兩側圍繞著晶粒區域。因此，此線路(trace)可具有”Y”型結構，其中晶粒位於Y型上方分支(upper branches)之中與之間。因為線路(trace)可切斷回流電流(return current)的直接路徑(direct path)，因而可避免在接地層中的回流電流沿著直接路徑回流回來。換言之，回流電流因而轉向(diverted)，沿著該線路(trace)回流到耦合於晶粒之接觸導通孔(via)中。
於上述之結構中，一般回流電流的轉向(diversion)會增加電源迴圈的阻抗(impedance)。於較高頻率的條件下，阻抗的增加會更加顯著。此外，亦可能造成電源雜訊(power noise)的增加，因而降低晶粒中訊號的真度(fidelity)。因此，需要提出一種基板佈局(substrate layout)與其製法，此種佈局能夠降低或消除上述之缺點。
本發明提供一種基板佈局，包括：一第一電源迴圈(first power loop)之一接地層(ground plane)，位於一基板的一層上；一第一線路軌(first trace rail)，位於該層上且沿著該接地層之一第一外圍延伸，其中該接地層位於該第一線路軌與一晶粒區域之間；以及一第一垂直線路(first perpendicular trace)耦合該第一線路軌，且從該第一線路軌垂直地延伸，其中該第一線路軌與該第一垂直線路組成一第二電源迴圈。
本發明另提供一種基板佈局，包括：一接地層(ground plane)，位於一基板的一層上，其中該接地層為一第一電源迴圈(first power loop)之一部分；一第一線路軌(first trace rail)，係沿著該接地層之一第一外部邊緣(first outer edge)延伸，其中該第一線路軌為一第二電源迴圈之一部分，且該接地層位於該第一線路軌與一晶粒區域之間；以及一第一線路(first trace)耦合該第一線路軌，其中該第二電源迴圈中沒有任何線路沿著垂直且與一回流電流(return current)之直接路徑(direct path)相交叉(intersect)的方向延伸，其中該回流電流係在該接地層中流到一回流電流結構，其中該回流電流結構大體上包含一接觸導通孔(via)、一接觸穿孔(through-via)或上述之組合。
本發明亦提供一種基板佈局之形成方法，包括以下步驟：提供具有一導電材料於其上的一基板，以該導電材料形成一接地層、一第一線路軌與一第一垂直線路，其中該第一線路軌沿著該接地層之一第一外部邊緣延伸，且該第一垂直線路與該第一線路軌耦合並從該第一線路軌垂直地延伸，其中該接地層介於該第一線路軌與該基板之一區域間，其中該區域為後續晶粒所在位置；以及形成一絕緣材料位於該接地層、該第一線路軌與該第一垂直線路之上。
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下：
以下特舉出本發明之實施例，並配合所附圖式作詳細說明。以下實施例的元件和設計係為了簡化所揭露之發明，並非用以限定本發明。
為了電性連接到積體電路或晶粒，下述實施例係有關於包含連線層之基板的特定內容。然而，亦可應用到其他實施例的基板中(例如中介基板(interposer substrate))，這些基板耦合到積體電路或晶粒，。
依據本發明之實施例，第1圖顯示基板的中間層(intermediate layer) 10。中間層(intermediate layer) 10可以是基板中的任意一層。中間層10包含一”電源B(power B)”接地層26。圖中亦顯示晶粒區域32的輪廓，其中晶粒可耦合到基板的外部表面。依圖中所示，接地層26大體上圍繞於晶粒區域32之兩側。沿著晶粒區域32之兩側為接觸導通孔30，當晶粒耦合到基板時，藉由接觸導通孔30使接地層26與晶粒電性耦合。
線路軌(trace rails) 12、14各自沿著接地層26之外部邊緣(exterior edge)延伸，且接地層26介於線路軌12、14與晶粒區域32之間。線路軌(trace rails) 12、14為”電源A(power A)”迴圈的一部分，且提供電源供應(power supply)與參考電壓(reference voltage)。線路軌12沿著接地層26之邊緣以第一方向延伸，而線路軌14沿著接地層26之另一邊緣以第二方向延伸，此第二方向垂直於第一方向。線路軌12、14與接觸導通孔(vias)24電性耦合，其中該接觸導通孔24與位於基板外表面上的球閘陣列(ball grid array,BGA)焊接球電性耦合。BGA焊接球可位於與晶粒相同或不同表面上。
第一、第二、第三、第四垂直線路16、18、20與22分別垂直地從各自的線路軌12、14延伸到接地層26中。垂直線路16、18、20與22為”電源A(power A)”迴圈的另一部分，且其各自使線路軌12、14與接觸導通孔28電性耦合，其中接觸導通孔28與晶粒電性耦合。垂直線路16、18、20與22各自垂直地延伸至最靠近自身線路的晶粒區域32之邊緣。須注意的是，線路軌12、14、垂直線路16、18、20、22皆與接地層26彼此電性隔離，使得線路軌12、14與垂直線路16、18、20、22不會短路(shorted)，亦不會與接地層26直接接觸。
於第1圖的結構中，流進接地層26之回流電流(return current)可更直接地(more directly)流到接觸導通孔30，此接觸導通孔30將回流電流導向晶粒。由於垂直線路16、18、20、22皆從最接近自身的線路軌12或14及/或晶粒區域之一側垂直地延伸，因此，回流電流(return current)的直接路徑(direct path)將不會受到”電源A”迴圈中任何介於中間的線路所截斷(cut off)。另言之，於接地層26中，僅有沿著接地層26之外部邊緣而延伸的線路有可能沿著垂直於回流電流直接路徑的方向延伸，除此之外，再也沒有任何”電源A”線路垂直於回流電流(return current)之直接路徑(direct path)。更精確地說，於此結構中，垂直線路16、18、20、22係沿著平行於(parallel to)回流電流之直接路徑的方向延伸。
在此結構中，因為在”電源A”迴圈中沒有線路會切斷接地層26中回流電流之直接路徑，”電源B”迴圈的阻抗(impedance)可因此降低，”電源A”迴圈的阻抗亦會降低。比起習知結構，可延長第1圖中”電源A”迴圈中的線路，雖然這樣做會增加線路的電阻(resistance)，但發明人了解當考慮此結構的優點時，線路的增長並不會對電源迴圈的阻抗造成不利的影響(adversely effect)。下述其他實施例將會更詳細討論此項觀察結果。
依據本發明之另一實施例，第2圖顯示基板的中間層40。第2圖中顯示一”電源B(power B)”接地層56、一晶粒區域62的輪廓，以及一接觸導通孔60，當晶粒耦合到基板時，接觸導通孔60使接地層56與晶粒電性耦合。如圖中所示，接地層56大體上圍繞於晶粒區域62之兩側。
線路軌(trace rails) 42、44各自沿著接地層56之外部邊緣(exterior edge)延伸，且接地層56介於線路軌42、44與晶粒區域62之間。線路軌(trace rails) 42、44為”電源A(power A)”迴圈的一部分。線路軌43沿著接地層56之邊緣以第一方向延伸，而線路軌44沿著接地層56之另一邊緣以第二方向延伸，此第二方向垂直於第一方向。線路軌42、44與接觸導通孔(vias) 54電性耦合，其中該接觸導通孔54與位於基板外表面上的球閘陣列(ball grid array,BGA)焊接球電性耦合。BGA焊接球可位於與晶粒相同或不同表面上。
類似於第1圖，第一、第二、第三、第四垂直線路46、48、50與52分別垂直地從各自的線路軌42、44延伸到接地層56中。垂直線路46、48、50與52為”電源A(power A)”迴圈的另一部分，且其各自使線路軌42、44與接觸導通孔58電性耦合，其中接觸導通孔58與晶粒電性耦合。垂直線路46、48、50與52各自垂直地延伸至最靠近自身線路的晶粒區域62之邊緣。
依據本發明之另一實施例，第3圖顯示基板的中間層70。第3圖中顯示一”電源B(power B)”接地層86、一晶粒區域92的輪廓，以及一接觸導通孔90，當晶粒耦合到基板時，接觸導通孔90使接地層86與晶粒電性耦合。如圖中所示，接地層86大體上圍繞於晶粒區域92之兩側。
線路軌(trace rails) 72、74各自沿著接地層86之外部邊緣(exterior edge)延伸，且接地層86介於線路軌72、74與晶粒區域92之間。線路軌(trace rails) 72、74為”電源A(power A)”迴圈的一部分。線路軌72沿著接地層86之邊緣以第一方向延伸，而線路軌74沿著接地層86之另一邊緣以第二方向延伸，此第二方向垂直於第一方向。線路軌72、74與接觸導通孔(vias) 84電性耦合，其中該接觸導通孔84與位於基板外表面上的球閘陣列(ball grid array,BGA)焊接球電性耦合。BGA焊接球可位於與晶粒之相同或不同表面上。
類似於第1、2圖，第一、第二、第三、第四垂直線路76、78、80與82分別垂直地從各自的線路軌72、74延伸到接地層86中。垂直線路76、78、80與82為”電源A(power A)”迴圈的另一部分，且其各自使線路軌72、74與接觸導通孔88電性耦合，其中接觸導通孔88與晶粒電性耦合。垂直線路76、78、80與82各自垂直地延伸至最靠近自身線路的晶粒區域92之邊緣。
第1圖~第3圖之差異突顯出這些實施例之優點。其中之一項優點在於位在基板外部表面上的導電球(conductive balls)之設置彈性(flexibility)，以及接觸導通孔(vias)之設置彈性。在第1圖~第3圖中的BGA球以及與BGA球電性耦合之接觸導通孔24、54、84，可以以任意方式排列。如第1圖所示，接觸導通孔24與BGA球位於靠近線路軌12、14之接點。如第2圖所示，3個接觸導通孔54排列於垂直線路52上。如第3圖所示，2個接觸導通孔84排列於垂直線路80上，且另一個接觸導通孔84位於垂直線路78上。其他BGA球之設置以及與其電性耦合之接觸導通孔之設置包括於其他實施例中，本發明之保護範圍並不以所揭露之圖式為限。此外，接觸導通孔並不需要位於垂直線路上(垂直線路使線路軌與耦合至晶粒上的接觸導通孔耦合)。換言之，接觸導通孔可與該些垂直導線分隔開，亦可以藉由另一線路與任一線路軌及/或垂直線路進行耦合。
另一優點在於位在接地層中的線路之設置彈性(flexibility)。垂直線路可設置於延伸穿過接地層之任何位置上。此外，垂直線路可直接與任何的線路軌耦合。須注意的是，此處所述之垂直線路係垂直於線路軌或晶粒區域邊緣，或者平行於回流電流之直接路徑。此處所使用的”垂直”和”平行”等用語，也包括依據一個基準線進行垂直或平行的次要路徑變化(minor routing variations)，此次要路徑變化係基於避開穿孔的考量或是生產基板的限制，目的在於防止線路(trace)垂直或平行，例如，於製作基板的過程中，導線只可延伸於四個方向中的某一方向(X方向、Y方向、與X方向相差正45度、與X方向相差負45度)
如上所述，上述實施例可同時降低電源A迴圈與電源B迴圈之阻抗。發明人亦觀察到第1圖~第3圖實施例之阻抗優於習知具有相對BGA配置之結構。由於降低上述情況中的阻抗，亦可降低電源迴圈中的雜訊，或是降低存在於晶粒中或從晶粒輸出的訊號之雜訊。
關於第1圖之實施例，電源B迴圈於頻率266 MHz、533 MHz、800 MHz的條件下之阻抗分別為0.74Ω、1.67Ω與2.88Ω，此數值分別高於習知結構67.5%、75.7%與89.5%。此外，此實施例中的電源A迴圈於直流電(DC)的條件下具有0.08 Ω的阻抗，此數值高於習知結構42.9%。
關於第2圖之實施例，電源B迴圈於頻率266 MHz、533 MHz、800 MHz的條件下之阻抗分別為0.76Ω、1.68Ω與2.70Ω，此數值分別高於習知結構69.0%、77.0%與97.7%。此外，此實施例中的電源A迴圈於直流電(DC)的條件下具有0.09 Ω的阻抗，此數值高於習知結構18.2%。
關於第3圖之實施例，電源B迴圈於頻率266 MHz、533 MHz、800 MHz的條件下之阻抗分別為0.79Ω、1.73Ω與2.86Ω，此數值分別高於習知結構68.4%、73.8%與85.6%。此外，此實施例中的電源A迴圈於直流電(DC)的條件下具有0.06Ω的阻抗，此數值高於習知結構14.3%。
依據本發明之另一實施例，第4A-4H圖顯示基板之形成方法。於第4A圖中，提供一核心100，其中在核心100之上表面壓合上一金屬導體102，在核心100之下表面壓合上另一金屬導體104。金屬導體102與104可以是銅。於第4B圖中，蝕刻金屬導體102與104，以形成線路軌(rail traces) 110、112與接地層106、108。第4B圖的剖面圖之平面圖顯示於第4C圖中，其中沿著第4C圖中的線4B-4B以形成第4B圖之剖面。第4C圖中顯示接地層106、線路軌110、116與垂直線路114、118。此佈局為第1圖~第3圖之簡化佈局。此外，此佈局所顯示的是形成於核心100上表面之導線層(wiring layer)，而且類似的佈局可形成於核心100之下表面。
於第4D圖中，形成樹脂120以覆蓋核心100上表面之導線層上，且形成另一樹脂122以覆蓋核心100下表面之導線層。於第4E圖中，蝕刻樹脂120以形成導通孔(via hole) 124，鑽過樹脂120、核心100與樹脂122以形成穿孔(through-via hole) 128。接著，電鍍一金屬導體126以覆蓋整個結構。於第4F圖中，蝕刻金屬導體126以形成訊號線130、接觸穿孔132與接觸導通孔134。形成一焊料罩幕136以覆蓋結構頂部，形成另一焊接罩幕138以覆蓋結構底部。
於第4G圖中，移除耦合到接觸導通孔(via)134之金屬導體上的焊料罩幕(solder mask) 136。接著，進行表面拋光(surface finish)。舉例而言，於移除的區域電鍍鎳142與金144，以形成導線接合指狀物(wire bond finger)。亦可使用其他表面拋光步驟，例如使用無電極電鍍鎳金(electroless nickel immersion gold,ENIG)、無電極電鍍鎳鈀金(nickel electroless palladium immersion gold,ENEPIG)或鎳鈀層。接著，晶粒140藉由黏著劑139接合到此結構。導線146用於接合指狀物與晶粒140，以形成結構與晶粒之間的電性連接。第4H圖顯示位於核心100上表面之金屬線層，此圖類似於第4C圖。第4H圖中亦顯示疊加於(super-imposed)此佈局上之接觸穿孔(through-via) 132、接觸導通孔(via)與晶粒區域148。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10．．．中間層
12、14．．．線路軌(trace rails)
16、18、20、22．．．線路(trace)
24、28、30．．．接觸導通孔(vias)
26．．．接地層(ground plane)
32．．．晶粒區域(die area)
40．．．中間層
42、44．．．線路軌(trace rails)
46、48、50、52．．．線路(trace)
54、58、60．．．接觸導通孔(vias)
56．．．接地層(ground plane)
62．．．晶粒區域(die area)
70．．．中間層
72、74．．．線路軌(trace rails)
76、78、80、82．．．線路(trace)
84、88、90．．．接觸導通孔(vias)
86．．．接地層(ground plane)
92．．．晶粒區域(die area)
100．．．核心
102、104．．．金屬導體(metal conductor)
106、108．．．接地層(ground planes)
110、112、116．．．線路軌(rail traces)
114、118．．．垂直線路
120、122．．．樹脂(resin)
124．．．導通孔(via hole)
126．．．金屬導體
128．．．穿孔(through-via hole)
130．．．訊號線(signal trace)
132．．．接觸穿孔(through-via)
134．．．接觸導通孔(via)
136、138．．．焊料罩幕(solder mask)
139．．．黏著層(adhesive)
140．．．晶粒(die)
142．．．鎳
146．．．導線(wire)
148．．．晶粒區域(die area)
第1~3圖為一系列俯視圖，用以說明本發明各個實施例之基板之中間層。
第4A~4H圖為一系列剖面圖，用以說明本發明一較佳實施例製作基板的方法。
10．．．中間層
12、14．．．線路軌(trace rails)
16、18、20、22．．．線路(trace)
24、28、30．．．接觸導通孔(vias)
26．．．接地層(ground plane)
32．．．晶粒區域(die area)

Claims (10)

  1. 一種基板佈局，包括：一第一電源迴圈(first power loop)之一接地層(ground plane)，位於一基板的一層上；一第一線路軌(first trace rail)，位於該層上且沿著該接地層之一第一外圍延伸，其中該接地層位於該第一線路軌與一晶粒區域之間；以及一第一垂直線路(first perpendicular trace)耦合該第一線路軌，且從該第一線路軌垂直地延伸，其中該第一線路軌與該第一垂直線路組成一第二電源迴圈。
  2. 如申請專利範圍第1項所述之基板佈局，尚包括：一第二線路軌，沿著該接地層之一第二外圍以一第二方向延伸，其中該第一線路軌沿著不同於該第二方向之一第一方向延伸，且其中該第一線路軌與該第二線路軌彼此電性耦合；以及一第二垂直線路與該第二線路軌耦合，且從該第二線路軌垂直地延伸。
  3. 如申請專利範圍第2項所述之基板佈局，尚包括：一第三垂直線路與該第二線路軌耦合，且從該第二線路軌垂直地延伸。
  4. 如申請專利範圍第1項所述之基板佈局，其中該第二電源迴圈中沒有任何線路截斷(cut off)從該接地層流向一接觸導通孔(via)的回流電流(return current)之直接路徑(direct flow)，其中該接觸導通孔(via)係使該接地層電性耦合至一晶粒。
  5. 如申請專利範圍第1項所述之基板佈局，其中一接觸導通孔(vias)、一接觸穿孔(through-via)或上述之組合與該第一線路軌直接耦合；以及該接觸導通孔、該接觸穿孔(through-via)或上述之組合與一焊接球(solder ball)電性耦合。
  6. 如申請專利範圍第1項所述之基板佈局，其中一接觸導通孔(vias)、一接觸穿孔(through-via)或上述之組合與該第一垂直線路直接耦合；以及該接觸導通孔、該接觸穿孔(through-via)或上述之組合與一焊接球(solder ball)電性耦合。
  7. 如申請專利範圍第1項所述之基板佈局，其中該第一垂直線路與一接觸導通孔(vias)、接觸穿孔(through-via)或上述之組合直接耦合；以及該接觸導通孔、該接觸穿孔(through-via)或上述之組合與一指狀物(finger)電性耦合，其中該指狀物電性耦合該晶粒。
  8. 一種基板佈局，包括：一接地層(ground plane)，位於一基板的一層上，其中該接地層為一第一電源迴圈(first power loop)之一部分；一第一線路軌(first trace rail)，係沿著該接地層之一第一外部邊緣(first outer edge)延伸，其中該第一線路軌為一第二電源迴圈之一部分，且該接地層位於該第一線路軌與一晶粒區域之間；以及一第一線路(first trace)耦合該第一線路軌，其中該第二電源迴圈中沒有任何線路沿著垂直且與一回流電流(return current)之直接路徑(direct path)相交叉(intersect)的方向延伸，其中該回流電流係在該接地層中流到一回流電流結構，其中該回流電流結構大體上包含一接觸導通孔(via)、一接觸穿孔(through-via)或上述之組合。
  9. 如申請專利範圍第8項所述之基板佈局，其中該第一線路從該第一線路軌垂直地延伸。
  10. 如申請專利範圍第8項所述之基板佈局，尚包括：一第二線路軌，係沿著該接地層之一第二外部邊緣(second outer edge)延伸，其中該第一外部邊緣與該第二外部邊緣以不同方向延伸，且其中該第一線路軌與該第二線路軌彼此電性耦合；以及一第二線路與該第二線路軌耦合，其中該第二線路從該第二線路軌垂直地延伸。
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