JP5190811B2 - 電源モジュール - Google Patents
電源モジュール Download PDFInfo
- Publication number
- JP5190811B2 JP5190811B2 JP2009296007A JP2009296007A JP5190811B2 JP 5190811 B2 JP5190811 B2 JP 5190811B2 JP 2009296007 A JP2009296007 A JP 2009296007A JP 2009296007 A JP2009296007 A JP 2009296007A JP 5190811 B2 JP5190811 B2 JP 5190811B2
- Authority
- JP
- Japan
- Prior art keywords
- input
- wiring
- electronic component
- terminal
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Dc-Dc Converters (AREA)
Description
図1は、本発明による電源モジュールの好適な一実施形態であるDCDCコンバータ1(電源モジュール)の構造を概略的に示す断面図であり、図2は、DCDCコンバータ1の等価回路図である。
Claims (2)
- 電子部品が内蔵された基板と、
前記基板上に載置され、且つ、所定の接地電位に接続される入力側キャパシタと、
前記基板に設けられ、且つ、入力電圧が入力される第1入力端子と、
を備え、
前記電子部品は、前記基板に設けられた第1ビア導体を介して前記入力側キャパシタと電気的に接続されており、且つ、前記入力電圧に応じた電圧が入力される第2入力端子を有しており、
前記第1入力端子は、前記基板に設けられた第2ビア導体を介して前記入力側キャパシタと電気的に接続されており、
前記第1入力端子及び前記電子部品は、前記入力側キャパシタを構成する一対の電極のうち接地されていない方の電極に接続されており、
前記第1入力端子及び前記入力側キャパシタが接続される配線、並びに、前記第2入力端子及び前記入力側キャパシタが接続される配線は、前記第2入力端子が形成される層とは異なる層で短絡されている、
電源モジュール。 - 前記基板上に載置され、且つ、前記基板に内蔵された電子部品とは異なる電子部品を備え、
前記電子部品は、前記第2入力端子が前記異なる電子部品とは反対側を向くように配置される、
請求項1記載の電源モジュール。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009296007A JP5190811B2 (ja) | 2009-12-25 | 2009-12-25 | 電源モジュール |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009296007A JP5190811B2 (ja) | 2009-12-25 | 2009-12-25 | 電源モジュール |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2011138812A JP2011138812A (ja) | 2011-07-14 |
JP5190811B2 true JP5190811B2 (ja) | 2013-04-24 |
Family
ID=44349984
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009296007A Active JP5190811B2 (ja) | 2009-12-25 | 2009-12-25 | 電源モジュール |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP5190811B2 (ja) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10193442B2 (en) | 2016-02-09 | 2019-01-29 | Faraday Semi, LLC | Chip embedded power converters |
WO2018148218A1 (en) * | 2017-02-08 | 2018-08-16 | Faraday Semi, LLC | Chip embedded power converters |
US10504848B1 (en) | 2019-02-19 | 2019-12-10 | Faraday Semi, Inc. | Chip embedded integrated voltage regulator |
US11069624B2 (en) | 2019-04-17 | 2021-07-20 | Faraday Semi, Inc. | Electrical devices and methods of manufacture |
US11063516B1 (en) | 2020-07-29 | 2021-07-13 | Faraday Semi, Inc. | Power converters with bootstrap |
US11990839B2 (en) | 2022-06-21 | 2024-05-21 | Faraday Semi, Inc. | Power converters with large duty cycles |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003188302A (ja) * | 2001-12-20 | 2003-07-04 | Kyocera Corp | 複合電子部品 |
JP3709882B2 (ja) * | 2003-07-22 | 2005-10-26 | 松下電器産業株式会社 | 回路モジュールとその製造方法 |
JP2009049046A (ja) * | 2007-08-13 | 2009-03-05 | Tdk Corp | 電子部品モジュール |
-
2009
- 2009-12-25 JP JP2009296007A patent/JP5190811B2/ja active Active
Also Published As
Publication number | Publication date |
---|---|
JP2011138812A (ja) | 2011-07-14 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4953034B2 (ja) | 電圧変換器 | |
EP2160931B1 (en) | Printed circuit board | |
US7239525B2 (en) | Circuit board structure with embedded selectable passive components and method for fabricating the same | |
JP5369827B2 (ja) | 電子部品内蔵モジュール | |
JP5190811B2 (ja) | 電源モジュール | |
TWI424799B (zh) | 基板佈局與其形成方法 | |
US20070194432A1 (en) | Arrangement of non-signal through vias and wiring board applying the same | |
WO2012137548A1 (ja) | チップ部品内蔵樹脂多層基板およびその製造方法 | |
JP2005294383A (ja) | キャパシタ実装配線基板及びその製造方法 | |
US8134841B2 (en) | Printed-wiring board, method of manufacturing printed-wiring board, and electronic equipment | |
JP4365166B2 (ja) | キャパシタ、多層配線基板及び半導体装置 | |
JP5160052B2 (ja) | 配線基板、キャパシタ | |
JP4983906B2 (ja) | 電子部品内蔵モジュール | |
JP7087044B2 (ja) | チップ電力供給システム、チップ、pcb、およびコンピュータデバイス | |
JP4829998B2 (ja) | キャパシタ実装配線基板 | |
TW202406421A (zh) | 印刷電路板和包括印刷電路板的電子設備 | |
CN106068056B (zh) | 印刷布线衬底 | |
US20170354038A1 (en) | Semiconductor integrated circuit device, printed board and manufacturing method of the semiconductor integrated circuit device | |
JP5105106B2 (ja) | 電子部品内蔵モジュール | |
JP2020013917A (ja) | 配線基板 | |
WO2024022449A1 (zh) | 印刷电路板和包括印刷电路板的电子设备 | |
CN112768425B (zh) | 一种多芯片模块 | |
JP4907274B2 (ja) | 配線基板、キャパシタ | |
TWI628771B (zh) | 半導體元件搭載基板 | |
JP2016178142A (ja) | 部品内蔵電源モジュール、部品内蔵モジュール及び部品内蔵モジュールの駆動方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20120213 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20121019 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20121212 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20130107 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20130120 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5190811 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20160208 Year of fee payment: 3 |