JP5369827B2 - 電子部品内蔵モジュール - Google Patents
電子部品内蔵モジュール Download PDFInfo
- Publication number
- JP5369827B2 JP5369827B2 JP2009085483A JP2009085483A JP5369827B2 JP 5369827 B2 JP5369827 B2 JP 5369827B2 JP 2009085483 A JP2009085483 A JP 2009085483A JP 2009085483 A JP2009085483 A JP 2009085483A JP 5369827 B2 JP5369827 B2 JP 5369827B2
- Authority
- JP
- Japan
- Prior art keywords
- electronic component
- substrate
- ground
- wiring
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000000758 substrate Substances 0.000 claims abstract description 75
- 239000004020 conductor Substances 0.000 claims description 60
- 230000004907 flux Effects 0.000 abstract description 17
- 230000000903 blocking effect Effects 0.000 abstract description 4
- 238000000034 method Methods 0.000 description 27
- HEZMWWAKWCSUCB-PHDIDXHHSA-N (3R,4R)-3,4-dihydroxycyclohexa-1,5-diene-1-carboxylic acid Chemical class O[C@@H]1C=CC(C(O)=O)=C[C@H]1O HEZMWWAKWCSUCB-PHDIDXHHSA-N 0.000 description 14
- 238000010586 diagram Methods 0.000 description 14
- 230000008569 process Effects 0.000 description 13
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 6
- 230000007257 malfunction Effects 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000011347 resin Substances 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000009499 grossing Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000008054 signal transmission Effects 0.000 description 3
- 230000001629 suppression Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000012544 monitoring process Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000007731 hot pressing Methods 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 229910000859 α-Fe Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
- H01L2224/82009—Pre-treatment of the connector or the bonding area
- H01L2224/8203—Reshaping, e.g. forming vias
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Coils Or Transformers For Communication (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
図1は、本発明による電子部品内蔵モジュールの好適な一実施形態であるDCDCコンバータ1の構造を概略的に示す断面図であり、図2は、DCDCコンバータ1の等価回路図である。
同様に、
パターン31E、グラウンド(接地)用の配線パターン31G、モード切替用の配線パターン31M、及び、出力電圧用の配線パターン31Voが形成される。また、第1配線層31には、外部素子と電気的に接続するために出力端子が形成されており、入力電圧端子21、イネーブル端子22、グラウンド端子23、モード端子24、出力電圧端子25を有している。さらに、積層される第2配線層32と接続するために、入力電圧用のビア導体92Vi、イネーブル用のビア導体92E、グラウンド用のビア導体92
G、モード切替用のビア導体92M、及び、出力電圧用のビア導体92Voが形成されており、上記各種の配線パターン31は、各種出力端子21〜25と、各種出力端子21〜25に対応する各ビア導体92とを接続している。
Claims (1)
- 第1の電子部品が内蔵された基板と、
前記基板上に載置された第2の電子部品と、
前記基板の内部において前記第1の電子部品と前記第2の電子部品との間に設けられており、且つ、所定の接地電位に接続された第1シールド層と、を有し、
前記第1シールド層は、前記接地電位に接続されたグラウンド端子にビア導体を介して接続され、且つ、前記基板の面方向における前記第1の電子部品の実装領域を覆うように形成され、
前記ビア導体は、前記第1の電子部品の側端部側に配置され、且つ、前記第1シールド層から前記基板の厚み方向に沿って直線状に前記グラウンド端子まで延設され、
前記第1の電子部品は、該第1の電子部品の出力端子が、前記第2の電子部品とは反対側を向くように配置され、
前記基板の内部において前記第1シールド層よりも下層であり、前記第1の電子部品を挟んで前記第2の電子部品及び前記第1シールド層と反対側に形成されており、且つ、前記接地電位に接続された第2シールド層と、
を有する電子部品内蔵モジュール。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009085483A JP5369827B2 (ja) | 2009-03-31 | 2009-03-31 | 電子部品内蔵モジュール |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009085483A JP5369827B2 (ja) | 2009-03-31 | 2009-03-31 | 電子部品内蔵モジュール |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2010238925A JP2010238925A (ja) | 2010-10-21 |
JP5369827B2 true JP5369827B2 (ja) | 2013-12-18 |
Family
ID=43092992
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009085483A Active JP5369827B2 (ja) | 2009-03-31 | 2009-03-31 | 電子部品内蔵モジュール |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP5369827B2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11355445B2 (en) | 2019-12-26 | 2022-06-07 | Samsung Electronics Co., Ltd. | Semiconductor packages |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4983906B2 (ja) * | 2009-12-25 | 2012-07-25 | Tdk株式会社 | 電子部品内蔵モジュール |
JP5736949B2 (ja) * | 2011-05-13 | 2015-06-17 | 株式会社村田製作所 | 高周波回路モジュール |
JP2012238797A (ja) * | 2011-05-13 | 2012-12-06 | Murata Mfg Co Ltd | 多層回路モジュール |
JP2012256675A (ja) * | 2011-06-08 | 2012-12-27 | Shinko Electric Ind Co Ltd | 配線基板、半導体装置及びその製造方法 |
JP2013084692A (ja) * | 2011-10-06 | 2013-05-09 | Ibiden Co Ltd | 配線板及びその製造方法 |
US8541849B2 (en) * | 2012-02-14 | 2013-09-24 | Genia Technologies, Inc. | Noise shielding techniques for ultra low current measurements in biochemical applications |
JP5342704B1 (ja) * | 2012-11-12 | 2013-11-13 | 太陽誘電株式会社 | 高周波回路モジュール |
JP6015813B2 (ja) * | 2015-05-27 | 2016-10-26 | 株式会社村田製作所 | 多層回路モジュール |
KR20240106874A (ko) * | 2022-12-29 | 2024-07-08 | 엘지이노텍 주식회사 | 통신모듈 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2682477B2 (ja) * | 1994-11-16 | 1997-11-26 | 日本電気株式会社 | 回路部品の実装構造 |
JP2001267710A (ja) * | 2000-03-15 | 2001-09-28 | Sony Corp | 電子回路装置および多層プリント配線板 |
JP2001291817A (ja) * | 2000-04-05 | 2001-10-19 | Sony Corp | 電子回路装置および多層プリント配線板 |
JP2009105096A (ja) * | 2007-10-19 | 2009-05-14 | Advantest Corp | 基板および電子部品を備える装置 |
-
2009
- 2009-03-31 JP JP2009085483A patent/JP5369827B2/ja active Active
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11355445B2 (en) | 2019-12-26 | 2022-06-07 | Samsung Electronics Co., Ltd. | Semiconductor packages |
US11735532B2 (en) | 2019-12-26 | 2023-08-22 | Samsung Electronics Co., Ltd. | Semiconductor packages |
Also Published As
Publication number | Publication date |
---|---|
JP2010238925A (ja) | 2010-10-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5369827B2 (ja) | 電子部品内蔵モジュール | |
US10219390B2 (en) | Fabrication method of packaging substrate having embedded passive component | |
KR101095161B1 (ko) | 전자부품 내장형 인쇄회로기판 | |
JP4953034B2 (ja) | 電圧変換器 | |
US9478343B2 (en) | Printed wiring board | |
EP3547363B1 (en) | Electronic assembly and electronic system with impedance matched interconnect structures | |
KR20150025449A (ko) | 전자부품 내장기판 | |
JP2005311249A (ja) | 部品内蔵型多層基板 | |
US9161433B2 (en) | Power supply control circuit module | |
JP5750528B1 (ja) | 部品内蔵回路基板 | |
US20150055309A1 (en) | Electronic component embedded substrate and method of manufacturing electronic component embedded substrate | |
JP4983906B2 (ja) | 電子部品内蔵モジュール | |
JP2015012022A (ja) | プリント配線板 | |
JP2007335764A (ja) | 配線基板、キャパシタ | |
JP5190811B2 (ja) | 電源モジュール | |
JP2005277389A (ja) | 多層配線基板及び半導体パッケージ | |
JP5354394B2 (ja) | 部品内蔵基板及びその製造方法 | |
JP2008141136A (ja) | 多層配線基板及び素子搭載装置 | |
US20070228578A1 (en) | Circuit substrate | |
JPWO2020174941A1 (ja) | 電子機器及び基板 | |
JP5105106B2 (ja) | 電子部品内蔵モジュール | |
JP2009117409A (ja) | 回路基板 | |
JP2018082070A (ja) | 配線基板およびこれを用いた電子装置 | |
JP2013115110A (ja) | 段差構造のプリント配線板 | |
JP2010062180A (ja) | 多層プリント配線板 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20111213 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20130124 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20130225 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130416 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20130820 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20130902 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5369827 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |