JP5750528B1 - 部品内蔵回路基板 - Google Patents
部品内蔵回路基板 Download PDFInfo
- Publication number
- JP5750528B1 JP5750528B1 JP2014063845A JP2014063845A JP5750528B1 JP 5750528 B1 JP5750528 B1 JP 5750528B1 JP 2014063845 A JP2014063845 A JP 2014063845A JP 2014063845 A JP2014063845 A JP 2014063845A JP 5750528 B1 JP5750528 B1 JP 5750528B1
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- JP
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- Prior art keywords
- circuit board
- component
- layer
- built
- conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/0242—Structural details of individual signal conductors, e.g. related to the skin effect
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
- H05K3/4608—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated comprising an electrically conductive base or core
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4697—Manufacturing multilayer circuits having cavities, e.g. for mounting components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
- H01L2224/251—Disposition
- H01L2224/2518—Disposition being disposed on at least two different sides of the body, e.g. dual array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0215—Grounding of printed circuits by connection to external grounding means
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Waveguides (AREA)
- Transceivers (AREA)
Abstract
Description
本発明の第1の実施の形態に係る部品内蔵回路基板について図面を参照して説明する。図1は部品内蔵回路基板の外観斜視図、図2は図1のX軸方向の断面図、図3は図1のY軸方向の断面図である。
次に、本発明の第2の実施の形態について図面を参照して説明する。前記第1の実施の形態に係る部品内蔵回路基板100では、コア層200に対して一方の側の導体層421に形成された信号線610のみが、貫通孔201の投影領域を横切るように形成されていた。本実施の形態に係る部品内蔵回路基板110では、図10に示すように、コア層200に対して他方の側の導体層321に形成された信号線630も、貫通孔201の投影領域を横切るように形成されている。ここで、部品内蔵回路基板110を厚み方向に透過してみた場合、信号線610と信号線630は交差しており、且つ、少なくとも信号線610と信号線630の交差部に内蔵部品としての回路基板500のグランド導体510が介在している。
本発明の第3の実施の形態に係る部品内蔵回路基板について図11を参照して説明する。図11は、第3の実施の形態に係る部品内蔵回路基板の断面図である。
本発明の第4の実施の形態に係る部品内蔵回路基板について図12を参照して説明する。図12は、第4の実施の形態に係る部品内蔵回路基板の断面図である。
本発明の第5の実施の形態に係る部品内蔵回路基板について図13を参照して説明する。図13は、第5の実施の形態に係る部品内蔵回路基板の断面図である。
Claims (6)
- 導体層と絶縁体層とを積層してなる回路基板と、該回路基板内に埋設された部品とを備えた部品内蔵回路基板において、
前記回路基板は、他の導体層より厚みが大きく且つグランドとして機能する導体層であるコア層を含み、前記部品はコア層に形成された貫通孔内に配置されており、
前記コア層に対向する導体層であって前記貫通孔を厚み方向に投影した領域には、高周波信号を伝送する信号線が形成されており、
前記部品は、前記信号線を厚み方向に投影した領域の少なくとも一部に形成されたグランドとして機能するグランド導体を備えた
ことを特徴とする部品内蔵回路基板。 - 前記部品のグランド導体を厚み方向に投影した領域における前記信号線の線幅が、コア層と対向する領域における前記信号線の線幅よりも大きい
ことを特徴とする請求項1記載の部品内蔵回路基板。 - 前記部品は、基板と、該基板の全部又は一部を覆い且つ前記グランド導体として機能する金属体とを含む
ことを特徴とする請求項1又は2記載の部品内蔵回路基板。 - 前記部品は、基板を含み、
該基板の表層又は内層には前記グランド導体が形成されている
ことを特徴とする請求項1又は2記載の部品内蔵回路基板。 - 前記部品は、前記グランド導体として機能する導体層と絶縁体層とを積層した回路基板からなる
ことを特徴とする請求項1又は2記載の部品内蔵回路基板。 - 前記部品は、半導体素子を含み、
該半導体素子の表面には前記グランド導体が形成されている
ことを特徴とする請求項1又は2記載の部品内蔵回路基板。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2014063845A JP5750528B1 (ja) | 2014-03-26 | 2014-03-26 | 部品内蔵回路基板 |
US14/511,984 US9713259B2 (en) | 2014-03-26 | 2014-10-10 | Communication module |
CN201410806688.2A CN104955260B (zh) | 2014-03-26 | 2014-12-22 | 部件内置电路板 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2014063845A JP5750528B1 (ja) | 2014-03-26 | 2014-03-26 | 部品内蔵回路基板 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP5750528B1 true JP5750528B1 (ja) | 2015-07-22 |
JP2015185812A JP2015185812A (ja) | 2015-10-22 |
Family
ID=53638010
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2014063845A Expired - Fee Related JP5750528B1 (ja) | 2014-03-26 | 2014-03-26 | 部品内蔵回路基板 |
Country Status (3)
Country | Link |
---|---|
US (1) | US9713259B2 (ja) |
JP (1) | JP5750528B1 (ja) |
CN (1) | CN104955260B (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2017069523A (ja) * | 2015-10-02 | 2017-04-06 | 株式会社村田製作所 | インダクタ部品、パッケージ部品およびスィッチングレギュレータ |
JP2019192920A (ja) * | 2019-05-31 | 2019-10-31 | 株式会社村田製作所 | インダクタ部品、パッケージ部品およびスィッチングレギュレータ |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106356351B (zh) * | 2015-07-15 | 2019-02-01 | 凤凰先驱股份有限公司 | 基板结构及其制作方法 |
US10950550B2 (en) * | 2015-12-22 | 2021-03-16 | Intel Corporation | Semiconductor package with through bridge die connections |
JP6620885B2 (ja) * | 2016-04-14 | 2019-12-18 | 株式会社村田製作所 | 複合部品内蔵回路基板、及び、複合部品 |
JP2018006450A (ja) * | 2016-06-29 | 2018-01-11 | 新光電気工業株式会社 | 電子部品内蔵基板及びその製造方法と電子部品装置 |
DE102017209366A1 (de) * | 2017-06-02 | 2018-12-06 | Conti Temic Microelectronic Gmbh | Elektrische Komponente und Verfahren zu deren Herstellung |
JP7167933B2 (ja) * | 2017-10-26 | 2022-11-09 | Tdk株式会社 | 電子部品内蔵構造体 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012209527A (ja) * | 2011-03-30 | 2012-10-25 | Tdk Corp | 部品内蔵基板及びその製造方法 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4339739B2 (ja) * | 2004-04-26 | 2009-10-07 | 太陽誘電株式会社 | 部品内蔵型多層基板 |
JP5284155B2 (ja) * | 2008-03-24 | 2013-09-11 | 日本特殊陶業株式会社 | 部品内蔵配線基板 |
CN103733426B (zh) * | 2012-01-06 | 2016-07-20 | 株式会社村田制作所 | 高频信号线路及电子设备 |
JP5143972B1 (ja) * | 2012-08-16 | 2013-02-13 | 太陽誘電株式会社 | 高周波回路モジュール |
US20140153204A1 (en) * | 2012-11-30 | 2014-06-05 | Samsung Electro-Mechanics Co., Ltd. | Electronic component embedded printing circuit board and method for manufacturing the same |
JP5420104B1 (ja) | 2013-08-29 | 2014-02-19 | 太陽誘電株式会社 | 高周波回路モジュール |
-
2014
- 2014-03-26 JP JP2014063845A patent/JP5750528B1/ja not_active Expired - Fee Related
- 2014-10-10 US US14/511,984 patent/US9713259B2/en active Active
- 2014-12-22 CN CN201410806688.2A patent/CN104955260B/zh not_active Expired - Fee Related
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012209527A (ja) * | 2011-03-30 | 2012-10-25 | Tdk Corp | 部品内蔵基板及びその製造方法 |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2017069523A (ja) * | 2015-10-02 | 2017-04-06 | 株式会社村田製作所 | インダクタ部品、パッケージ部品およびスィッチングレギュレータ |
US10715041B2 (en) | 2015-10-02 | 2020-07-14 | Murata Manufacturing Co., Ltd. | Inductor component, package component, and switching regulator |
US11876449B2 (en) | 2015-10-02 | 2024-01-16 | Murata Manufacturing Co., Ltd. | Inductor component, package component, and switching regulator |
JP2019192920A (ja) * | 2019-05-31 | 2019-10-31 | 株式会社村田製作所 | インダクタ部品、パッケージ部品およびスィッチングレギュレータ |
Also Published As
Publication number | Publication date |
---|---|
US9713259B2 (en) | 2017-07-18 |
CN104955260A (zh) | 2015-09-30 |
JP2015185812A (ja) | 2015-10-22 |
CN104955260B (zh) | 2018-02-23 |
US20150282328A1 (en) | 2015-10-01 |
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