WO2024022449A1 - 印刷电路板和包括印刷电路板的电子设备 - Google Patents

印刷电路板和包括印刷电路板的电子设备 Download PDF

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Publication number
WO2024022449A1
WO2024022449A1 PCT/CN2023/109606 CN2023109606W WO2024022449A1 WO 2024022449 A1 WO2024022449 A1 WO 2024022449A1 CN 2023109606 W CN2023109606 W CN 2023109606W WO 2024022449 A1 WO2024022449 A1 WO 2024022449A1
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WO
WIPO (PCT)
Prior art keywords
power
printed circuit
circuit board
conduction path
signal conduction
Prior art date
Application number
PCT/CN2023/109606
Other languages
English (en)
French (fr)
Inventor
周宴
郑夏威
严明
Original Assignee
摩尔线程智能科技(北京)有限责任公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Priority claimed from CN202210892660.XA external-priority patent/CN115209613A/zh
Priority claimed from CN202221953984.1U external-priority patent/CN217936067U/zh
Application filed by 摩尔线程智能科技(北京)有限责任公司 filed Critical 摩尔线程智能科技(北京)有限责任公司
Publication of WO2024022449A1 publication Critical patent/WO2024022449A1/zh

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits

Definitions

  • the present application relates to the field of electronic circuit technology, and in particular, to a printed circuit board and electronic equipment including the printed circuit board.
  • integrated circuit chips are becoming more and more integrated.
  • integrated circuit chips include an increasing number of circuit modules. These different circuit modules usually have independent functions.
  • the above-mentioned circuit modules are also called IP cores.
  • the integrated circuit chip is disposed on the printed circuit board, and the power pins of the integrated circuit chip are electrically connected to the power traces in the printed circuit board, so that the integrated circuit chip can receive the corresponding power voltage via the printed circuit board.
  • Some embodiments of the present application provide a printed circuit board, which can at least reduce the noise interference between different circuit modules in the integrated circuit chip when the integrated circuit chip is running, even if these different circuit modules receive The power signals are the same.
  • a printed circuit board provided according to an embodiment of the present application includes: a plurality of conductive layers; and at least one insulating layer, each of the at least one insulating layer being located between adjacent conductive layers in the plurality of conductive layers. between.
  • the plurality of conductive layers include a top conductive layer for connecting a plurality of pins of the integrated circuit chip, the top conductive layer includes a first conductive part and a second conductive part, the first conductive part and the second conductive part The electrical part is respectively used to connect the first power pin and the second power pin among the plurality of pins of the integrated circuit chip.
  • the plurality of conductive layers include power traces that transmit power signals to the integrated circuit chip, and the printed circuit board includes a first power signal conduction path.
  • the first power signal conduction path and the second power signal conduction path electrically connect the first conductive part and the second conductive part to the power trace respectively. wire, so that the first conductive part and the second conductive part receive the same power signal.
  • Each of the first power signal conduction path and the second power signal conduction path passes through at least a first insulating layer of the at least one insulating layer closest to the top conductive layer.
  • the plurality of conductive layers further includes a bottom conductive layer and at least one middle conductive layer, the bottom conductive layer, at least the one middle conductive layer and the top conductive layer along the printed circuit board are stacked sequentially in the thickness direction, the at least one intermediate conductive layer includes the power trace, the first power signal conduction path and the second power signal conduction path are respectively connected from the first conductive part and the A second conductive portion extends to the power trace.
  • the printed circuit board includes first blind holes and second blind holes extending from the first conductive portion and the second conductive portion to the power traces, the first to The path and the second power signal conduction path include the first blind hole and the second blind hole respectively.
  • the plurality of conductive layers further includes a bottom conductive layer and at least one middle conductive layer, the bottom conductive layer, at least the one middle conductive layer and the top conductive layer along the printed circuit board are stacked sequentially in the thickness direction, the bottom conductive layer includes the power trace, the first power signal conduction path and the second power signal conduction path are respectively connected from the first conductive part and the second Conductive portions extend to the power traces.
  • the printed circuit board includes first and second through-holes extending from the first conductive portion and the second conductive portion to the power trace, respectively.
  • the signal conduction path and the second power signal conduction path include the first through hole and the second through hole respectively.
  • the top conductive layer further includes a third conductive portion, the third conductive portion is used to connect a third power pin among the plurality of pins of the integrated circuit chip, and the printed
  • the circuit board also includes a third power signal conduction path, the third power signal conduction path electrically connects the third part to the power trace, so that the first conductive part, the second conductive part part and the third conductive part receive the same power signal.
  • Another embodiment of the present application provides an electronic device, including a printed circuit board as described in any one of the preceding embodiments and an integrated circuit chip, the integrated circuit chip including a power signal for receiving the same voltage level
  • the first power pin and the second power pin are respectively connected to the first conductive part and the second conductive part in the top conductive layer of the printed circuit board. part.
  • the plurality of conductive layers of the printed circuit board include ground traces, and the electronic device Also included is at least one capacitor connected in parallel between the ground trace and the power trace.
  • the integrated circuit chip is disposed on a first side of the printed circuit board, and the at least one capacitor is disposed on a second side of the printed circuit board opposite the first side.
  • the integrated circuit chip further includes a first ground pin and a second ground pin
  • the printed circuit board further includes a first ground signal conduction path and a second ground signal conduction path
  • the The first power signal conduction path, the second power signal conduction path, the first ground signal conduction path and the second ground signal conduction path are respectively connected from the first power supply pin and the third ground signal conduction path.
  • Two power pins, the first ground pin and the second ground pin extend along the thickness direction of the printed circuit board to the second side of the printed circuit board, and the at least one capacitor includes a capacitor connected to a first capacitor between the first power supply signal conduction path and the first ground signal conduction path, and a first capacitor connected between the second power supply signal conduction path and the second ground signal conduction path of the second capacitor.
  • the electronic device further includes a voltage converter, a voltage output terminal of the voltage converter is electrically connected to the power trace in the printed circuit board.
  • the voltage converter is arranged on the first side of the printed circuit board.
  • Figure 1 schematically illustrates a partial top view of a printed circuit board, and electrical connections between the printed circuit board and a power supply powering the printed circuit board, according to one embodiment of the present application;
  • Figure 2 schematically illustrates a partial top view of a printed circuit board and electrical connections between the printed circuit board and a power supply powering the printed circuit board according to another embodiment of the present application;
  • Figure 3 schematically illustrates a partial top view of a printed circuit board and electrical connections between the printed circuit board and a power supply powering the printed circuit board according to another embodiment of the present application;
  • FIG. 4 illustrates a schematic partial cross-sectional view of a printed circuit board according to yet another embodiment of the present application
  • Figure 5 illustrates a schematic partial cross-sectional view of a printed circuit board according to yet another embodiment of the present application
  • Figure 6 illustrates a schematic partial cross-sectional view of a printed circuit board according to yet another embodiment of the present application
  • Figure 7 illustrates a schematic partial cross-sectional view of an electronic device according to yet another embodiment of the present application.
  • FIGS 8 and 9 respectively illustrate the impedance curves at two voltage nodes when the electronic device applies scheme one, scheme two and scheme three described in this article respectively;
  • Figure 10 illustrates the isolation between different voltage nodes when electronic equipment is applied using scheme one, scheme two and scheme three respectively.
  • the "electronic equipment” mentioned in this article at least includes printed circuit boards and integrated circuit chips connected to the printed circuit board. That is to say, “electronic equipment” includes the combination of printed circuit boards and integrated circuit chips. Electronic equipment can also include Additional mechanical parts or electrical components. Examples of electronic devices include, but are not limited to, motherboards, graphics cards, computers, tablets, mobile communication devices, etc.
  • Each circuit module (IP core) in the integrated circuit chip requires a corresponding power supply voltage to achieve the corresponding function.
  • the inventor of the present application realized that different circuit modules have different requirements on the noise of power supply signals. For example, even if the voltage value of the power supply voltage (operating voltage) required by two different circuit modules is the same, the requirements for the ripple signal in the power supply signal are also different. At the same time, there may also be large differences in the power supply noise signals generated when different circuit modules are running. Therefore, a lower degree of coupling between the power supply signals of different circuit modules is expected even when the voltage values of the operating voltages required by different circuit modules are the same.
  • a technical solution to reduce the low degree of coupling between power signals of different circuit modules in an integrated circuit chip is to design multiple independent power supplies on a printed circuit board for different circuit modules in the integrated circuit chip.
  • Figure 1 shows an example of this technical solution.
  • use at least two power supplies e.g.
  • the dots in Figure 1 are used to schematically represent the area where the printed circuit board PB is connected to the pins of the integrated circuit chip, that is, the dots may correspond to the pins of the integrated circuit chip.
  • the output end of the first power supply 10 and a part of the pins of the integrated circuit chip are electrically connected to the first power supply trace (not shown in FIG. 1 ) on the printed circuit board PB, thereby forming a first power supply signal transmission path, and the second power supply
  • the output end of 20 and another part of the pins of the integrated circuit chip are electrically connected to the second power supply trace (not shown in Figure 1) on the printed circuit board PB, thereby forming a second power signal transmission path.
  • FIG. 1 The dots in Figure 1 are used to schematically represent the area where the printed circuit board PB is connected to the pins of the integrated circuit chip, that is, the dots may correspond to the pins of the integrated circuit chip.
  • the output end of the first power supply 10 and a part of the pins of the integrated circuit chip are electrically
  • the first power signal transmission path and the second power signal transmission path are identified as 100 and 200 respectively. Since two independent power supplies are used to supply power to the printed circuit board and the integrated circuit chip, the first power supply trace and the second power supply trace in the printed circuit board are also independent and isolated from each other, so the power supply to each circuit module of the integrated circuit chip The interference noise between each power signal transmission path is small. However, corresponding independent power supplies are still provided for each circuit module with the same operating voltage in the integrated circuit chip, which leads to an increase in the cost of the electronic equipment. Moreover, arranging multiple power traces that are isolated and independent from each other in a printed circuit board may limit the wiring space within the printed circuit board, resulting in weak flow capabilities of some signal traces, including power traces. In order to enhance the flow capacity of the signal traces, it is necessary to increase the number of conductive layers in the printed circuit board, but this further leads to an increase in the production cost of the printed circuit board.
  • Figure 2 illustrates a technical solution according to another embodiment of the present application.
  • the technical solution of Figure 2 only uses a single power supply 10 to work within the integrated circuit chip on the printed circuit board.
  • the circuit modules are powered by the same voltage.
  • a noise suppression device 30 is provided on the voltage output path of the power supply 10 .
  • the noise suppression device 30 can be used to form two power supply signals based on the output of the power supply 10 .
  • the printed circuit board PB shown in FIG. 2 is the same as the printed circuit board shown in FIG. 1 , and the first power signal transmission path and the second power signal transmission path are also identified as 100 and 200 respectively.
  • noise suppression devices 30 include, but are not limited to, magnetic beads, zero-ohm resistors, and the like. Although the voltage levels of the power signals transmitted by the first power signal transmission path and the second power signal transmission path are the same, multiple power traces that are isolated from each other and independent of each other still need to be provided in the printed circuit board PB, which also does not alleviate the need to increase the number of printed circuit boards. There is a contradiction between the flow capacity of the signal traces in the circuit board and the manufacturing cost of the printed circuit board.
  • the technical solution for powering the integrated circuit chip described above in conjunction with FIGS. 1 and 2 may be called a first-type technical solution (Scheme 1).
  • Scheme 1 the technical solution for powering the integrated circuit chip described above in conjunction with FIGS. 1 and 2 may be called a first-type technical solution (Scheme 1).
  • the first type of technical solution multiple independent and isolated power traces are provided in the printed circuit board.
  • the integrated circuit chip is running, the situation is equivalent to the printed circuit board including multiple independent power signals, respectively.
  • Providing voltages to different power pins of the integrated circuit chip helps reduce noise interference between the different power pins of the integrated circuit chip during operation, thereby improving the working performance of the integrated circuit chip.
  • this type of technical solution results in weak flow capacity of some signal traces in the printed circuit board. It is necessary to increase the number of conductive layers of the printed circuit board to improve the flow capacity of the signal traces. This Leading to an increase in the cost of printed circuit boards.
  • a solution that does not increase the cost of the printed circuit board is to interconnect the different power pins in the integrated circuit chip that can receive the same voltage level on the surface conductive layer of the printed circuit board.
  • surface conductive layer refers to the integrated
  • the conductive layer in the printed circuit board closest to the integrated circuit chip can also be understood as the “top conductive layer” mentioned below.
  • a single power supply 10 can be used to power the integrated circuit chip. An example of this technical solution can be explained with the help of Figure 3 .
  • the printed circuit board actually only includes a single power signal transmission path for multiple power supply pins of the integrated circuit chip that receive the same voltage level.
  • the output terminal of the power supply 10 supplies power to different power pins of the integrated circuit chip.
  • the various power supply pins connected to the output terminal of the power supply 10 are actually connected to each other via the same power signal transmission path 100 .
  • the technical solution explained in this paragraph in conjunction with Figure 3 can be called solution two.
  • the wiring space for signal traces including power traces in the printed circuit board is relatively small, so it is conducive to enhancing The flow capacity of the signal traces of the printed circuit board, but the noise interference between different power pins of the integrated circuit chip is obvious during operation, which may lead to a reduction in the operating performance of the integrated circuit chip.
  • Another embodiment of the present application provides a printed circuit board, which attempts to reduce the noise interference between different power pins of the integrated circuit chip during operation, while controlling the production cost of the printed circuit board and ensuring the reliability of the printed circuit board. Strong flow capacity of signal wiring.
  • the printed circuit board provided according to this embodiment includes a plurality of conductive layers and at least one insulating layer, and each insulating layer of the at least one insulating layer is respectively located between adjacent conductive layers of the plurality of conductive layers.
  • Figure 4 schematically shows a partial cross-sectional view of a printed circuit board.
  • the printed circuit board includes a plurality of conductive layers 401, 402, 403, 404, and adjacent conductive layers located in each conductive layer. insulation layer between.
  • the plurality of conductive layers of the printed circuit board include a top conductive layer 401 for connecting a plurality of pins of the integrated circuit chip.
  • the top conductive layer 401 includes a first conductive part 401a and a second conductive part 401b.
  • the two electrical parts 401b are respectively used to connect the first power pin and the second power pin among the plurality of pins of the integrated circuit chip (not shown in Figure 4).
  • the plurality of conductive layers include power traces 402 that transmit power signals to the integrated circuit chip.
  • the printed circuit board includes a first power signal conduction path d1 and a second power signal conduction path d2.
  • the first power signal conduction path d2 and the second power signal conduction path d2 electrically connect the first conductive part 401a and the second conductive part 401b to the power trace 402 respectively, so that the The first conductive part 401a and the second conductive part 401b receive the same power signal.
  • each of the first power signal conduction path d1 and the second power signal conduction path d2 passes through at least the first insulating layer 410 of the at least one insulating layer closest to the top conductive layer. .
  • the cross-sectional view shown in FIG. 4 is only used to schematically represent the technical features of the printed circuit board related to the above-mentioned embodiments of the present application, and other technical features irrelevant to the above-mentioned embodiments are omitted. component or structure.
  • the printed circuit board may further include a solder mask layer located on the top conductive layer 401 and a solder mask layer located below the bottom conductive layer 404 .
  • FIG. 4 shows a printed circuit board including four conductive layers, the number of conductive layers included in the printed circuit board is not limited thereto.
  • the conductive layer structures shown in Figure 4 do not represent the conductive layers in actual printed circuit board products. Some conductive layers can be continuous plate structures or intermittent patterned structures.
  • the first conductive portion 401a and the second electrical portion 401b in the top conductive layer 401 can be used with the integrated circuit chip to receive two different power supplies with the same voltage level, respectively.
  • the pins eg, first power pin and second power pin
  • the first power pin and the second power pin of the integrated circuit chip are electrically connected to the power trace 402 via the first power signal conduction path d1 and the second power signal conduction path d2 passing through the first insulating layer 410 respectively.
  • the first power pin and the second power pin are electrically connected to the same power trace 402, but the equivalent inductance of the first power signal conduction path d1 and the second power signal conduction path d2 can suppress at least A part of the noise signal reduces signal interference between different circuit modules connected to the first power pin and the second power pin in the integrated circuit chip.
  • multiple power traces that are physically isolated from each other are not provided. That is, compared to the aforementioned solution 1, the signal traces including the power traces are included in the printed circuit board. The spatial layout is less constrained, which is conducive to ensuring strong flow capacity of signal wiring.
  • Figure 5 schematically shows a partial cross-sectional view of a printed circuit board according to another embodiment of the present application.
  • the embodiment shown in FIG. 5 is substantially the same as the embodiment shown in FIG. 4 .
  • the main difference between the two lies in the number of conductive layers included in the printed circuit board and the length of the first power signal conduction path and the second power signal conduction path. Differences in path length.
  • the plurality of conductive layers of the printed circuit board include a bottom conductive layer 404/505 and at least one intermediate conductive layer.
  • the bottom conductive layer 404/505, the at least one intermediate conductive layer The conductive layer and the top conductive layer 401/501 are stacked sequentially along the thickness direction of the printed circuit board.
  • the power supply wiring device 402/504 is provided in the at least one middle conductive layer.
  • the first power signal conduction path d1 and the Two power signal conduction paths d2 extend from the first conductive part 401a/501a and the second conductive part 401b/501b to the power trace 402/504 respectively.
  • the first power signal conduction path d1 and the second power signal conduction path d2 in the printed circuit board shown in FIG. 5 have longer lengths.
  • the first conductive portion 501a and the second electrical portion 501b in the top conductive layer 501 can be used with the integrated circuit chip to receive two different power supplies with the same voltage level, respectively.
  • the pins (for example, the first power pin and the second power pin) are welded, and the signal conduction path between the first power pin and the second power pin is longer, which can further reduce the connection between the integrated circuit chip and the second power pin. Signal interference between different circuit modules connected to one power pin and the second power pin.
  • the first power signal conduction path d1 and the second power signal conduction path d2 do not penetrate the entire thickness of the printed circuit board.
  • a conductive part and the second conductive part extend to the first blind hole and the second blind hole of the power trace, and the first power signal conduction path d1 and the second power signal conduction path d2 are respectively Including the first blind hole and the second blind hole.
  • the inner walls of the first blind hole and the second blind hole may be coated with conductive material.
  • the plurality of conductive layers of the printed circuit board include a top conductive layer 601, middle conductive layers 602, 603, 604 and a bottom conductive layer 605.
  • Layers 604, 603, 602 and the top conductive layer 601 are stacked sequentially along the thickness direction of the printed circuit board.
  • the bottom conductive layer 605 includes power traces.
  • the first power signal conduction path and the second power signal conduction path are conductive from the top respectively.
  • the first conductive portion 601a and the second conductive portion 601b of the layer extend to the power traces.
  • the first power signal conduction path d1 and the second power signal conduction path d2 pass through the first insulating layer 610, the insulating layer between each intermediate conductive layer, and connect to the power traces of the bottom conductive layer 605. connect. Similar to the embodiment shown in FIG. 5 , the first power signal conduction path d1 and the second power signal conduction path d2 are insulated from each intermediate conductive layer. Compared with the embodiment shown in FIG. 5, since the first power signal conduction path and the second power signal conduction path respectively extend from the first conductive portion 601a and the second conductive portion 601b of the top conductive layer to the bottom conductive layer.
  • the printed circuit board includes first and second vias for power traces extending from the first and second conductive portions 601a and 601b respectively to the bottom conductive layer 605, the first power signal
  • the conduction path d1 and the second power signal conduction path d2 respectively include the first through hole and the second through hole. Inner walls of the first through hole and the second through hole may be coated with conductive material.
  • the power traces of the printed circuit board can only be distributed in a single conductive layer. According to the design requirements of the printed circuit board, the power traces can be distributed in different conductive layers, and different parts of the same power trace located in different conductive layers can be connected to each other through via holes in the insulating layer. Furthermore, the single cell traces mentioned in the embodiments of FIGS. 4 to 6 are provided for power supply pins in the integrated circuit chip that receive the same voltage level. In the case where the integrated circuit chip includes multiple power supply pins that receive different voltage levels, the printed circuit board may include multiple power supply traces that are isolated and independent from each other.
  • the top conductive layer further includes a third conductive portion, the third conductive portion is used to connect a third power pin among the plurality of pins of the integrated circuit chip, and the printed circuit board further includes a third a power signal conduction path, the third power signal conduction path electrically connects the third part to the power trace, so that the first conductive part, the second conductive part and the third The conductive parts receive the same power signal.
  • the top conductive layer may include any number of conductive portions that are independent of each other and are respectively used to connect different power pins of the integrated circuit chip that receive power signals at the same voltage level.
  • FIG. 1 For embodiments of the present application, provide an electronic device including a printed circuit board as described in any one of the preceding embodiments and an integrated circuit chip, the integrated circuit chip including a device for receiving the same voltage level
  • the first power pin and the second power pin of the power signal, the first power pin and the second power pin are respectively connected to the first conductive part in the top conductive layer of the printed circuit board and Second conductive part.
  • the first power supply pin and the second power supply pin of the integrated circuit chip respectively pass through the first power supply signal conduction path and the second power supply signal conduction path at least through the first insulating layer of the printed circuit board. Electrically connected to power traces.
  • the first power signal conduction path and the second power signal conduction path increase the equivalent inductance value of the signal transmission path between the first power supply pin and the second power supply pin, thereby suppressing at least part of the noise signal and reducing integration Interference between different circuit modules in the circuit chip connected to the first power pin and the second power pin.
  • the spatial layout of the signal traces including the power traces in the printed circuit board is less constrained. Small, which is conducive to ensuring strong flow capacity of strong signal wiring.
  • only one voltage source eg, voltage converter
  • voltage converter is needed to supply power to the first power pin and the second power pin of the integrated circuit chip, thereby avoiding an increase in the cost of electronic equipment components.
  • Figure 7 schematically shows a partial cross-sectional view of an electronic device provided according to an embodiment of the present application.
  • the main difference between the structure of the printed circuit board in this electronic device and the structure of the printed circuit board of the second solution explained with reference to FIG. 3 lies in the locations in the printed circuit board where different power supply pins receiving the same voltage level are interconnected with the power traces.
  • the top view of the printed circuit board shown in FIG. 3 can also be used to schematically represent the top view of the printed circuit board in the electronic device.
  • the partial cross-sectional view shown in Figure 7 can be considered as being taken along line A1-A2 in Figure 3.
  • FIG. 7 schematically shows an integrated circuit chip IC arranged on a printed circuit board, and illustrates a plurality of conductive portions in the top conductive layer 701, including a first conductive portion P1, a second conductive portion P2, a third conductive portion Conductive portion P3, fourth conductive portion G1, fifth conductive portion G2 and sixth conductive portion G3.
  • the first conductive part P1, the second conductive part P2 and the third conductive part P3 are respectively connected to the first power pin, the second power pin and the third power pin of the integrated circuit chip IC for receiving the same voltage level
  • the fourth conductive part G1, the fifth conductive part G2 and the sixth conductive part G3 are respectively connected to the first, second and third ground pins of the integrated circuit chip IC for receiving the reference ground voltage.
  • the printed circuit board includes a first insulating layer 710 , intermediate conductive layers 702 , 703 , 704 and a bottom conductive layer 704 .
  • the multiple conductive layers of the printed circuit board include ground traces and power traces.
  • the ground traces are located in the middle conductive layer 704 and the power traces are located in the bottom conductive layer 705.
  • the first ground pin and the second ground pin of the integrated circuit chip IC The ground pin and the third ground pin are both electrically connected to the ground trace, and the first power pin, the second power pin and the third power pin of the integrated circuit chip IC are all electrically connected to the power trace. That is to say, the printed circuit board shown in FIG.
  • the 7 includes a first power signal conduction path d1, a second power signal conduction path d2 and a third power signal conduction path d3, which respectively connect the first conductive part P1 and the third power signal conduction path d3.
  • the two conductive parts P2 and the third conductive part P3 are connected to the power traces, and each of the first power signal conduction path d1, the second power signal conduction path d2 and the third power signal conduction path d3 extends along The thickness direction of the circuit board extends to the bottom conductive layer 705, thereby reducing noise interference between different circuit modules connected to the first power pin, the second power pin and the third power pin in the integrated circuit chip IC.
  • the first power signal conduction path d1, the second power signal conduction path d2 and the third power signal conduction path d3 are electrically connected to the bottom conductive layer 705 and are insulated from each other between the intermediate conductive layers.
  • the electronic device further includes at least one capacitor connected in parallel between the ground trace and the power trace.
  • Figure 7 schematically shows three capacitors C1, C2 and C3.
  • the first power pin, the second power pin and the third power pin connection of the integrated circuit chip to the first conductive part, the second conductive part and the third conductive part of the printed circuit board can be regarded as connecting to the integrated circuit chip respectively.
  • Three voltage nodes powered by different internal circuit modules, the first power pin, the second power pin and the third power pin of the integrated circuit chip are respectively connected through the first power signal conduction path d1 and the second power signal conduction path Path d2 and the third power signal conduction path d3 are electrically connected to the power traces. Therefore, the filtering effect of the capacitors connected in parallel between the ground traces and the power traces can actually be shared by the aforementioned three voltage nodes and reduce Impedance at each voltage node.
  • the integrated circuit chip IC is disposed on a first side of the printed circuit board, and the at least one capacitor The device is arranged on a second side of the printed circuit board that is opposite to the first side.
  • the first side is the side close to the top conductive layer 701 of the printed circuit board.
  • FIG. 7 does not show other structures of the printed circuit board that are less relevant to the technical solution of the present application, such as solder resist layers.
  • the integrated circuit chip includes a first ground pin and a second ground pin
  • the printed circuit board further includes a first ground signal conduction path and a second ground signal conduction path, and the third ground signal conduction path
  • a power signal conduction path, the second power signal conduction path, the first ground signal conduction path and the second ground signal conduction path are respectively connected from the first power supply pin and the second ground signal conduction path.
  • the power pin, the first ground pin and the second ground pin extend along the thickness direction of the printed circuit board to the second side of the printed circuit board, and the at least one capacitor includes a capacitor connected to the a first capacitor between the first power supply signal conduction path and the first ground signal conduction path, and a first capacitor connected between the second power supply signal conduction path and the second ground signal conduction path Second capacitor.
  • the printed circuit board can include more pins and more signal conduction paths to ground.
  • FIG. 7 shows a first ground signal conduction path e1, a second ground signal conduction path e2, and a third ground signal conduction path e3.
  • the path e3 extends from the first power pin, the second power pin, the third power pin, the first ground pin, the second ground pin and the third ground pin respectively along the thickness direction of the printed circuit board to Second side of the PCB.
  • At least one capacitor connected in parallel between the voltage trace and the ground trace includes a first capacitor C1 connected between the first power signal conduction path d1 and the first ground signal conduction path e1, a first capacitor C1 connected between the second power signal conduction path d1 and a first ground signal conduction path e1.
  • a second capacitor C2 between the conductive path d2 and the second ground signal conductive path e2, and a third capacitor C3 connected between the third power signal conductive path d3 and the third ground signal conductive path e3.
  • the electronic device further includes a voltage converter, a voltage output terminal of the voltage converter is electrically connected to the power trace in the printed circuit board.
  • voltage converters include, but are not limited to, rectifiers, DC choppers, and combinations of rectifiers and DC choppers.
  • the voltage converter can convert the external power supply voltage of the electronic device into the appropriate voltage required for the operation of the integrated circuit chip.
  • a voltage converter is arranged on said first side of said printed circuit board. That is, like the integrated circuit chip, the voltage converter is also mounted (for example, by soldering) on the first side of the printed circuit board.
  • a printed circuit board of an electronic device includes 12 layers of conductive layers arranged in a stacked manner. layer, each of the aforementioned power signal conduction paths extends to the bottom conductive layer (the 12th conductive layer).
  • the power pin of an integrated circuit chip can be considered as the voltage node that supplies power to the integrated circuit chip.
  • Figure 8 illustrates the impedance curve at the voltage node when applying the different technical solutions described herein to power an integrated circuit chip.
  • the impedance at the above-mentioned voltage node can be understood numerically as the voltage at the voltage node when no current is provided to other voltage nodes and only unit current is injected at the above-mentioned voltage node.
  • This impedance may also be referred to herein as the self-impedance of the voltage node.
  • FIG. 8 illustrates the impedance curve at a voltage node when the electronic device applies the solution 1 and solution 2 described herein and the technical solution of the embodiment illustrated in FIG. 7 (referred to as solution 3 in this article) respectively.
  • curves 8a, 8b and 8c in Figure 8 respectively represent the impedance of a certain voltage node at different frequencies when scheme one, scheme two and scheme three are applied.
  • Figure 9 illustrates the impedance curve at another voltage node when the electronic device applies scheme one, scheme two and scheme three described in this article respectively.
  • curves 9a, 9b and 9c in Figure 9 respectively represent the impedance of the other voltage node at different signal frequencies in the case of applying scheme one, scheme two and scheme three.
  • Figure 10 illustrates the isolation between the above-mentioned different voltage nodes when using options one, two and three respectively.
  • the isolation here is used to characterize different voltage nodes (i.e., different power pins of integrated circuit chips). ).
  • V1 represents the amplitude of the AC signal applied at the first voltage node of the two voltage nodes
  • V2 represents the amplitude of the AC signal applied at the first voltage node at the second voltage node of the two voltage nodes. Amplitude of AC signal. Therefore, a smaller value of isolation L means better isolation between two voltage nodes.
  • curves 10a, 10b and 10c in Figure 10 respectively represent the isolation between two voltage nodes in the case of applying scheme one, scheme two and scheme three.
  • electronic equipment using Scheme 1 and Scheme 3 can achieve good suppression of high-frequency noise between nodes with different voltages. Therefore, electronic equipment using Scheme 3 can ensure a strong flow capacity of the power traces in the printed circuit board, and at the same time can better suppress noise interference between different voltage nodes (different power pins of integrated circuit chips).

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Abstract

本申请实施例提供一种印刷电路板和包括印刷电路板的电子设备。印刷电路板包括：多个导电层；至少一个绝缘层。多个导电层包括用于连接集成电路芯片的多个引脚的顶导电层，顶导电层所包括的第一导电部分和第二导电部分分别用于连接集成电路芯片的多个引脚中的第一电源引脚和第二电源引脚，多个导电层包括向集成电路芯片传输电源信号的电源走线，印刷电路板所包括的第一电源信号导通路径和第二电源信号导通路径分别将第一导电部分和第二导电部分电连接至电源走线，以使第一导电部分和第二导电部分接收同一电源信号。第一电源信号导通路径和第二电源信号导通路径中的每个至少穿过至少一个绝缘层中最靠近顶导电层的第一绝缘层。

Description

印刷电路板和包括印刷电路板的电子设备
相关申请的交叉引用
本公开要求在2022年07月27日提交中国专利局、申请号为202210892660.X、名称为“印刷电路板和包括印刷电路板的电子设备”的中国专利申请，以及在2022年07月27日提交中国专利局、申请号为202221953984.1、名称为“印刷电路板和包括印刷电路板的电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本申请涉及电子电路技术领域，具体地，涉及一种印刷电路板和包括该印刷电路板的电子设备。
背景技术
得益于半导体技术和电子技术的快速发展，集成电路芯片的集成程度也越来越高。相应地，集成电路芯片包括数量越来越多的电路模块，这些不同的电路模块通常具有各自独立的功能，上述的电路模块也称为IP核。为了使得集成电路芯片内的各个电路模块正常运行实现相应的功能，需要向电路模块提供相应的电源电压。因此，集成电路芯片设置在印刷电路板上，集成电路芯片的电源引脚与印刷电路板中的电源走线电连接，从而集成电路芯片可以经由印刷电路板接收相应的电源电压。
发明内容
本申请的一些实施例提供了一种印刷电路板，利用该印刷电路板，至少可以降低集成电路芯片运行时集成电路芯片中不同电路模块之间的噪声干扰，即使这些不同的电路模块接收到的电源信号相同。
根据本申请的实施例提供的印刷电路板包括：多个导电层；以及至少一个绝缘层，所述至少一个绝缘层中的各个绝缘层分别位于所述多个导电层中相邻的导电层之间。所述多个导电层包括用于连接集成电路芯片的多个引脚的顶导电层，所述顶导电层包括第一导电部分和第二导电部分,所述第一导电部分和所述第二电部分分别用于连接所述集成电路芯片的所述多个引脚中的第一电源引脚和第二电源引脚。所述多个导电层包括向所述集成电路芯片传输电源信号的电源走线，所述印刷电路板包括第一电源信号导通路径 和第二电源信号导通路径，所述第一电源信号导通路径和所述第二电源信号导通路径分别将所述第一导电部分和所述第二导电部分电连接至所述电源走线，以使得所述第一导电部分和所述第二导电部分接收同一电源信号。所述第一电源信号导通路径和所述第二电源信号导通路径中的每个至少穿过所述至少一个绝缘层中最靠近所述顶导电层的第一绝缘层。
在一些实施例中，所述多个导电层还包括底导电层和至少一个中间导电层，所述底导电层、至少所述一个中间导电层和所述顶导电层沿着所述印刷电路板的厚度方向依次层叠，所述至少一个中间导电层包括所述电源走线，所述第一电源信号导通路径和所述第二电源信号导通路径分别从所述第一导电部分和所述第二导电部分延伸至所述电源走线。
在一些实施例中，所述印刷电路板包括分别从所述第一导电部分和所述第二导电部分延伸至所述电源走线的第一盲孔和第二盲孔，所述第一到路径和所述第二电源信号导通路径分别包括所述第一盲孔和所述第二盲孔。
在一些实施例中，所述多个导电层还包括底导电层和至少一个中间导电层，所述底导电层、至少所述一个中间导电层和所述顶导电层沿着所述印刷电路板的厚度方向依次层叠，所述底导电层包括所述电源走线，所述第一电源信号导通路径和所述第二电源信号导通路径分别从所述第一导电部分和所述第二导电部分延伸至所述电源走线。
在一些实施例中，所述印刷电路板包括分别从所述第一导电部分和所述第二导电部分延伸至所述电源走线的第一通孔和第二通孔，所述第一电源信号导通路径和所述第二电源信号导通路径分别包括所述第一通孔和所述第二通孔。
在一些实施例中，所述顶导电层还包括第三导电部分，所述第三导电部分用于连接所述集成电路芯片的所述多个引脚中的第三电源引脚，所述印刷电路板还包括第三电源信号导通路径，所述第三电源信号导通路径将所述第三部分电连接至所述电源走线，以使所述第一导电部分、所述第二导电部分和所述第三导电部分接收同一电源信号。
本申请的另一实施例提供了一种电子设备，包括如前述实施例中任一实施例所述的印刷电路板和集成电路芯片，所述集成电路芯片包括用于接收相同电压水平的电源信号的第一电源引脚和第二电源引脚，所述第一电源引脚和所述第二电源引脚分别连接至所述印刷电路板的顶导电层中的第一导电部分和第二导电部分。
在一些实施例中，所述印刷电路板的所述多个导电层包括接地走线，所述电子设备 还包括并联在所述接地走线和所述电源走线之间的至少一个电容器。
在一些实施例中，所述集成电路芯片布置在所述印刷电路板的第一侧，所述至少一个电容器布置在所述印刷电路板的与所述第一侧正对的第二侧。
在一些实施例中，所述集成电路芯片还包括第一接地引脚和第二接地引脚，所述印刷电路板还包括第一接地信号导通路径和第二接地信号导通路径，所述第一电源信号导通路径、所述第二电源信号导通路径、所述第一接地信号导通路径和所述第二接地信号导通路径分别从所述第一电源引脚、所述第二电源引脚、所述第一接地引脚和所述第二接地引脚沿着所述印刷电路板的厚度方向延伸至所述印刷电路板的第二侧，所述至少一个电容器包括连接在所述第一电源信号导通路径和所述第一接地信号导通路径之间的第一电容器、以及连接在所述第二电源信号导通路径和所述第二接地信号导通路径之间的第二电容器。
在一些实施例中，电子设备还包括电压变换器，所述电压变换器的电压输出端电连接至所述印刷电路板中的所述电源走线。
在一些实施例中，所述电压变换器布置在所述印刷电路板的所述第一侧。
以上概述了本申请的一些实施例，基于一些实施例的组合以及不同实施例中特征的组合可以获得另外的不同实施例，这些不同实施例同样属于本申请的保护范围。
附图说明
现在将更详细并且参考附图来描述本申请的实施例。能够理解到的是，附图中示出的印刷电路板和包括该印刷电路板的电子设备的截面图或俯视图仅示意性地表示印刷电路板或电子设备的与本申请实施例所描述的技术方案相关的部分结构或部分元件，并不代表实际的产品结构。
图1示意性地图示了根据本申请的一个实施例的印刷电路板的局部俯视图、以及印刷电路板和向印刷电路板供电的电源之间的电连接；
图2示意性地图示了根据本申请的另一实施例的印刷电路板的局部俯视图、以及印刷电路板和向印刷电路板供电的电源之间的电连接；
图3示意性地图示了根据本申请的另一实施例的印刷电路板的局部俯视图、以及印刷电路板和向印刷电路板供电的电源之间的电连接；
图4图示了根据本申请的又一实施例的印刷电路板的示意性局部截面图；
图5图示了根据本申请的又一实施例的印刷电路板的示意性局部截面图；
图6图示了根据本申请的又一实施例的印刷电路板的示意性局部截面图；
图7图示了根据本申请的又一实施例的电子设备的示意性局部截面图；
图8和图9分别图示了电子设备分别应用本文描述的方案一、方案二以及方案三时两个电压节点处的阻抗曲线；
图10图示了电子设备分别应用分别采用方案一、方案二和方案三的情况下的不同电压节点之间的隔离度。
具体实施方式
下面的描述提供了本申请的各种实施例的特定细节，以便本领域的技术人员能够充分理解和实施本申请的各种实施例。在某些情况下，本申请并没有示出或详细描述一些本领域熟知的结构或功能，以避免这些不必要的描述使对本申请的实施例的描述模糊不清。本申请的技术方案可以体现为许多不同的形式和目的，并且不应局限于本文所阐述的实施例。提供这些实施例是为了使得本申请的技术方案清楚完整，但所述实施例并不限定本专利申请的保护范围。
在此，首先对本申请实施例中涉及的部分用语进行说明，以便于本领域技术人员理解。
本文提到的“电子设备”至少包括印刷电路板和连接在印刷电路板上的集成电路芯片，也就是说，“电子设备”包括印刷电路板和集成电路芯片的组合体，电子设备也可以包括另外的机械部件或电气元件。电子设备的示例包括但不限于主板、显卡、计算机、平板电脑、移动通信装置等。
集成电路芯片中的各个电路模块(IP核)需要相应的电源电压以实现相应的功能。本申请的发明人认识到，不同电路模块对电源信号的噪声有不同的要求。例如，即使两个不同的电路模块所需要的电源电压(工作电压)的电压值相同，对电源信号中的纹波信号的要求也不同。同时，不同电路模块运行时产生的电源噪声信号也可能存在较大差异。因此，即使在不同电路模块所需的工作电压的电压值相同的情况下，也期望不同电路模块的电源信号之间较低的耦合度。
根据本申请的一个实施例，降低集成电路芯片不同电路模块的电源信号之间较低的耦合度的技术方案是针对集成电路芯片中的不同电路模块在印刷电路板上设计彼此独立的多个电源走线。图1示出了该技术方案的示例。如图1所示，至少采用两个电源(例 如，第一电压变换器10、第二电压变换器20)向印刷电路板PB提供输出电压。相应地，印刷电路板PB中至少存在彼此独立的第一电源走线和第二电源走线，分别接收两个电源输出的电压。图1中的圆点用于示意性地表示印刷电路板PB与集成电路芯片的引脚连接的区域，即圆点可对应于集成电路芯片的引脚。第一电源10的输出端和集成电路芯片的一部分引脚与印刷电路板PB中的第一电源走线(图1中未示出)电连接，从而形成第一电源信号传输路径，第二电源20的输出端和集成电路芯片的另一部分引脚与印刷电路板PB中的第二电源走线图1中未示出)电连接，从而形成第二电源信号传输路径。在图1中，第一电源信号传输路径和第二电源信号传输路径分别被标识为100和200。由于采用两个独立的电源向印刷电路板和集成电路芯片供电，印刷电路板中的第一电源走线和第二电源走线也彼此独立和隔离，所以向集成电路芯片的各个电路模块供电的各电源信号传输路径彼此之间的干扰噪声较小。然而，为集成电路芯片中工作电压相同的各个电路模块仍分别设置对应的独立电源，这导致电子设备成本的增加。而且，在印刷电路板中设置彼此隔离和独立的多个电源走线，这可能限制印刷电路板内的布线空间，导致包括电源走线在内的一些信号走线的通流能力较弱。为了增强信号走线的通流能力，需要增加印刷电路板内的导电层的数量，但这进一步导致印刷电路板的制作成本的增加。
图2图示了根据本申请的另一实施例的技术方案，与图1所示的技术方案相比，图2的技术方案只采用单个的电源10为印刷电路板上的集成电路芯片内工作电压相同的电路模块供电。如图2所示，电源10的电压输出路径上设置有噪声抑制器件30，利用噪声抑制器件30可以基于电源10的输出形成两路电源信号。图2中所示的印刷电路板PB与图1中所示的印刷电路板相同，第一电源信号传输路径和第二电源信号传输路径同样分别被标识为100和200。噪声抑制器件30的示例包括但不限于磁珠、零欧姆电阻等。虽然第一电源信号传输路径和第二电源信号传输路径传输的电源信号的电压水平相同，但是，印刷电路板PB中仍需要设置彼此隔离和独立的多个电源走线，这同样不能缓解增加印刷电路板内的信号走线的通流能力和控制印刷电路板的制作成本之间的矛盾。
在本文中，以上结合图1和图2所说明的为集成电路芯片供电的技术方案可以被称为第一类技术方案(方案一)。在第一类技术方案中，在印刷电路板内设置彼此独立和隔离的多条电源走线，当集成电路芯片运行时，该情形等同于印刷电路板内包括多个彼此独立的电源信号，分别向集成电路芯片的不同电源引脚提供电压，这有利于降低集成电路芯片在运行时不同电源引脚之间的噪声干扰，进而提升集成电路芯片的工作性能。然 而，如前所述，这类技术方案导致印刷电路板中的一些信号走线的通流能力较弱，需要增加印刷电路板的导电层的层数才能提升信号走线的通流能力，这导致印刷电路板的成本的增加。
一种不增加印刷电路板的成本的解决方案是让集成电路芯片中可以接收相同电压水平的不同电源引脚在印刷电路板的表层导电层相互连接，这里的“表层导电层”指的是集成电路芯片安装至印刷电路板时印刷电路板中距离集成电路芯片最近的导电层，其也可以理解成下文中提到的“顶导电层”。印刷电路板内不针对接收相同电压水平的不同电源引脚设置彼此独立和隔离的多个电源走线，这时，可以采用单个的电源10为集成电路芯片供电。可以借助图3来说明该技术方案的示例。在该技术方案中，针对集成电路芯片的接收相同电压水平的多个电源引脚，印刷电路板实际上只包括单个的电源信号传输路径。如图3所示，电源10的输出端为集成电路芯片的不同电源引脚供电，与电源10的输出端连接的各个电源引脚实际上是经由同一电源信号传输路径100彼此连通的。在本段结合图3说明的技术方案可被称为方案二，在该情形中，印刷电路板中包括电源走线在内的信号走线的布线空间受到的限制相对较小，因此有利于增强印刷电路板的信号走线的通流能力，但是集成电路芯片在运行时不同电源引脚之间的噪声干扰较明显，可能导致集成电路芯片运行性能的降低。
本申请的另一实施例提供了一种印刷电路板，试图降低集成电路芯片在运行时不同电源引脚之间的噪声干扰，同时实现印刷电路板的制作成本的控制和保证印刷电路板中的信号走线的较强的通流能力。
根据该实施例提供的印刷电路板包括多个导电层以及至少一个绝缘层，所述至少一个绝缘层中的各个绝缘层分别位于所述多个导电层中相邻的导电层之间。图4示意性地示出了印刷电路板的局部截面图，如图4所示，印刷电路板包括多个导电层401、402、403、404、以及位于各导电层中相邻的导电层之间的绝缘层。印刷电路板的多个导电层包括用于连接集成电路芯片的多个引脚的顶导电层401，顶导电层401包括第一导电部分401a和第二导电部分401b,第一导电部分401a和第二电部分401b分别用于连接集成电路芯片的所述多个引脚中的第一电源引脚和第二电源引脚(图4中未示出)。所述多个导电层包括向集成电路芯片传输电源信号的电源走线402，印刷电路板包括第一电源信号导通路径d1和第二电源信号导通路径d2，第一电源信号导通路径d2和第二电源信号导通路径d2分别将第一导电部分401a和第二导电部分401b电连接至电源走线402，以使得所 述第一导电部分401a和第二导电部分401b接收同一电源信号。如图4所示，第一电源信号导通路径d1和第二电源信号导通路径d2中的每个至少穿过所述至少一个绝缘层中最靠近所述顶导电层的第一绝缘层410。
能够理解到的是，图4所示的截面图仅用于示意性地表示印刷电路板中与本申请上述实施例涉及的技术特征，而省略了其它的与上述实施例中的技术特征无关的部件或结构。例如，印刷电路板的还可包括位于顶导电层401上的阻焊层以及位于底导电层404下方的阻焊层。图4虽然示出了包括四个导电层的印刷电路板，但是，印刷电路板所包含的导电层的数目并不受此限制。另外，图4所示的各个导电层结构并不代表实际的印刷电路板的产品中的导电层，一些导电层可以是连续的板状结构，也可以是断续的图案化结构。
当集成电路芯片连接于图4所示的印刷电路板时，顶导电层401中的第一导电部分401a和第二电部分401b可分别与集成电路芯片用于接收相同电压水平的两个不同电源引脚(例如，第一电源引脚和第二电源引脚)焊接。集成电路芯片的第一电源引脚和第二电源引脚分别经由穿过第一绝缘层410的第一电源信号导通路径d1和第二电源信号导通路径d2与电源走线402电连接。也就是说，第一电源引脚和第二电源引脚电连接至同一电源走线402，但是，第一电源信号导通路径d1和第二电源信号导通路径d2的等效电感可以抑制至少一部分噪声信号，降低集成电路芯片中与第一电源引脚和第二电源引脚连接的不同电路模块之间的信号干扰。同时，针对接收相同电压水平的两个不同电源引脚，并没有设置在物理上彼此隔离的多个电源走线，即相对于前述的方案一，印刷电路板内包括电源走线的信号走线的空间布局受到的约束较小，有利于保证信号走线较强的通流能力。
图5示意性地示出了根据本申请的另一实施例的印刷电路板的局部截面图。图5所示的实施例与图4所示的实施例大致相同，二者主要的区别在于印刷电路板所包括的导电层的数目以及第一电源信号导通路径的长度、第二电源信号导通路径的长度方面的差别。在图4和图5所示的实施例中，印刷电路板的多个导电层包括底导电层404/505、和至少一个中间导电层，所述底导电层404/505、所述至少一个中间导电层和所述顶导电层401/501沿着印刷电路板的厚度方向依次层叠，电源走线设402/504设置在所述至少一个中间导电层中，第一电源信号导通路径d1和第二电源信号导通路径d2分别从所述第一导电部分401a/501a和所述第二导电部分401b/501b延伸至所述电源走线402/504。与图4 所示的实施例相比，图5所示的印刷电路板中的第一电源信号导通路径d1和第二电源信号导通路径d2具有更长的长度。当集成电路芯片连接于图5所示的印刷电路板时，顶导电层501中的第一导电部分501a和第二电部分501b可分别与集成电路芯片用于接收相同电压水平的两个不同电源引脚(例如，第一电源引脚和第二电源引脚)焊接，第一电源引脚和第二电源引脚之间的信号导通路径更长，从而能够进一步降低集成电路芯片中与第一电源引脚和第二电源引脚连接的不同电路模块之间的信号干扰。
如图4或图5所示，第一电源信号导通路径d1和第二电源信号导通路径d2并没有穿透印刷电路板的整个厚度，因此，所述印刷电路板包括分别从所述第一导电部分和所述第二导电部分延伸至所述电源走线的第一盲孔和第二盲孔，所述第一电源信号导通路径d1和所述第二电源信号导通路径d2分别包括所述第一盲孔和所述第二盲孔。第一盲孔和第二盲孔的内壁可涂覆有导电材料。
根据本申请的另外的实施例，如图6所示，印刷电路板的多个导电层包括顶导电层601、中间导电层602、603、604和底导电层605，底导电层605、中间导电层604、603、602和顶导电层601沿着印刷电路板的厚度方向依次层叠，底导电层605包括电源走线，第一电源信号导通路径和第二电源信号导通路径分别从顶导电层的第一导电部分601a和第二导电部分601b延伸至电源走线。在该实施例中，第一电源信号导通路径d1和第二电源信号导通路径d2穿过第一绝缘层610、各个中间导电层之间的绝缘层并与底导电层605的电源走线连接。与图5所示的实施例类似，第一电源信号导通路径d1和第二电源信号导通路径d2与各中间导电层之间是绝缘的。相比于图5所示的实施例，由于第一电源信号导通路径和第二电源信号导通路径分别从顶导电层的第一导电部分601a和第二导电部分601b延伸至底导电层的电源走线，当集成电路芯片的不同电源引脚连接至第一导电部分601a和第二导电部分601b时，上述不同电源引脚之间的信号导通路径更长，集成电路芯片中与上述不同电源引脚连接的不同电路模块之间的信号干扰可以进一步得到抑制。
在图6的实施例中，印刷电路板包括分别从第一导电部分601a和第二导电部分601b延伸至底导电层605的电源走线的第一通孔和第二通孔，第一电源信号导通路径d1和第二电源信号导通路径d2分别包括所述第一通孔和所述第二通孔。第一通孔和第二通孔的内壁可涂覆有导电材料。
在以上结合图4至图6描述的印刷电路板的实施例中，仅提到位于某一导电层中的 电源走线，但是，这并不意味着印刷电路板的电源走线只能分布于单个的导电层中。根据印刷电路板的设计需求，电源走线可以分布于不同的导电层，同一电源走线位于不同导电层中的不同部分可以经由绝缘层中的过孔相互连接。而且，图4至图6实施例中提到的单个单元走线是针对集成电路芯片中接收相同电压水平的电源引脚设置的。在集成电路芯片包括接收不同电压水平的多个电源引脚的情形中，印刷电路板可包括彼此隔离和独立的多条电源走线。
图4至图6示意性地示出了顶导电层的第一导电部分和第二导电部分分别经由第一电源信号导通路径和第二电源信号导通路径连接至电源走线。在其他实施例中，顶导电层还包括第三导电部分，第三导电部分用于连接所述集成电路芯片的所述多个引脚中的第三电源引脚，印刷电路板还包括第三电源信号导通路径，所述第三电源信号导通路径将所述第三部分电连接至所述电源走线，以使所述第一导电部分、所述第二导电部分和所述第三导电部分接收同一电源信号。顶导电层可以包括彼此独立的任意数量的导电部分，分别用于连接集成电路芯片接收同一电压水平的电源信号的不同电源引脚。
本申请的另外的实施例提供了一种电子设备，该电子设备包括如前述实施例中任一实施例所述的印刷电路板和集成电路芯片，所述集成电路芯片包括用于接收相同电压水平的电源信号的第一电源引脚和第二电源引脚，所述第一电源引脚和所述第二电源引脚分别连接至所述印刷电路板的顶导电层中的第一导电部分和第二导电部分。
在该电子设备中，集成电路芯片的第一电源引脚和第二电源引脚分别经由至少穿过印刷电路板的第一绝缘层的第一电源信号导通路径和第二电源信号导通路径与电源走线电连接。第一电源信号导通路径和第二电源信号导通路径增加了第一电源引脚和第二电源引脚之间的信号传输路径的等效电感值，从而可以抑制至少一部分噪声信号，降低集成电路芯片中与第一电源引脚和第二电源引脚连接的不同电路模块之间的干扰。同时，不必在印刷电路板中设置用于接收相同电压水平而在物理上彼此隔离的多条电源走线，相应地，印刷电路板内包括电源走线的信号走线的空间布局受到的约束较小，有利于保证较强信号走线较强的通流能力。同时，仅需要一个电压源(例如，电压变换器)向集成电路芯片的第一电源引脚和第二电源引脚供电，避免电子设备元器件成本的增加。
图7示意性地示出了根据本申请的一个实施例提供的电子设备的局部截面图。该电子设备中的印刷电路板的结构与参照图3说明的方案二的印刷电路板的结构的主要区别在于接收相同电压水平的不同电源引脚在印刷电路板中与电源走线相互连接的位置不同， 图3所示的印刷电路板的俯视图也可以用来示意性地表示该电子设备中的印刷电路板的俯视图。图7所示的局部截面图可以视为沿着图3中的线A1-A2获得的。
图7示意性地示出了布置在印刷电路板上的集成电路芯片IC，并图示了顶导电层701中的多个导电部分，包括第一导电部分P1、第二导电部分P2、第三导电部分P3、第四导电部分G1、第五导电部分G2和第六导电部分G3。第一导电部分P1、第二导电部分P2和第三导电部分P3分别与集成电路芯片IC的用于接收相同电压水平的第一电源引脚、第二电源引脚和第三电源引脚连接，第四导电部分G1、第五导电部分G2和第六导电部分G3分别与集成电路芯片IC的用于接收参考地电压的第一接地引脚、第二接地引脚和第三接地引脚连接。如图7所示，印刷电路板包括第一绝缘层710、中间导电层702、703、704以及底导电层704。印刷电路板的多个导电层包括接地走线和电源走线，接地走线位于中间导电层704中，电源走线位于底导电层705中，集成电路芯片IC的第一接地引脚、第二接地引脚和第三接地引脚均与接地走线电连接，集成电路芯片IC的第一电源引脚、第二电源引脚和第三电源引脚均与电源走线电连接。也就是说，图7所示的印刷电路板包括第一电源信号导通路径d1、第二电源信号导通路径d2和第三电源信号导通路径d3，它们分别将第一导电部分P1、第二导电部分P2、第三导电部分P3连接至电源走线，且第一电源信号导通路径d1、第二电源信号导通路径d2和第三电源信号导通路径d3中的每个沿着延伸电路板的厚度方向延伸至底导电层705，从而可以减少集成电路芯片IC中与第一电源引脚、第二电源引脚和第三电源引脚连接的不同电路模块之间的噪声干扰。第一电源信号导通路径d1、第二电源信号导通路径d2和第三电源信号导通路径d3与底导电层705电连接，而与各个中间导电层相互绝缘。根据本申请的该实施例，电子设备还包括并联在接地走线和所述电源走线之间的至少一个电容器。图7示意性地示出了三个电容器C1、C2和C3。
集成电路芯片与印刷电路板的第一导电部分、第二导电部分和第三导电部分连接的第一电源引脚、第二电源引脚和第三电源引脚连接可分别视为向集成电路芯片内部的不同电路模块供电的三个电压节点，集成电路芯片的第一电源引脚、第二电源引脚和第三电源引脚分别通过第一电源信号导通路径d1、第二电源信号导通路径d2和第三电源信号导通路径d3与电源走线电连接，所以，并联在接地走线和电源走线之间的电容器的滤波效果实际上可以为前述的三个电压节点共享，并降低每个电压节点处的阻抗。
在一些实施例中，集成电路芯片IC布置在印刷电路板的第一侧，所述至少一个电容 器布置在所述印刷电路板的与所述第一侧正对的第二侧。在图7所示的实施例中，第一侧即为靠近印刷电路板的顶导电层701的一侧。当然，图7中没有示出印刷电路板与本申请的技术方案不太相关的其它结构，例如阻焊层等。
根据本申请的一些实施例，集成电路芯片包括第一接地引脚和第二接地引脚，所述印刷电路板还包括第一接地信号导通路径和第二接地信号导通路径，所述第一电源信号导通路径、所述第二电源信号导通路径、所述第一接地信号导通路径和所述第二接地信号导通路径分别从所述第一电源引脚、所述第二电源引脚、所述第一接地引脚和所述第二接地引脚沿着所述印刷电路板的厚度方向延伸至所述印刷电路板的第二侧，所述至少一个电容器包括连接在所述第一电源信号导通路径和所述第一接地信号导通路径之间的第一电容器、以及连接在所述第二电源信号导通路径和所述第二接地信号导通路径之间的第二电容器。当然，印刷电路板可以包括更多的接到引脚和更多的接地信号导通路径。例如，图7示出了第一接地信号导通路径e1、第二接地信号导通路径e2和、第三接地信号导通路径e3。第一电源信号导通路径d1、第二电源信号导通路径d2、第三电源信号导通路径d3、第一接地信号导通路径e1、第二接地信号导通路径e2和第三接地信号导通路径e3分别从第一电源引脚、第二电源引脚、第三电源引脚、第一接地引脚、第二接地引脚和第三接地引脚沿着印刷电路板的厚度方向延伸至印刷电路板的第二侧。并联在电压走线和接地走线之间的至少一个电容器包括连接在第一电源信号导通路径d1和第一接地信号导通路径e1之间的第一电容器C1、连接在第二电源信号导通路径d2和第二接地信号导通路径e2之间的第二电容器C2、以及连接在第三电源信号导通路径d3和第三接地信号导通路径e3之间的第三电容器C3。
在一些实施例中，电子设备还包括电压变换器，所述电压变换器的电压输出端电连接至所述印刷电路板中的所述电源走线。电压变换器的示例包括但不限于整流器、直流斩波器以及整流器和直流斩波器的组合。电压变换器可以将电子设备的外部电源电压变换为适于集成电路芯片工作所需要的适当电压。
在一些实施例中，电压变换器布置在所述印刷电路板的所述第一侧。也就是说，与集成电路芯片一样，电压变换器也安装(例如，通过焊接)在印刷电路板的第一侧。
图4至图7中所示的印刷电路板的各个导电层并不代表实际的印刷电路板产品的结构，而只是用于示意性地表示各导电层与电源信号导通路径和接地信号导通路径之间的关联。根据本申请的一个实施例，电子设备的印刷电路板包括依次层叠布置的12层导电 层，前述的各个电源信号导通路径均延伸至底导电层(第12层导电层)。如前所述，集成电路芯片的电源引脚可视为向集成电路芯片供电的电压节点。图8图示了在应用本文描述的不同技术方案为集成电路芯片供电时电压节点处的阻抗曲线。上述电压节点处的阻抗在数值上可以理解为在不向其它电压节点提供电流而仅在上述电压节点处注入单位电流时该电压节点处的电压。该阻抗在本文中也可称为电压节点的自阻抗。图8图示了电子设备分别应用本文中描述的方案一、方案二以及图7所图示的实施例的技术方案(在本文中称为方案三)时一个电压节点处的阻抗曲线。具体地，图8中的曲线8a、8b和8c分别表示在应用方案一、方案二和方案三的情况下某一电压节点的不同频率下的阻抗。图9图示了电子设备分别应用本文中描述的方案一、方案二以及方案三时另一电压节点处的阻抗曲线。具体地，图9中的曲线9a、9b和9c分别表示在应用方案一、方案二和方案三的情况下该另一电压节点的不同信号频率下的阻抗。
在图8和图9中，曲线8b和8c彼此近似重合，曲线9b和9c彼此近似重合，为了区分起见，曲线8c和9c均以虚线形式示出。从图8和图9可以看出，在应用方案二和方案三的情况下，电子设备的电压节点的阻抗特性基本接近，但是，电子设备的电压节点的阻抗在采用方案一的情况下变得较大，数值接近于应用方案二和方案三情况下的两倍。因此，这表明采用本文提供的方案三的印刷电路板中的电源走线具有较强的通流能力。
图10图示了分别采用方案一、方案二和方案三的情况下上述的不同电压节点之间的隔离度，这里的隔离度用于表征不同电压节点(即，集成电路芯片的不同电源引脚)之间的噪声隔离能力。在一个实施例中，两个电压节点隔离度L可以表示为L＝20*lg(V2/V1)。V1表示在两个电压节点中的第一电压节点处施加的交流信号的幅值，V2表示由于在第一电压节点处施加的交流信号而在两个电压节点中的第二电压节点处产生的交流信号的幅值。因此，隔离度L的值越小意味着两个电压节点的隔离度越好。具体地，图10中的曲线10a、10b和10c分别表示在应用方案一、方案二和方案三的情况下两个电压节点之间的隔离度。从图10可以看出，采用方案一和方案三的电子设备可以实现不同电压节点之间高频噪声的良好抑制。因此，采用方案三的电子设备能够保证印刷电路板中的电源走线较强的通流能力，同时可以较好地抑制不同电压节点(集成电路芯片的不同电源引脚)之间的噪声干扰。
以上描述了本申请的一些实施例，“第一”、“第二”、“第三”等术语在本文中可以用 来描述各种设备、元件、部件或部分，但是这些设备、元件、部件或部分不应当由这些术语限制，仅表示名称方面的区分。此外，本文提到的“电连接”包括“直接连接”或“间接连接”。以上已经结合一些实施例描述了本申请的技术方案，但是本申请的保护范围并不限于在本文中所阐述的实施例的特定形式，本申请的范围由所附权利要求来定义。

Claims (12)

  1. 一种印刷电路板，包括：
    多个导电层；以及
    至少一个绝缘层，所述至少一个绝缘层中的各个绝缘层分别位于所述多个导电层中相邻的导电层之间，
    其中所述多个导电层包括用于连接集成电路芯片的多个引脚的顶导电层，所述顶导电层包括第一导电部分和第二导电部分,所述第一导电部分和所述第二电部分分别用于连接所述集成电路芯片的所述多个引脚中的第一电源引脚和第二电源引脚，
    其中所述多个导电层包括向所述集成电路芯片传输电源信号的电源走线，所述印刷电路板包括第一电源信号导通路径和第二电源信号导通路径，所述第一电源信号导通路径和所述第二电源信号导通路径分别将所述第一导电部分和所述第二导电部分电连接至所述电源走线，以使得所述第一导电部分和所述第二导电部分接收同一电源信号，
    其中所述第一电源信号导通路径和所述第二电源信号导通路径中的每个至少穿过所述至少一个绝缘层中最靠近所述顶导电层的第一绝缘层。
  2. 根据权利要求1所述的印刷电路板，其中所述多个导电层还包括底导电层和至少一个中间导电层，所述底导电层、至少所述一个中间导电层和所述顶导电层沿着所述印刷电路板的厚度方向依次层叠，所述至少一个中间导电层包括所述电源走线，所述第一电源信号导通路径和所述第二电源信号导通路径分别从所述第一导电部分和所述第二导电部分延伸至所述电源走线。
  3. 根据权利要求2所述的印刷电路板，其中所述印刷电路板包括分别从所述第一导电部分和所述第二导电部分延伸至所述电源走线的第一盲孔和第二盲孔，所述第一到路径和所述第二电源信号导通路径分别包括所述第一盲孔和所述第二盲孔。
  4. 根据权利要求1所述的印刷电路板，其中所述多个导电层还包括底导电层和至少一个中间导电层，所述底导电层、至少所述一个中间导电层和所述顶导电层沿着所述印刷电路板的厚度方向依次层叠，所述底导电层包括所述电源走线，所述第一电源信号导通路径和所述第二电源信号导通路径分别从所述第一导电部分和所述第二导电部分延伸至所述电源走线。
  5. 根据权利要求2所述的印刷电路板，其中所述印刷电路板包括分别从所述第一导电部分和所述第二导电部分延伸至所述电源走线的第一通孔和第二通孔，所述第一电源 信号导通路径和所述第二电源信号导通路径分别包括所述第一通孔和所述第二通孔。
  6. 根据权利要求1-5中任一项所述的印刷电路板，其中所述顶导电层还包括第三导电部分，所述第三导电部分用于连接所述集成电路芯片的所述多个引脚中的第三电源引脚，所述印刷电路板还包括第三电源信号导通路径，所述第三电源信号导通路径将所述第三部分电连接至所述电源走线，以使所述第一导电部分、所述第二导电部分和所述第三导电部分接收同一电源信号。
  7. 一种电子设备，包括如权利要求1-6中任一项所述的印刷电路板和集成电路芯片，其中所述集成电路芯片包括用于接收相同电压水平的电源信号的第一电源引脚和第二电源引脚，所述第一电源引脚和所述第二电源引脚分别连接至所述印刷电路板的顶导电层中的第一导电部分和第二导电部分。
  8. 根据权利要求7所述的电子设备，其中所述印刷电路板的所述多个导电层包括接地走线，所述电子设备还包括并联在所述接地走线和所述电源走线之间的至少一个电容器。
  9. 根据权利要求8所述的电子设备，其中所述集成电路芯片布置在所述印刷电路板的第一侧，所述至少一个电容器布置在所述印刷电路板的与所述第一侧正对的第二侧。
  10. 根据权利要求9所述的电子设备，其中所述集成电路芯片还包括第一接地引脚和第二接地引脚，所述印刷电路板还包括第一接地信号导通路径和第二接地信号导通路径，
    其中所述第一电源信号导通路径、所述第二电源信号导通路径、所述第一接地信号导通路径和所述第二接地信号导通路径分别从所述第一电源引脚、所述第二电源引脚、所述第一接地引脚和所述第二接地引脚沿着所述印刷电路板的厚度方向延伸至所述印刷电路板的第二侧，
    其中所述至少一个电容器包括连接在所述第一电源信号导通路径和所述第一接地信号导通路径之间的第一电容器、以及连接在所述第二电源信号导通路径和所述第二接地信号导通路径之间的第二电容器。
  11. 根据权利要求10所述的电子设备，其中所述电子设备还包括电压变换器，所述电压变换器的电压输出端电连接至所述印刷电路板中的所述电源走线。
  12. 根据权利要求11所述的电子设备，其中所述电压变换器布置在所述印刷电路板的所述第一侧。
PCT/CN2023/109606 2022-07-27 2023-07-27 印刷电路板和包括印刷电路板的电子设备 WO2024022449A1 (zh)

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JP2006294769A (ja) * 2005-04-08 2006-10-26 Nec Corp 多層プリント配線基板
US20070144770A1 (en) * 2005-12-26 2007-06-28 Fujitsu Limited Printed wiring board including power supply layer and ground layer
CN102548185A (zh) * 2010-12-17 2012-07-04 佳能株式会社 印刷电路板
CN102792784A (zh) * 2011-03-10 2012-11-21 联发科技股份有限公司 高速应用的印刷电路板设计
CN114141743A (zh) * 2020-09-04 2022-03-04 英特尔公司 芯片组件
CN115209613A (zh) * 2022-07-27 2022-10-18 摩尔线程智能科技(北京)有限责任公司 印刷电路板和包括印刷电路板的电子设备

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JP2006294769A (ja) * 2005-04-08 2006-10-26 Nec Corp 多層プリント配線基板
US20070144770A1 (en) * 2005-12-26 2007-06-28 Fujitsu Limited Printed wiring board including power supply layer and ground layer
CN102548185A (zh) * 2010-12-17 2012-07-04 佳能株式会社 印刷电路板
CN102792784A (zh) * 2011-03-10 2012-11-21 联发科技股份有限公司 高速应用的印刷电路板设计
CN114141743A (zh) * 2020-09-04 2022-03-04 英特尔公司 芯片组件
CN115209613A (zh) * 2022-07-27 2022-10-18 摩尔线程智能科技(北京)有限责任公司 印刷电路板和包括印刷电路板的电子设备

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