TWI399649B - 用於提供不確定讀取資料等待時間之方法、集線器裝置、記憶體控制器及記憶體系統 - Google Patents

用於提供不確定讀取資料等待時間之方法、集線器裝置、記憶體控制器及記憶體系統 Download PDF

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TWI399649B
TWI399649B TW095143452A TW95143452A TWI399649B TW I399649 B TWI399649 B TW I399649B TW 095143452 A TW095143452 A TW 095143452A TW 95143452 A TW95143452 A TW 95143452A TW I399649 B TWI399649 B TW I399649B
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Kevin C Gower
Paul W Coteus
Robert B Tremaine
Warren E Maule
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G06F13/1657—Access to multiple memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers

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用於提供不確定讀取資料等待時間之方法、集線器裝置、記憶體控制器及記憶體系統
本發明係關於由一菊鏈通道連接至一記憶體控制器之集線器裝置組成的記憶體系統。將集線器裝置附接至或駐留在含有記憶體裝置的記憶體模組上。更特定言之，本發明係關於讀取資料之流程控制及由每一集線器裝置傳回至控制器之讀取資料的識別。
許多高效能計算性主記憶體系統使用由一或多個通道連接至一記憶體控制器之多個充分緩衝的記憶體模組。記憶體模組含有一集線器裝置及多個記憶體裝置。該集線器裝置充分緩衝在記憶體控制器與記憶體裝置之間的指令、位址及資料信號。使用一分級等待時間或位置依賴性等待時間技術來控制讀取資料的流程。在兩種情況下，記憶體控制器均能夠預測自記憶體模組請求之讀取資料的傳回時間且能夠排程指令以避免在讀取資料由每一記憶體模組合並至控制器介面上時發生的碰撞。
在一些情況下，記憶體控制器能夠發送一連同讀取指令一起的讀取資料延遲加法指令。此指示目標集線器裝置將額外延遲添加至讀取資料之傳回上以便簡化指令的發送及避免碰撞。在所有情況下，讀取資料必須按照其被請求的次序傳回。此外，總讀取資料等待時間必須完全可由記憶體控制器來預測。在執行時間操作期間，此兩項限制導致將額外間隙添加至自記憶體模組傳回之讀取資料的封包。
此將等待時間添加至平均讀取操作。此外，集線器不能夠使用不確定技術來比正常速度更快或更慢地將讀取資料傳回。此等技術包括(但不限於)局部地快取讀取資料、猜測性地讀取記憶體裝置、獨立地管理記憶體裝置位址頁、資料壓縮等。
為在實際工作負荷條件下最佳化平均讀取等待時間，且賦予高級集線器裝置之能力，需要允許記憶體模組於一不可預測之時間將讀取資料傳回至記憶體控制器的方法。必須以不會破壞讀取資料且允許記憶體控制器識別每一讀取資料封包的方式來完成此過程。因為集線器裝置將本端讀取資料合併至一級聯記憶體控制器通道上，所以藉由避免資料碰撞來防止資料破壞尤其複雜。
例示性實施例包括一用於提供不確定讀取資料等待時間之方法。該方法包括判定是否已接收到一本端資料封包。若已接收到一本端資料封包，則將該本端資料封包儲存至一緩衝器裝置中。該方法亦包括判定該緩衝器裝置是否含有一資料封包且判定一用於經由一上游通道將資料封包傳輸至一記憶體控制器之上游驅動器是否閒置。若該緩衝器含有一資料封包且該上游驅動器閒置，則將該資料封包傳輸至該上游驅動器。該方法進一步包括判定是否已接收到一上游資料封包。該上游資料封包呈一包括一訊框開始指示符及一識別標籤之訊框格式，該記憶體控制器使用該訊框格式以使該上游資料封包與其對應的讀取指令相關聯。若已接收到一上游資料封包且該上游驅動器並非閒置，則將該上游資料封包儲存至該緩衝器裝置中。若已接收到一上游資料封包且該緩衝器裝置不含有一資料封包且該上游驅動器閒置，則將該上游資料封包傳輸至該上游驅動器。若該上游驅動器並非閒置，則將進程中之任何資料封包繼續傳輸至該上游驅動器。
例示性實施例包括在一記憶體系統中之一集線器裝置。該集線器裝置包括一用於接收資料封包之裝置、一用於經由一上游通道將資料封包傳輸至一記憶體控制器之上游驅動器，及一包括用於促進不確定讀取資料等待時間之指令的機件。用於接收資料封包之裝置包括一上游接收器，其用於自一下游集線器裝置接收上游資料封包；及一記憶體介面，其用於自一本端儲存裝置接收本端資料封包。每一資料封包呈一包括一訊框開始指示符及一識別標籤之訊框格式，一記憶體控制器使用該訊框格式以使資料封包與其對應的讀取指令相關聯。該機件上之指令促進判定是否已接收到一本端資料封包。若已接收到一本端資料封包，則將該本端資料封包儲存至一緩衝器裝置中。該等指令亦促進判定該緩衝器裝置是否含有一資料封包及判定該上游驅動器是否閒置。若該緩衝器含有一資料封包且該上游驅動器閒置，則將該資料封包傳輸至該上游驅動器。該等指令進一步促進判定是否已接收到一上游資料封包。若已接收到一上游資料封包且該上游驅動器並非閒置，則將該上游資料封包儲存至該緩衝器裝置中。若已接收到一上游資料封包且該緩衝器裝置不含有一資料封包且該上游驅動器閒置，則將該上游資料封包傳輸至該上游驅動器。若該上游驅動器並非閒置，則將進程中之任何資料封包繼續傳輸至該上游驅動器。
例示性實施例包括一具有一或多個記憶體模組之記憶體子系統。該等記憶體模組包括由一菊鏈通道連接至一記憶體控制器之一或多個記憶體裝置。使用一包括一識別標籤及訊框開始指示符之訊框格式來將讀取資料傳回至該記憶體控制器。該記憶體系統亦包括在記憶體模組上以用於緩衝位址、指令及資料之一或多個集線器裝置。該等集線器裝置包括控制器通道緩衝器，該等控制器通道緩衝器與一先佔式本端資料合併演算法(preemptive local data merge algorithm)結合使用，以最小化讀取資料等待時間及使得能將不確定讀取資料傳回時間提供至記憶體控制器。
其他例示性實施例包括一具有一或多個記憶體模組之記憶體系統。該等記憶體模組包括由一菊鏈通道連接至一記憶體控制器之記憶體裝置。使用一包括一識別標籤及訊框開始指示符之訊框格式來將讀取資料傳回至該記憶體控制器。該記憶體系統亦包括連接至該等記憶體模組以用於緩衝位址、指令及資料之一或多個集線器裝置。該等集線器裝置包括控制器通道緩衝器，該等控制器通道緩衝器與一先佔式本端資料合併演算法結合使用以最小化讀取資料等待時間及使得能將不確定讀取資料傳回時間提供至記憶體控制器。
例示性實施例利用控制器通道緩衝器(CCB)、具有識別標籤之讀取資料訊框格式及一先佔式資料合併技術來使得能提供最小化及不確定讀取資料等待時間。例示性實施例允許記憶體模組在未預知的時間將讀取資料傳回至一記憶體控制器。將識別標籤資訊添加至讀取資料封包以指示用以得到資料之讀取指令以及讀取資料所用之集線器。識別標籤資訊由控制器利用以將讀取資料封包與由控制器所發送的讀取指令匹配。藉由使用識別標籤資訊，可以不同於對應讀取指令之發送次序的次序來傳回讀取資料。
例示性實施例亦提供一先佔式資料合併處理以防止在實施不確定讀取資料等待時間時在上游通道上發生資料碰撞。將一CCB添加至集線器裝置以暫時儲存讀取資料。當記憶體模組上之一記憶體裝置讀取資料時，資料自記憶體介面傳送至緩衝器。當集線器裝置偵測到一上游資料封包(亦即，自偵測集線器裝置下游之一集線器裝置發送至控制器的資料封包)不在經由一上游通道(其通常採用若干次傳送以發送整個資料封包)至偵測集線器裝置傳送之中時，偵測集線器裝置檢查在其CCB中是否存在一等待於上游發送的讀取資料封包。若集線器裝置在CCB中偵測到一讀取資料封包，則其將該讀取資料封包自CCB驅動至上游資料匯流排上。同時，若一新的上游資料封包經由上游資料匯流排被接收，則將資料封包儲存在集線器裝置上的CCB中。以此方式，來自上游之資料封包不會與自集線器裝置上的CCB發送至上游之資料封包碰撞。在CCB中存在一個以上資料封包的情況下，可實施各種方法來判定接著將發送之資料封包(例如，可首先發送來自最舊讀取指令的資料封包)。
例示性實施例適用於由一或多個記憶體模組110建構之記憶體系統，該等記憶體模組110係經由菊鏈記憶體通道114連接至一記憶體控制器102，如圖1所描繪。該等記憶體模組110含有：緩衝往返於控制器記憶體通道114之指令、位址及資料信號的集線器裝置112；以及連接至該集線器裝置112的一或多個記憶體裝置108。記憶體通道114之下游部分(下游通道104)將寫入資料及記憶體操作指令傳輸至集線器裝置112。控制器通道114之上游部分(上游通道106)傳回所請求的讀取資料(本文稱為上游資料封包)。
圖2描繪一替代性例示性實施例，其包括由連接至集線器裝置112之一或多個記憶體模組110建構的記憶體系統，集線器裝置112進一步由菊鏈記憶體通道114連接至記憶體控制器102。在此實施例中，未將集線器裝置112定位於記憶體模組110上；而是使集線器裝置112與記憶體模組110通信。如圖2所描繪，記憶體模組110可經由多點鏈接及/或點對點鏈接與集線器裝置112通信。其他硬體組態為可能的，例如例示性實施例可僅利用一單級菊鏈集線器裝置112及/或記憶體模組110。
圖3描繪具有流程控制邏輯308之集線器裝置112，其由例示性實施例利用以執行本文所描述之處理。可用硬體及/或軟體來建構集線器裝置112及集線器裝置112內之組件。集線器裝置112經由接收器邏輯304(本文亦稱為上游接收器)接收上游通道104上之上游資料封包。上游資料封包係自集線器裝置112發送至控制器102之資料封包，該集線器裝置112係在接收集線器裝置112的下游。可將一上游資料封包發送至驅動器邏輯306(本文亦稱為上游驅動器)，以供在上游通道106上朝向控制器102驅動，或者，若上游通道106忙碌，則可將上游資料封包暫時儲存在集線器裝置112上的CCB 310中。上游資料封包之目的地由流程控制邏輯308確定且藉由發送一信號至本端資料多工器312來實施。
在例示性實施例中，CCB 310或緩衝器裝置駐留在集線器裝置112中且(經由接收器邏輯304)安全地擷取在集線器裝置112將其本端資料封包合併至上游通道106上時分流至CCB 310中之上游資料封包傳送。本端資料封包係讀取自附接至由集線器裝置112導引之記憶體模組110之記憶體裝置108的資料封包。此等記憶體裝置108本文亦稱為本端儲存裝置。將自本端儲存裝置讀取之資料(本端資料封包)格式化以用於在上游控制器介面上經由上游驅動器傳回且將其儲存在CCB 310中。格式化包括將本端資料封包串列化成適當訊框格式(例如，見圖5中描繪之例示性訊框格式)，及將值插入至識別標籤(來源於讀取請求)、第一傳送欄位，及匯流排循環冗餘碼(CRC)欄位中，在例示性實施例中，本端資料封包之格式化執行為將本端資料封包儲存至CCB 310中之部分。
當在記憶體介面302處接收到一資料封包時，該資料封包在本端資料封包正等待(經由驅動器邏輯306)合併至上游通道106上時被儲存至CCB 310中。資料封包內之識別標籤允許記憶體控制器102將一傳回之讀取資料封包與其對應的讀取資料請求指令相關聯。資料封包亦含有在接近一上游讀取資料訊框(將資料封包格式化為讀取資料訊框)之開始而傳遞的小且易於解碼之"開始"或第一傳送("ft")欄位(本文亦稱為訊框開始指示符)，其指示一讀取資料訊框存在於該資料封包中。此由集線器裝置112中之流程控制邏輯308使用以監控通道讀取資料之活動性。
當藉由一本端讀取操作或藉由自下游集線器裝置之先前經分流讀取資料封包(CCB中之資料封包本文稱為經儲存之資料封包)而使得在CCB 310中存在資料時，集線器裝置112將在獲得允許後立即將資料經由驅動器邏輯306合併至上游通道106上。集線器裝置112在上游通道106閒置之任何時候或在當前處於進程中之一資料封包的最後一次傳送之後立即將本端資料合併至上游通道106上。使用此方法始終不會對分讀取資料訊框，但傳送於上游通道106上之仍未抵達集線器裝置112之本端資料多工器312的讀取資料訊框可被搶佔並被分流至CCB 310中。此允許上游通道106上之讀取資料中的間隙最小化，此在實際完全工作負載條件下增加了匯流排效率且產生減少的平均讀取資料等待時間。
當多個讀取資料封包存在於CCB 310中時，集線器裝置112可經組態以發送對應於最早讀取指令之讀取資料封包。此最小化了發送至遠離記憶體控制器102的許多菊鏈位置之集線器裝置112之讀取請求的不當等待時間。亦可實施其他CCB 310卸載優先權排序演算法。舉例而言，讀取資料訊框之識別標籤欄位可含有一優先權欄位。該優先權欄位可用於引導卸載CCB 310。或者，可在請求讀取資料時傳遞優先權資訊。集線器裝置112隨後可將識別標籤與先前記錄之優先權資訊比較以確定CCB 310中接著將發送之位置。亦可使用有時在高優先權資料之前發送低優先權資料以確保低優先權資料不會被已標記有較高優先權之請求完全停止的方法。
圖4為由例示性實施例中位於集線器裝置112中之流程控制邏輯308促進之方法流程。圖4中所描繪的方法執行先佔式本端資料合併且可由包括硬體及/或軟體指令之機件(諸如流程控制邏輯308中之有限狀態器)來實施。該方法始於方塊402且在例示性實施例中週期性地重複(例如，在每次控制器通道傳送之後或上游通道循環之後)。在方塊404處，將記憶體介面302中之任何本端讀取資料封包(亦即，來自附接至集線器裝置112之記憶體模組110上的記憶體裝置108)載入至CCB 310中。此確保流程控制邏輯308清楚並管理本端讀取資料之上游驅動。在方塊406處，判定CCB 310中是否存在資料。若CCB 310中不存在資料，則在方塊412處將資料自接收器邏輯304投送至驅動器邏輯306。由流程控制邏輯308導引該投送，其方式係：設定本端資料多工器312，以將上游資料封包發送至驅動器邏輯306，來將上游資料封包朝向控制器102驅動至上游通道106上。處理隨後繼續至414，在下一上游通道循環時處理將於此處發送回方塊404。
若在方塊406處判定在CCB 310中存在資料，則執行方塊408來判定一上游通道操作是否在進行中(亦即，是上游資料封包還是本端讀取資料封包處於正經由驅動器邏輯306驅動至上游通道106上之中)。在上游通道操作在進行中(亦即，驅動器忙碌)時，處理繼續至方塊412處。在方塊412處，藉由設定本端資料多工器312，將上游資料封包發送至驅動器邏輯306，來將上游讀取資料封包自接收器邏輯304投送至驅動器邏輯306。或者，在上游通道操作不在進行中(亦即，驅動器閒置)且CCB 310中存在資料時處理繼續至方塊410處。在方塊410處，將來自CCB 310之資料驅動至上游通道106，同時將自上游通道106接收於接收器邏輯304中之任何資料封包分流(儲存)至下一可用CCB 310位置中。由導引上游資料封包以供載入至CCB 310中之流程控制邏輯308來執行分流。處理隨後繼續至414處，其在下一上游通道循環時將處理發送回方塊404。
圖5為用於上游通道106上之上游資料封包及本端讀取資料封包的例示性讀取資料訊框格式。在圖5中所描繪之訊框格式使用21個信號線道且每一封包包括16個傳送。其包括一個位元之第一開始指示符502及識別標籤504，以及256個位元(32B)之讀取資料506及用於傳輸誤差偵測之匯流排CRC 508。可使用信號線道及傳送深度之其他組合，來建立包括與本發明相容之一訊框開始指示符、讀取資料識別標籤及讀取資料的訊框格式。
例示性實施例係關於由連接至記憶體模組或包含在記憶體模組上之菊鏈集線器邏輯裝置組成的電腦記憶體系統。集線器被菊鏈在一記憶體控制器通道上且進一步被附接至記憶體模組上的記憶體裝置。記憶體控制器發送讀取資料請求至將此讀取資料自記憶體模組合並至記憶體通道上的集線器。使用通道緩衝器及封包識別標籤，集線器能夠在記憶體控制器不可預測之時間處及在可能搶佔較早發送之讀取請求的時間處傳回讀取資料，而無需釋放或破壞在通道上傳回至記憶體控制器之任何讀取資料。
例示性實施例可用於藉由更充分利用上游通道來最佳化平均讀取資料等待時間。經由使用CCB、具有識別標籤之讀取資料訊框格式及一先佔式資料合併技術，可執行不確定讀取資料等待時間來更充分利用控制器通道。
如上所描述，本發明之實施例可以電腦實施方法及設備之形式加以體現以實現該等過程。本發明之實施例亦可以含有包括在有形媒體(諸如，軟碟、CD－ROM(緊密光碟－唯讀記憶體)、硬碟機，或任何其他電腦可讀儲存媒體)中之指令的電腦程式碼形式加以體現，其中，當將電腦程式碼載入至一電腦中且由該電腦執行時，電腦變成用於實現本發明的設備。本發明亦可以(例如)儲存在一儲存媒體中、載入至一電腦中及/或由一電腦執行或經由一些傳輸媒體(諸如經由電線或電纜、經由光纖或經由電磁輻射)傳輸之任一電腦程式碼形式加以體現，其中，當將電腦程式碼載入至一電腦中且由該電腦執行時，電腦變成用於實現本發明的設備。當實施於一通用微處理器上時，電腦程式碼段組態該微處理器以建立特定邏輯電路。
雖然已參考例示性實施例描述了本發明，但熟習此項技術者應瞭解可進行各種改變且可以均等物取代本發明元件而不脫離本發明之範疇。此外，可進行許多修改以使一特定情況或材料適合本發明之教示而不脫離其本質範疇。因此，希望本發明不限於作為預期用於執行本發明之最佳模式所揭示的特定實施例，而希望本發明包括屬於所附申請專利範圍之範疇內的所有實施例。此外，術語第一、第二等的使用並不表示任何次序或重要性，術語第一、第二等而是用於將一個元件與另一元件區分開。
102．．．記憶體控制器
104．．．下游通道
106．．．上游通道
108．．．記憶體裝置
110．．．記憶體模組
112．．．集線器裝置
114．．．記憶體通道
304．．．接收器邏輯
306．．．驅動器邏輯
308．．．流程控制邏輯
310．．．控制器通道緩衝器
312．．．本端資料多工器
502．．．第一開始指示符
504．．．識別標籤
506．．．讀取資料
508．．．匯流排循環冗餘碼
圖1描繪一例示性記憶體系統，其具有以點對點鏈接之多級菊鏈記憶體模組；圖2描繪一例示性記憶體系統，其具有由一菊鏈通道連接至一記憶體模組及聯接至一記憶體控制器的集線器裝置；圖3描繪一可由例示性實施例利用的集線器邏輯裝置；圖4描繪由例示性實施例中之集線器邏輯裝置實施的例示性方法流程；及圖5描繪一可由例示性實施例利用的讀取資料格式。

Claims (15)

  1. 一種用於在一記憶體系統中提供不確定讀取資料等待時間之方法，該方法包含：判定是否已接收到一本端資料封包；若已接收到一本端資料封包，則將該本端資料封包儲存至一緩衝器裝置中；判定該緩衝器裝置是否含有一或多個資料封包；判定一用於經由一上游通道將該一或多個資料封包傳輸至一記憶體控制器之上游驅動器是否閒置；若該緩衝器裝置含有一或多個資料封包且該上游驅動器閒置，則將該一或多個資料封包中一經選擇資料封包傳輸至該上游驅動器；判定是否已接收到一上游資料封包，該上游資料封包呈一包括於一第一傳輸中一單一位元之訊框開始指示符及一識別標籤之多個傳輸之訊框格式，該記憶體控制器使用該訊框格式以使該上游資料封包與其對應的讀取指令相關聯，該識別標籤分佈於整個上游資料封包之多個傳輸之每一傳輸；若已接收到該上游資料封包且該上游驅動器並非閒置，則將該上游資料封包儲存至該緩衝器裝置中，該緩衝器裝置經組態以儲存該本端資料封包及該上游資料封包之兩者作為該一或多個資料封包；若已接收到該上游資料封包且該緩衝器裝置不含有一或多個資料封包且該上游驅動器閒置，則將該上游資料 封包傳輸至該上游驅動器；及若該上游驅動器並非閒置則繼續傳輸進程中之任何資料封包。
  2. 如請求項1之方法，其中在一週期性基礎上執行該判定是否已接收到該本端資料封包、該判定該緩衝器裝置是否含有一或多個資料封包、該判定該上游驅動器是否閒置及該判定是否已接收到該上游資料封包。
  3. 如請求項2之方法，其中該週期性基礎係每一上游通道循環一次。
  4. 如請求項1之方法，其中該經選擇資料封包基於一優先權排序演算法被選擇以傳輸。
  5. 如請求項4之方法，其中該優先權排序演算法係基於對應於該經選擇資料封包之該讀取指令的一齡期來選擇該經選擇資料封包。
  6. 如請求項4之方法，其中該優先權排序演算法係基於與該經選擇資料封包相關聯的一優先權來選擇該經選擇資料封包，且進一步其中該經選擇資料封包呈該多個傳輸訊框格式，其包括該訊框開始指示符及該識別標籤，該優先權包含於該識別標籤之一優先權欄位中，且該優先權排序演算法週期性地在一較高優先權資料封包之前選擇一較低優先權資料封包作為該經選擇資料封包。
  7. 如請求項1之方法，其中該多個傳輸之訊框格式進一步包括一匯流排循環冗餘碼(CRC)欄位，該匯流排CRC欄位分佈於該多個傳輸不包括該第一傳輸中，且與該訊框 開始指示符位於一共同位元位置。
  8. 如請求項7之方法，其中該將該本端資料封包儲存至該緩衝器裝置包括格式化該本端資料封包，該格式化包括將該本端資料封包串列化成該多個傳輸之訊框格式及將值插入至該訊框開始指示符、該識別標籤及該匯流排CRC欄位。
  9. 一種在一記憶體系統中之集線器裝置，該集線器裝置包含：一用於接收資料封包之裝置，該裝置包括一上游接收器，其用於自一下游集線器裝置接收上游資料封包；及一記憶體介面，其用於自一本端儲存裝置接收本端資料封包，其中每一資料封包呈一包括於一第一傳輸中一單一位元之訊框開始指示符及一識別標籤之多個傳輸之訊框格式，一記憶體控制器使用該訊框格式以使該資料封包與其對應的讀取指令相關聯，該識別標籤分佈於整個資料封包之多個傳輸之每一傳輸；一上游驅動器，其用於經由一上游通道將該等資料封包傳輸至該記憶體控制器；及一包括用於促進以下根據請求項1至8項任一方法之各項之指令的機件。
  10. 一種用於在一記憶體系統中之記憶體控制器，該記憶體控制器包含：一上游通道，其用於在一不可預測之時間自一下游集線器裝置接收上游資料封包，呈一多個傳輸訊框格式之 每一封包包括於一第一傳輸中單一位元之訊框開始指示符及一識別標籤，該識別標籤分佈於整個資料封包之多個傳輸之每一傳輸；及用於在該記憶體控制器中用於使該等接收資料封包與其對應的讀取資料請求指令相關聯之邏輯，其使用包括於該等讀取資料封包內之識別標籤。
  11. 如請求項10之記憶體控制器，其中每一讀取資料封包在相對於其相對應之讀取請求指令之一不可預測之時間接收。
  12. 如請求項10之記憶體控制器，其中該等讀取資料封包以一相對於該等讀取資料封包相對應之讀取請求指令之一發送次序不可預測之順序接收。
  13. 如請求項10之記憶體控制器，其中該多個傳輸訊框之格式進一步包括一匯流排循環冗餘碼(CRC)欄位，該匯流排CRC欄位分佈於該多個傳輸不包括該第一傳輸中，且與該訊框開始指示符位於一共同位元位置。
  14. 一種記憶體系統，其包含：一記憶體控制器，其包含：一上游通道，其用於在一個或多個讀取資料封包相對應之讀取請求指令之一不可預測之時間接收該一個或多個讀取資料封包，呈一多個傳輸之訊框格式之每一讀取資料封包包括於一第一傳輸中之一單一位元訊框開始指示符及一識別標籤，該識別標籤分佈於整個上游讀取資料封包之多個傳輸之每一傳輸；及 若干電腦指令，其用於在該記憶體控制器中使該等接收一或多個讀取資料封包與對應的一或多個讀取資料請求指令相關聯，其使用包括於該一或多個讀取資料封包每一者內之識別標籤；一或多個記憶體模組，其具有藉由一菊鏈通道連接至該記憶體控制器之一或多個記憶體裝置，其中該讀取資料傳回至該記憶體控制器作為該一或多個讀取資料封包；及在該等記憶體模組上用於緩衝位址、指令及資料之一或多個集線器裝置，該等集線器裝置包括控制器通道緩衝器，該等控制器通道緩衝器與一先佔式本端資料合併邏輯結合使用，以最小化讀取資料等待時間及使得能將不確定讀取資料傳回時間提供至該記憶體控制器。
  15. 一種記憶體系統，其包含：一記憶體控制器，其包含：一上游通道，其用於在一個或多個讀取資料封包相對應之讀取請求指令之一不可預測之時間接收該一個或多個讀取資料封包，呈一多個傳輸之訊框格式之每一讀取資料封包包括於一第一傳輸中之一單一位元訊框開始指示符及一識別標籤，該識別標籤分佈於整個上游讀取資料封包之多個傳輸之每一傳輸；及若干電腦指令，其用於在該記憶體控制器中使該等接收一或多個讀取資料封包與對應的一或多個讀取資料請求指令相關聯，其使用包括於該一或多個讀取資料 封包每一者內之識別標籤；一或多個記憶體模組，其具有藉由一菊鏈通道連接至該記憶體控制器之一或多個記憶體裝置，其中該讀取資料傳回至該記憶體控制器作為該一或多個讀取資料封包；及在該等記憶體模組上用於緩衝位址、指令及資料之一或多個集線器裝置，該等集線器裝置包括控制器通道緩衝器，該等控制器通道緩衝器與一先佔式本端資料合併邏輯結合使用，以最小化讀取資料等待時間及使得能將不確定讀取資料傳回時間提供至該記憶體控制器，其中該一或多個集線器裝置之每一者包括一上游驅動器且執行根據請求項1至8項任一方法。
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US8145868B2 (en) 2012-03-27
US20120151171A1 (en) 2012-06-14
CN101300556A (zh) 2008-11-05
US8151042B2 (en) 2012-04-03
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US20070286078A1 (en) 2007-12-13
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US20070160053A1 (en) 2007-07-12
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CN101300556B (zh) 2010-05-19
US20070286199A1 (en) 2007-12-13
US20120151172A1 (en) 2012-06-14
US8327105B2 (en) 2012-12-04
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