TWI392405B - 線路結構 - Google Patents
線路結構 Download PDFInfo
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- TWI392405B TWI392405B TW098136193A TW98136193A TWI392405B TW I392405 B TWI392405 B TW I392405B TW 098136193 A TW098136193 A TW 098136193A TW 98136193 A TW98136193 A TW 98136193A TW I392405 B TWI392405 B TW I392405B
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Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
- H05K3/181—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating
- H05K3/182—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method
- H05K3/184—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method using masks
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/465—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer having channels for the next circuit layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0183—Dielectric layers
- H05K2201/0195—Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0347—Overplating, e.g. for reinforcing conductors or bumps; Plating over filled vias
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/10—Using electric, magnetic and electromagnetic fields; Using laser light
- H05K2203/107—Using laser light
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
- H05K2203/1173—Differences in wettability, e.g. hydrophilic or hydrophobic areas
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
- H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
- H05K3/386—Improvement of the adhesion between the insulating substrate and the metal by the use of an organic polymeric bonding layer, e.g. adhesive
- H05K3/387—Improvement of the adhesion between the insulating substrate and the metal by the use of an organic polymeric bonding layer, e.g. adhesive for electroless plating
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/421—Blind plated via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4661—Adding a circuit layer by direct wet plating, e.g. electroless plating; insulating materials adapted therefor
Description
本發明是有關於一種線路結構,且特別是有關於一種具有細線路的線路結構。
近年來隨著電子工業之生產技術的突飛猛進,線路基板可搭載各種電子零件,以廣泛地應用於各種不同功能的電子產品中。目前,電子產品朝向多功能化及小型化的方向發展。在此趨勢下,線路基板需大幅提昇其佈線密度,以搭載更多且更精密的電子零件,而提昇佈線密度無非是透過縮小線寬以及線距來達成。
於習知技術中,線路層的形成方式是先於基板上全面電鍍一金屬層,之後再以微影蝕刻的方式圖案化金屬層。然而,習知技術受限於電鍍製程所形成的金屬層的均勻度以及微影蝕刻製程的精準度等製程能力的限制,而不易製作線寬低於40微米的線路,以致於產品良率低且製作成本高。
本發明提供一種線路結構,具有較小的線寬。
本發明提出一種線路結構包括一線路板、一絕緣層、一導電通道、一可鍍介電層以及一導電圖案。絕緣層配置於線路板上並覆蓋線路板的一線路層。導電通道貫穿絕緣層並與線路層相連,且導電通道突出於絕緣層的一第一表面。可鍍介電層配置於絕緣層的第一表面上,並具有一溝槽圖案,且導電通道之突出於第一表面的部分位於溝槽圖案中,可鍍介電層的材質包括一可被化學鍍的材料。導電圖案位於溝槽圖案中,並與導電通道相連,其中導電圖案與導電通道之間存在一交界面。
在本發明之一實施例中,可鍍介電層具有一朝向遠離線路板的第二表面,且第二表面具有溝槽圖案,線路結構更包括一抗鍍介電層,其配置於第二表面上且位於溝槽圖案外,抗鍍介電層的材質包括一抗化學鍍的材料。
在本發明之一實施例中,抗鍍介電層的材質包括不含羥基(OH)官能基團或羧基(COOH)官能基團的高分子材料。
在本發明之一實施例中,高分子材料包括環氧樹脂、聚亞醯胺、液晶聚合物、甲基丙烯酸酯型樹脂、乙烯苯基型樹脂、烯丙基型樹脂、聚丙烯酸酯型樹脂、聚醚型樹脂、聚烯烴型樹脂、聚胺型樹脂、聚矽氧烷型樹脂或前述之組合。
在本發明之一實施例中,抗鍍介電層的材質包括一易雷射加工的材料。
在本發明之一實施例中,可鍍介電層的材質包括高分子材料。
在本發明之一實施例中,高分子材料包括環氧樹脂、聚亞醯胺、液晶聚合物或前述之組合。
在本發明之一實施例中,可鍍介電層的材質包括一易雷射加工的材料。
在本發明之一實施例中,絕緣層的材質包括樹脂、聚亞醯胺或液晶聚合物。
在本發明之一實施例中,絕緣層的材質包括玻璃纖維。
在本發明之一實施例中,導電圖案覆蓋導電通道。
在本發明之一實施例中,導電圖案的最小線寬約為40微米以下。
為讓本發明之上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。
圖1繪示本發明一實施例之線路結構的剖面圖,圖2繪示圖1之線路結構的一種變化。
請參照圖1,本實施例之線路結構100包括一線路板110、一絕緣層120、一導電通道130、一可鍍介電層140以及一導電圖案150。
絕緣層120配置於線路板110上並覆蓋線路板110的一線路層112。在本實施例中,絕緣層120的材質包括樹脂、聚亞醯胺、液晶聚合物或芳香族聚醯胺(Aramid)。在本實施例中,絕緣層120例如為一膠片(prepreg),絕緣層120的材質可包括玻璃纖維。導電通道130貫穿絕緣層120並與線路層112相連,且導電通道130突出於絕緣層120的一表面122,其中表面122朝向遠離線路板110的方向。
可鍍介電層140配置於絕緣層120的表面122上,並具有一溝槽圖案R,且溝槽圖案R並未貫穿可鍍介電層140。導電通道130之突出於表面122的部分位於溝槽圖案R中,可鍍介電層140的材質包括一可被化學鍍的材料。詳細而言,在本實施例中,『可被化學鍍的材料』是代表在化學鍍製程中會吸附催化劑的材料。可鍍介電層140的材質例如為高分子材料,其中高分子材料包括環氧樹脂、聚亞醯胺、液晶聚合物或前述之組合。在本實施例中,可鍍介電層140的材質可為一易雷射加工的材料,亦即容易在雷射燒蝕的過程中被移除的材料。
詳細而言,可鍍介電層140具有一朝向遠離線路板110的表面142,且表面142具有溝槽圖案R。在本實施例中,可在溝槽圖案R外的表面142上配置一抗鍍介電層160(如圖2所示),抗鍍介電層160的材質包括一抗化學鍍的材料。詳細而言,在本實施例中,『抗化學鍍的材料』是代表在化學鍍製程中不會吸附催化劑的材料。抗鍍介電層160的材質例如為不含羥基(OH)官能基團或羧基(COOH)官能基團的高分子材料(亦即疏水性高分子材料),其中高分子材料包括環氧樹脂、聚亞醯胺、液晶聚合物、甲基丙烯酸酯型樹脂、乙烯苯基型樹脂、烯丙基型樹脂、聚丙烯酸酯型樹脂、聚醚型樹脂、聚烯烴型樹脂、聚胺型樹脂、聚矽氧烷型樹脂或前述之組合。在本實施例中,抗鍍介電層160的材質可為一易雷射加工的材料。
請再次參照圖1,導電圖案150位於溝槽圖案R中,並與導電通道130相連,其中導電圖案150與導電通道130之間存在一交界面S,且交界面S例如為非平面,交界面S突出於絕緣層120的表面122。在本實施例中,導電圖案150覆蓋導電通道130。換言之,突出於絕緣層120的表面122的導電通道130是以類似榫接的方式與導電圖案150接合。在其他實施例中,導電通道130之一朝向遠離線路板110的方向的端部(未繪示)可齊平於導電圖案150的表面152。
值得注意的是,請參照圖2,本實施例之導電圖案150的製作方式可以是先在線路板110上形成絕緣層120、可鍍介電層140與抗鍍介電層160之後,進行一化學鍍製程,以於溝槽圖案R中形成導電圖案150。由於導電圖案150只會形成在溝槽圖案R所暴露出的可鍍介電層140上,因此,導電圖案150只會填滿於溝槽圖案R中。如此一來,本實施例可藉由溝槽圖案R來定義出導電圖案150,進而可藉由控制溝槽圖案R的最小溝槽寬度來調整形成在溝槽圖案R中的導電圖案150的最小線寬。再者,由於可鍍介電層140與抗鍍介電層160皆可為易雷射加工的材料,故可以雷射燒蝕的方式形成溝槽圖案R。如此一來,本實施例毋須藉由微影蝕刻的方式來形成線路層,故可縮小導電圖案150的最小線寬(例如將最小線寬縮小至40微米以下)、提升製程良率並降低製作成本。
詳細而言,相較於習知以減成法製作線路時,會受限於微影蝕刻製程的精準度等製程能力的限制而不易製作線寬低於40微米的線路,以致於產品良率低導致製作成本高,本實施例是形成溝槽圖案R,並在溝槽圖案R中形成線路(即導電圖案150),因此,溝槽圖案R的溝槽最小寬度可等同於導電圖案150的最小線寬,而由於可鍍介電層140與抗鍍介電層160皆可為易雷射加工的材料,故本實施例可採用雷射燒蝕的方式形成溝槽圖案R以使溝槽最小寬度小於40微米,從而使得導電圖案150的最小線寬可小於40微米。
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾,故本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100...線路結構
110...線路板
112...線路層
120...絕緣層
122、142、152...表面
130...導電通道
140...可鍍介電層
150...導電圖案
160...抗鍍介電層
R...溝槽圖案
S...交界面
圖1繪示本發明一實施例之線路結構的剖面圖。
圖2繪示圖1之線路結構的一種變化。
100...線路結構
110...線路板
112...線路層
120...絕緣層
122、142、152...表面
130...導電通道
140...可鍍介電層
150...導電圖案
R...溝槽圖案
S...交界面
Claims (12)
- 一種線路結構,包括:一線路板;一絕緣層,配置於該線路板上並覆蓋該線路板的一線路層;一導電通道,貫穿該絕緣層並與該線路層相連,且該導電通道突出於該絕緣層的一第一表面;一可鍍介電層,配置於該絕緣層的該第一表面上,並具有一溝槽圖案,且該導電通道之突出於該第一表面的部分位於該溝槽圖案中,該可鍍介電層的材質包括一可被化學鍍的材料;以及一導電圖案,位於該溝槽圖案中,並與該導電通道相連,其中該導電圖案與該導電通道之間存在一交界面,且該交界面突出於該絕緣層的該第一表面。
- 如申請專利範圍第1項所述之線路結構,其中該可鍍介電層具有一朝向遠離該線路板的第二表面,且該第二表面具有該溝槽圖案,該線路結構更包括:一抗鍍介電層,配置於該第二表面上且位於該溝槽圖案外,該抗鍍介電層的材質包括一抗化學鍍的材料。
- 如申請專利範圍第2項所述之線路結構,其中該抗鍍介電層的材質包括不含羥基官能基團或羧基官能基團的高分子材料。
- 如申請專利範圍第3項所述之線路結構,其中該高分子材料包括環氧樹脂、聚亞醯胺、液晶聚合物、甲基丙烯酸酯型樹脂、乙烯苯基型樹脂、烯丙基型樹脂、聚丙烯酸酯型樹脂、聚醚型樹脂、聚烯烴型樹脂、聚胺型樹脂、聚矽氧烷型樹脂或前述之組合。
- 如申請專利範圍第2項所述之線路結構,其中該抗鍍介電層的材質包括一易雷射加工的材料。
- 如申請專利範圍第1項所述之線路結構,其中該可鍍介電層的材質包括高分子材料。
- 如申請專利範圍第6項所述之線路結構,其中該高分子材料包括環氧樹脂、聚亞醯胺、液晶聚合物或前述之組合。
- 如申請專利範圍第1項所述之線路結構,其中該可鍍介電層的材質包括一易雷射加工的材料。
- 如申請專利範圍第1項所述之線路結構,其中該絕緣層的材質包括樹脂、聚亞醯胺或液晶聚合物。
- 如申請專利範圍第1項所述之線路結構,其中該絕緣層的材質包括玻璃纖維。
- 如申請專利範圍第1項所述之線路結構,其中該導電圖案覆蓋該導電通道。
- 如申請專利範圍第1項所述之線路結構,其中該導電圖案的最小線寬約為40微米以下。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW098136193A TWI392405B (zh) | 2009-10-26 | 2009-10-26 | 線路結構 |
JP2010042396A JP4964974B2 (ja) | 2009-10-26 | 2010-02-26 | 回路構造 |
US12/718,194 US8288662B2 (en) | 2009-10-26 | 2010-03-05 | Circuit structure |
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CN109714888B (zh) * | 2017-10-25 | 2020-08-18 | 欣兴电子股份有限公司 | 电路板及其制造方法 |
TWI642333B (zh) | 2017-10-25 | 2018-11-21 | 欣興電子股份有限公司 | 電路板及其製造方法 |
TWI642334B (zh) | 2017-10-25 | 2018-11-21 | 欣興電子股份有限公司 | 電路板及其製造方法 |
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US20110094779A1 (en) | 2011-04-28 |
US8288662B2 (en) | 2012-10-16 |
TW201116172A (en) | 2011-05-01 |
JP2011091353A (ja) | 2011-05-06 |
JP4964974B2 (ja) | 2012-07-04 |
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