TWI390686B - Resin package type semiconductor device and manufacturing method thereof - Google Patents
Resin package type semiconductor device and manufacturing method thereof Download PDFInfo
- Publication number
- TWI390686B TWI390686B TW097103545A TW97103545A TWI390686B TW I390686 B TWI390686 B TW I390686B TW 097103545 A TW097103545 A TW 097103545A TW 97103545 A TW97103545 A TW 97103545A TW I390686 B TWI390686 B TW I390686B
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- Taiwan
- Prior art keywords
- wafer
- resin
- pad
- wafer pad
- semiconductor wafer
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims description 348
- 229920005989 resin Polymers 0.000 title claims description 67
- 239000011347 resin Substances 0.000 title claims description 67
- 238000004519 manufacturing process Methods 0.000 title claims description 37
- 235000012431 wafers Nutrition 0.000 claims description 540
- 229910000679 solder Inorganic materials 0.000 claims description 64
- 229910045601 alloy Inorganic materials 0.000 claims description 50
- 239000000956 alloy Substances 0.000 claims description 50
- 239000000758 substrate Substances 0.000 claims description 47
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 37
- 229910052802 copper Inorganic materials 0.000 claims description 37
- 239000010949 copper Substances 0.000 claims description 37
- 229910000881 Cu alloy Inorganic materials 0.000 claims description 33
- 229910000833 kovar Inorganic materials 0.000 claims description 24
- 239000000725 suspension Substances 0.000 claims description 20
- 238000005538 encapsulation Methods 0.000 claims description 19
- 238000000034 method Methods 0.000 claims description 11
- 229910052732 germanium Inorganic materials 0.000 claims description 9
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 9
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims description 4
- 230000000149 penetrating effect Effects 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 238000004806 packaging method and process Methods 0.000 claims 1
- 230000000052 comparative effect Effects 0.000 description 27
- 230000006378 damage Effects 0.000 description 25
- 239000000463 material Substances 0.000 description 11
- 230000035882 stress Effects 0.000 description 10
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 8
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 8
- 239000003822 epoxy resin Substances 0.000 description 6
- 239000011521 glass Substances 0.000 description 6
- 229920000647 polyepoxide Polymers 0.000 description 6
- 230000006866 deterioration Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 230000008646 thermal stress Effects 0.000 description 5
- 238000003466 welding Methods 0.000 description 5
- 238000005452 bending Methods 0.000 description 4
- 238000002474 experimental method Methods 0.000 description 4
- 229910052742 iron Inorganic materials 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- 238000005476 soldering Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000004080 punching Methods 0.000 description 3
- 229910000906 Bronze Inorganic materials 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 239000010974 bronze Substances 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 230000008961 swelling Effects 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- 230000003685 thermal hair damage Effects 0.000 description 2
- 241000272168 Laridae Species 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 230000001151 other effect Effects 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
Classifications
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Description
本發明係關於樹脂封裝型半導體裝置及其製造方法,特別有關具備固定有半導體晶片之晶片銲墊之樹脂封裝型半導體裝置及其製造方法。
以往,據知有具備固定有半導體晶片之晶片銲墊之樹脂封裝型半導體裝置(參考例如專利文獻1)。
於上述專利文獻1記載一種樹脂封裝型半導體裝置,其係具備:晶片銲墊,其係固定有半導體晶片;封裝體(樹脂封裝層),其係封裝半導體晶片;及引線端子,其係電性連接於半導體晶片。於此類以往之樹脂封裝型半導體裝置,半導體晶片一般中介焊錫層而固定於晶片銲墊。
[專利文獻1]日本特開2006-302963號公報
然而,於上述以往之樹脂封裝型半導體裝置,由於中介焊錫層來將半導體晶片固定於晶片銲墊,因此起因於半導體晶片與晶片銲墊之熱膨脹係數之差,會具有甚大之應力加在半導體晶片之不便。因此,具有由於甚大之應力加在半導體晶片而發生裂痕等損傷之問題點。
本發明係為了解決如上問題者,本發明之一目的在於提供一種可抑制半導體晶片損傷之樹脂封裝型半導體裝置。
本發明之另一目的在於提供一種可抑制半導體晶片損傷
之樹脂封裝型半導體裝置之製造方法。
為了達成上述目的,根據本發明之第一態樣之樹脂封裝型半導體裝置具備:半導體晶片,其係包含矽基板;晶片銲墊,其係中介焊錫層而固定有半導體晶片;樹脂封裝層,其係封裝半導體晶片;及複數引線端子,其係與半導體晶片電性地連接,一端部藉由樹脂封裝層覆蓋。然後,引線端子係由銅或銅合金構成,晶片銲墊係由合金Alloy-42或科伐(Kovar)合金構成。並且,晶片銲墊係構成引線端子之厚度以下之厚度。此外,本發明之合金Alloy-42係指鐵中含有鎳約42%之合金,本發明之科伐(Kovar)合金係指鐵中添加有鎳、鈷之合金。
此根據第一態樣之樹脂封裝型半導體裝置係如上述,由合金Alloy-42或科伐合金來構成晶片銲墊,以便相較於由銅合金等來構成晶片銲墊之情況,可縮小晶片銲墊之熱膨脹係數與半導體晶片之熱膨脹係數之差,因此即使中介焊錫層來將半導體晶片固定於晶片銲墊上之情況時,仍可縮小晶片銲墊之翹曲與半導體晶片之翹曲之差。具體而言,合金Alloy-42及科伐合金之膨脹係數分別為4~8 ppm/K程度及5~7 ppm/K程度,兩者均比銅合金之熱膨脹係數(17ppm/K程度)接近半導體晶片(矽基板)之熱膨脹係數(3~4 ppm/K程度),因此可縮小焊錫接合時之半導體晶片之熱膨脹量與晶片銲墊之熱膨脹量之差。因此,中介焊錫來將半導體晶片固定於晶片銲墊上時,可縮小因溫度降低所產生
之晶片銲墊之翹曲與半導體晶片之翹曲之差,因此可減低加在半導體晶片之應力。藉此,可抑制於半導體晶片發生裂痕等損傷。而且,藉由將晶片銲墊構成引線端子之厚度以下之厚度,即使由合金Alloy-42或科伐合金來構成晶片銲墊,仍可容易地形成晶片銲墊,因此可容易地獲得半導體晶片與晶片銲墊之熱膨脹係數差小之樹脂封裝型半導體裝置。而且,藉由將晶片銲墊構成引線端子之厚度以下之厚度,可謀求樹脂封裝型半導體裝置之薄型化。
而且,第一態樣係藉由與構成晶片銲墊之合金Alloy-42或科伐合金不同之材料之銅或銅合金,來構成引線端子,以便與由構成晶片銲墊之材料之合金Alloy-42或科伐合金來構成引線端子之情況不同,可使引線端子之熱膨脹係數(17 ppm/K程度)與含玻璃環氧樹脂等之安裝基板之熱膨脹係數(例如17 ppm/K程度)約略相同。因此,將樹脂封裝型半導體裝置予以表面安裝於安裝基板上時,即使於樹脂封裝型半導體裝置及安裝基板等加入溫度變化循環之情況時,仍可減低加在電性連接引線端子與安裝基板之焊錫接合部之熱應力。藉此,即使由合金Alloy-42或科伐合金來構成晶片銲墊之情況時,仍可抑制於焊錫接合部產生龜裂,因此可抑制起因於焊錫接合部產生龜裂,引線端子與安裝基板之電性連接分離之不便。其結果,可抑制半導體晶片損傷,同時可抑制樹脂封裝型半導體裝置之安裝可靠性降低。
根據本發明之第二態樣之樹脂封裝型半導體裝置具備:
半導體晶片,其係包含矽基板;晶片銲墊,其係中介焊錫層而固定有半導體晶片;樹脂封裝層,其係封裝半導體晶片;及複數引線端子,其係與半導體晶片電性地連接,一端部藉由樹脂封裝層覆蓋。然後,晶片銲墊及引線端子係由銅或銅合金構成,並且晶片銲墊係構成比引線端子之厚度大之0.25 mm以上之厚度。
此根據第二態樣之樹脂封裝型半導體裝置係如上述,藉由將晶片銲墊構成比引線端子之厚度大之0.25 mm以上之厚度,可使晶片銲墊具有充分強度,因此即使是由銅或銅合金來構成晶片銲墊之情況時,於中介焊錫層來將半導體晶片固定於晶片銲墊上時,仍可抑制晶片銲墊之翹曲變大。藉此,由於可減低加在半導體晶片之應力,因此可抑制於半導體晶片發生裂痕等損傷。而且,藉由將晶片銲墊之厚度與引線端子之厚度構成不同厚度,即使為增大晶片銲墊之厚度之情況,仍可抑制引線端子之厚度變大,故可容易地進行引線端子之形成及引線端子之彎曲加工等。藉此,可抑制半導體晶片損傷,同時提高樹脂封裝型半導體裝置之製造效率。
而且,第二態樣係藉由銅或銅合金來構成引線端子,可使引線端子之熱膨脹係數(17 ppm/K程度)與含玻璃環氧樹脂等之安裝基板之熱膨脹係數(例如17 ppm/K程度)約略相同。因此,將樹脂封裝型半導體裝置予以表面安裝於安裝基板上時,即使於樹脂封裝型半導體裝置及安裝基板等加入溫度變化循環之情況時,仍可減低加在電性連接引線端
子與安裝基板之焊錫接合部之熱應力。藉此,可抑制於焊錫接合部產生龜裂,因此可抑制起因於焊錫接合部產生龜裂,引線端子與安裝基板之電性連接分離之不便。其結果,可抑制半導體晶片損傷,同時可抑制樹脂封裝型半導體裝置之安裝可靠性降低。
於此情況下,晶片銲墊宜構成比引線端子之厚度大之0.5 mm以上之厚度。若如此地構成,可使晶片銲墊具有充分強度,因此即使由銅或銅合金來構成晶片銲墊之情況時,仍可於中介焊錫層來將半導體晶片固定於晶片銲墊上時,容易地抑制晶片銲墊之翹曲變大。藉此,由於可容易地減低加在半導體晶片之應力減低,因此可容易地抑制於半導體晶片發生裂痕等損傷。
於上述根據第一及第二態樣之樹脂封裝型半導體裝置,半導體晶片宜固定於晶片銲墊之一主面上;晶片銲墊宜配置為與一主面相反側之另一主面從樹脂封裝層露出。若如此地構成,由於可使從樹脂封裝層露出之晶片銲墊之另一方主面對於安裝基板之安裝面熱接觸,因此可經由晶片銲墊使半導體晶片之動作時所產生之熱傳遞至安裝基板。藉此,可抑制半導體晶片損傷,同時提高散熱性。
於上述根據第一及第二態樣之樹脂封裝型半導體裝置,於晶片銲墊藉由另一主面及側面所構成之角部上,宜設置有缺口部。若如此地構成,即使於水分等從晶片銲墊與樹脂封裝層之界面侵入之情況時,由於可增長到半導體晶片之侵入路徑,因此可使水分等難以到達半導體晶片。因
此,可抑制起因於到達半導體晶片之水分等膨脹而產生半導體晶片損傷該類不便,並且可抑制起因於水分等侵入到半導體晶片之可靠性降低。
於此情況下,晶片銲墊宜從俯視看來具有四角形狀;缺口部宜分別設置於藉由晶片銲墊之另一主面及晶片銲墊之側面所構成之4個角部。若如此地構成,即使於水分等從晶片銲墊與樹脂封裝層之界面侵入之情況時,仍可容易地使水分等難以到達半導體晶片,因此可容易地抑制起因於到達半導體晶片之水分等膨脹而產生半導體晶片損傷該類不便,並且可容易地抑制起因於水分等侵入到半導體晶片之可靠性降低。
於上述根據第一及第二態樣之樹脂封裝型半導體裝置,晶片銲墊宜具有比半導體晶片之平面積大之平面積;於晶片銲墊固定有半導體晶片之區域以外之特定區域上,設置有從一主面側貫通至另一主面側之開口部。若如此地構成,由於即使從晶片銲墊與樹脂封裝層之界面侵入之水分等到達固定有半導體晶片之晶片銲墊之一主面側,仍可經由開口部而於晶片銲墊之另一主面側被去除,因此可抑制水分等滯留於半導體晶片附近。因此,可更容易地抑制起因於到達半導體晶片之水分等熱膨脹而產生半導體晶片損傷該類不便。
於該情況下,開口部宜以從俯視看來包圍半導體晶片周圍之方式設置有複數個。若如此地構成,由於可經由複數開口部,將到達晶片銲墊之一主面側之水分等,於晶片銲
墊之另一主面側去除,因此可容易地抑制水分等滯留於半導體晶片附近。因此,可進一步更容易地抑制起因於到達半導體晶片之水分等膨脹而產生半導體晶片損傷該類不便。
根據本發明之第三態樣之樹脂封裝型半導體裝置之製造方法具備:形成包含引線端子之引線框架之步驟;與引線框架為別體之另外形成晶片銲墊之步驟;於晶片銲墊之一主面上,中介焊錫層來固定包含矽基板之半導體晶片之步驟;及至少將半導體晶片藉由樹脂封裝層來予以樹脂封裝之步驟。然後,形成引線框架之步驟包含:由銅或銅合金來構成引線框架之步驟;形成晶片銲墊之步驟包含:由合金Alloy-42或科伐(Kovar)合金來構成晶片銲墊之步驟;及將晶片銲墊構成引線框架之厚度以下之厚度之步驟。此外,本發明之合金Alloy-42係指鐵中含有鎳約42%之合金,本發明之科伐(Kovar)合金係指鐵中添加有鎳、鈷之合金。
此根據第三態樣之樹脂封裝型半導體裝置之製造方法係如上述,由合金Alloy-42或科伐合金來構成晶片銲墊,以便相較於由銅合金等來構成晶片銲墊之情況,可縮小晶片銲墊之熱膨脹係數與半導體晶片之熱膨脹係數之差,因此即使中介焊錫層來將半導體晶片固定於晶片銲墊上之情況時,仍可縮小晶片銲墊之翹曲與半導體晶片之翹曲之差。具體而言,合金Alloy-42及科伐合金之膨脹係數分別為4~8 ppm/K程度及5~7 ppm/K程度,兩者均比銅合金之熱膨脹
係數(17 ppm/K程度)接近半導體晶片(矽基板)之熱膨脹係數(3~4 ppm/K程度),因此可縮小焊錫接合時之半導體晶片之熱膨脹量與晶片銲墊之熱膨脹量之差。因此,中介焊錫來將半導體晶片固定於晶片銲墊上時,可縮小因溫度降低所產生之晶片銲墊之翹曲與半導體晶片之翹曲之差,因此可減低加在半導體晶片之應力。藉此,可抑制於半導體晶片發生裂痕等損傷。而且,藉由將晶片銲墊構成引線端子之厚度以下之厚度,即使由合金Alloy-42或科伐合金來構成晶片銲墊,仍可容易地形成晶片銲墊,因此可容易地製造半導體晶片與晶片銲墊之熱膨脹係數差小之樹脂封裝型半導體裝置。而且,藉由將晶片銲墊構成引線端子之厚度以下之厚度,可謀求樹脂封裝型半導體裝置之薄型化。
而且,第三態樣係藉由銅或銅合金,來構成引線框架,以便與利用合金Alloy-42或科伐合金來與晶片銲墊一體地形成引線框架之情況不同,可使引線框架之熱膨脹係數(17 ppm/K程度)與含玻璃環氧樹脂等之安裝基板之熱膨脹係數(例如17 ppm/K程度)約略相同。因此,將製造好之樹脂封裝型半導體裝置予以表面安裝於安裝基板上時,即使於樹脂封裝型半導體裝置及安裝基板等加入溫度變化循環之情況時,仍可減低加在電性連接引線端子與安裝基板之焊錫接合部之熱應力。藉此,即使由合金Alloy-42或科伐合金來構成晶片銲墊之情況時,仍可抑制於焊錫接合部產生龜裂,因此可抑制起因於焊錫接合部產生龜裂,引線端子與安裝基板之電性連接分離之不便。其結果,可抑制半
導體晶片損傷,同時可抑制樹脂封裝型半導體裝置之安裝可靠性降低。
根據本發明之第四態樣之樹脂封裝型半導體裝置之製造方法具備:形成包含引線端子之引線框架之步驟;與引線框架為別體之另外形成晶片銲墊之步驟;於晶片銲墊之一主面上,中介焊錫層來固定包含矽基板之半導體晶片之步驟;及至少將半導體晶片藉由樹脂封裝層來予以樹脂封裝之步驟。然後,形成引線框架之步驟包含:由銅或銅合金來構成引線框架之步驟;形成晶片銲墊之步驟包含:由銅或銅合金來構成晶片銲墊之步驟;及將晶片銲墊構成比引線框架之厚度大之0.25 mm以上之厚度之步驟。
此根據第四態樣之樹脂封裝型半導體裝置之製造方法係如上述,藉由將晶片銲墊構成比引線框架之厚度大之0.25 mm以上之厚度,可使晶片銲墊具有充分強度,因此即使是由銅或銅合金來構成晶片銲墊之情況時,於中介焊錫層來將半導體晶片固定於晶片銲墊上時,仍可抑制晶片銲墊之翹曲變大。藉此,由於可減低加在半導體晶片之應力因此可抑制於半導體晶片發生裂痕等損傷。而且,藉由將晶片銲墊之厚度與引線框架之厚度構成不同厚度,即使為增大晶片銲墊之厚度之情況,仍可抑制引線框架之厚度變大,故可容易地進行引線框架之形成及引線端子之彎曲加工等。藉此,可抑制半導體晶片損傷,同時提高樹脂封裝型半導體裝置之製造效率。
而且,第四態樣係藉由銅或銅合金來構成引線框架,可
使引線框架之熱膨脹係數(17 ppm/K程度)與含玻璃環氧樹脂等之安裝基板之熱膨脹係數(例如17 ppm/K程度)約略相同。因此,將樹脂封裝型半導體裝置予以表面安裝於安裝基板上時,即使於樹脂封裝型半導體裝置及安裝基板等加入溫度變化循環之情況時,仍可減低加在電性連接引線框架之引線端子與安裝基板之焊錫接合部之熱應力。藉此,可抑制於焊錫接合部產生龜裂,因此可抑制起因於焊錫接合部產生龜裂,引線端子與安裝基板之電性連接分離之不便。其結果,可抑制半導體晶片損傷,同時可抑制樹脂封裝型半導體裝置之安裝可靠性降低。
於此情況下,形成晶片銲墊之步驟宜包含將晶片銲墊構成比引線框架之厚度大之0.5 mm以上之厚度之步驟。若如此地構成,可使晶片銲墊具有充分強度,因此即使由銅或銅合金來構成晶片銲墊之情況時,仍可於中介焊錫層來將半導體晶片固定於晶片銲墊上時,容易地抑制晶片銲墊之翹曲變大。藉此,由於可容易地減低加在半導體晶片之應力,因此可容易地抑制於半導體晶片發生裂痕等損傷。
於上述根據第三及第四態樣之樹脂封裝型半導體裝置之製造方法,於將半導體晶片固定於晶片銲墊上之步驟後,宜進一步具備:藉由超音波接合,將固定有半導體晶片之晶片銲墊接合於引線框架之特定位置之步驟。若如此地構成,即使與引線框架為別體而另外形成晶片銲墊之情況時,由於可容易地將晶片銲墊接合於引線框架之特定位置,因此仍可容易地製造可抑制半導體晶片損傷之樹脂封
裝型半導體裝置。而且,藉由利用超音波接合來將晶片銲墊接合於引線框架,可抑制於藉由超音波接合以外之鉚接接合或點焊接來將晶片銲墊接合於引線框架之情況下所產生之各種不便。具體而言,藉由鉚接接合來將晶片銲墊接合於引線框架之情況時,由於需要用以進行鉚接接合之銷或模具等,因此具有零件數及製造設備增加之不便。而且,於藉由點焊接來將晶片銲墊接合於引線框架之情況時,由於焊接時之熱而存在有固定於晶片銲墊之半導體晶片蒙受熱損傷之不便。因此,藉由利用超音波接合來將晶片銲墊接合於引線框架,可抑制零件數及製造設備增加,並且可抑制於半導體晶片加以熱損傷之不便產生。
如以上,若根據本發明,可獲得可抑制半導體晶片損傷之樹脂封裝型半導體裝置。
而且,若根據本發明,可獲得可抑制半導體晶片損傷之樹脂封裝型半導體裝置之製造方法。
以下,根據圖式來說明將本發明予以具體化之實施型態。此外,於以下實施型態說明有關將本發明適用於樹脂封裝型半導體裝置之一例之QFP(Quad Flat Package:四平包)型之樹脂封裝型半導體裝置之情況。
圖1係表示已去除根據本發明之第一實施型態之樹脂封裝型半導體裝置之樹脂封裝層之一部分之狀態之全體立體
圖。圖2係表示已去除根據圖1所示之本發明之第一實施型態之樹脂封裝型半導體裝置之樹脂封裝層之一部分之狀態之俯視圖。圖3係沿著圖2之300-300線之剖面圖。圖4~圖6係用以說明根據圖1所示之本發明之第一實施型態之樹脂封裝型半導體裝置之晶片銲墊之構造之圖。首先,參考圖1~圖6來說明有關根據本發明之第一實施型態之樹脂封裝型半導體裝置100之構造。
如圖1~圖3所示,根據第一實施型態之樹脂封裝型半導體裝置100具備:半導體晶片1、固定有半導體晶片1之晶片銲墊10、複數引線端子21、及樹脂封裝層30。
半導體晶片1係具有於矽基板(未圖示)上形成有半導體層(未圖示)之結構,形成約300 μm之厚度。該半導體晶片1係中介由高熔點焊錫(Pb-5% Sn)等所構成之第一焊錫層2(參考圖1及圖3),來固定於晶片銲墊10之上面(一主面)10a上。亦即,半導體晶片1係於晶片銲墊10之上面10a上利用焊錫接合。此外,第一焊錫層2為本發明之「焊錫層」之一例。
而且,如圖2及圖5所示,晶片銲墊10係俯視看來實質上形成四角形狀,並且包含一體地連結之4個懸吊引線11。
於此,於第一實施型態,晶片銲墊10係由合金Alloy-42(Fe-42Ni合金)或科伐(Kovar)合金構成。而且,晶片銲墊10係構成後述引線端子21之厚度(約0.15 mm)以下之厚度。具體而言,晶片銲墊10構成約0.125 mm之厚度。而且,於藉由晶片銲墊10之下面(另一主面)10b及晶片銲墊10
之側面所構成之角部,如圖6所示設有缺口部12。該缺口部12設置於藉由晶片銲墊10之下面10b及晶片銲墊10之側面所構成之4個角部之各個。
而且,於第一實施型態,如圖2所示,晶片銲墊10係構成為具有比半導體晶片1之平面積大之平面積,於晶片銲墊10之上面10a之特定區域,如圖4及圖5所示設有用以固定半導體晶片1之晶片固定區域13。而且,於晶片銲墊10之晶片固定區域13以外之特定區域,如圖4~圖6所示形成從晶片銲墊10之上面10a側貫通至下面10b側之開口部14。該開口部14係以包圍晶片固定區域13(半導體晶片1)周圍之方式設置有複數個。藉此,即使於半導體晶片1附近滯留有水分等之情況,該水分等仍會經由開口部14而從晶片銲墊10之下面10b被去除。
而且,4個懸吊引線11係於晶片銲墊10之4個角部之各個逐一配置1個,俯視看來,形成擴散為放射狀。該4個懸吊引線11係為了於後述之引線框架20保持晶片銲墊10而設置。而且,4個懸吊引線11分別折曲,以便將晶片銲墊10下移安置。因此,第一實施型態之晶片銲墊10係如圖3所示,成為配置於比後述之內引線21b位於下方側之狀態。而且,晶片銲墊10配置為其下面10b從樹脂封裝層30之下面露出。此外,露出之晶片銲墊10之下面10b係中介第二焊錫層3而與安裝基板40之安裝面熱接觸。
而且,複數引線端子21係由磷青銅或無氧銅等銅系(銅或銅合金)材料構成,形成約0.15 mm之厚度。而且,如圖
1~圖3所示,複數引線端子21分別具有:外引線部21a,其係從樹脂封裝層30導出之部分;及內引線部(一方端部)21b,其係與半導體晶片1一同被樹脂封裝層30覆蓋。該外引線部21a係如圖3所示,引線端子21折曲為鷗翼形狀,並經由第三焊錫層4來電性連接(表面安裝)於安裝基板40。此外,安裝基板40係由玻璃環氧樹脂等構成。而且,內引線部21b係如圖1~圖3所示,經由接合金屬線(例如金線等)5來電性連接於半導體晶片1。亦即,半導體晶片1係對於安裝基板40電性地連接。
而且,複數引線端子21互呈分離,並且配置為從4方向包圍晶片銲墊10。具體而言,複數引線端子21係如圖2所示區分為分別包含特定數之引線端子21之4個群組,並且分別包含該特定數之引線端子21之4個群組配置為從4方向包圍晶片銲墊10。如上述藉由配置複數引線端子21,以便於4方向各取出特定數之鷗翼形狀之複數引線端子21。
而且,樹脂封裝層30係藉由例如環氧樹脂等熱硬化性樹脂構成,藉由將半導體晶片1或接合金屬線5等予以樹脂封裝而具有保護半導體晶片1或接合金屬線5等免於氣體或水分等之功能。而且,樹脂封裝層30係如圖2所示,俯視看來形成四角形狀。亦即,樹脂封裝層30俯視看來具有4道邊。從該四角形狀之樹脂封裝層30之4道邊,分別突出有特定數之引線端子21(外引線部21a)。
第一態樣係如上述,由合金Alloy-42或科伐合金來構成晶片銲墊10,以便相較於由銅合金等來構成晶片銲墊10之
情況,可縮小晶片銲墊10之熱膨脹係數與半導體晶片1之熱膨脹係數之差,因此即使中介第一焊錫層2來將半導體晶片1固定於晶片銲墊10上之情況時,仍可縮小晶片銲墊10之翹曲與半導體晶片1之翹曲之差。具體而言,合金Alloy-42及科伐合金之膨脹係數分別為4~8 ppm/K程度及5~7 ppm/K程度,兩者均比銅合金之熱膨脹係數(17 ppm/K程度)接近半導體晶片1(矽基板)之熱膨脹係數(3~4 ppm/K程度),因此可縮小焊錫接合時之半導體晶片1之熱膨脹量與晶片銲墊10之熱膨脹量之差。因此,中介第一焊錫層2來將半導體晶片1固定於晶片銲墊10上時,可縮小因溫度降低所產生之晶片銲墊10之翹曲與半導體晶片1之翹曲之差,因此可減低加在半導體晶片1之應力(半導體晶片1之翹曲)。藉此,可抑制於半導體晶片1發生裂痕等損傷。
而且,第一實施型態係藉由將晶片銲墊10構成引線端子21之厚度(約0.15 mm)以下之厚度之約0.125 mm之厚度,以便即使由合金Alloy-42或科伐合金來構成晶片銲墊10,仍可容易地形成晶片銲墊10,因此可容易地獲得半導體晶片1與晶片銲墊10之熱膨脹係數差小之樹脂封裝型半導體裝置100。
而且,第一實施型態係藉由將晶片銲墊10構成引線端子21之厚度以下之厚度,可謀求樹脂封裝型半導體裝置100之薄型化。
而且,第一態樣係藉由銅或銅合金來構成引線端子21,可使引線端子21之熱膨脹係數(17 ppm/K程度)與含玻璃環
氧樹脂等之安裝基板40之熱膨脹係數(例如17 ppm/K程度)約略相同,因此將樹脂封裝型半導體裝置100予以表面安裝於安裝基板40上時,即使於樹脂封裝型半導體裝置100及安裝基板40等加入溫度變化循環之情況時,仍可減低加在電性連接引線端子21與安裝基板40之焊錫接合部(第三焊錫層4)之熱應力。藉此,即使由合金Alloy-42或科伐合金來構成晶片銲墊10之情況時,仍可抑制於焊錫接合部(第三焊錫層4)產生龜裂,因此可抑制起因於焊錫接合部(第三焊錫層4)產生龜裂,引線端子21與安裝基板40之電性連接分離之不便。其結果,可抑制半導體晶片1損傷,同時可抑制樹脂封裝型半導體裝置100之安裝可靠性降低。
而且,第一實施型態係使晶片銲墊10之下面10b從樹脂封裝層30之下面露出,並且使露出之晶片銲墊10之下面10b經由第二焊錫層3而與安裝基板40之安裝面熱接觸,藉此可經由晶片銲墊10使半導體晶片1之動作時所產生之熱傳遞至安裝基板40,因此可抑制半導體晶片1損傷,同時提高散熱性。
而且,上述第一實施型態係於藉由晶片銲墊10之下面10b及晶片銲墊10之側面所構成之4個角部上,分別設置有缺口部12,以便即使於水分等從晶片銲墊10與樹脂封裝層30之界面侵入之情況時,由於可增長到半導體晶片1之侵入路徑,因此可使水分等難以到達半導體晶片1。因此,可抑制起因於到達半導體晶片1之水分等熱膨脹而產生半導體晶片1損傷該類不便,並且可抑制起因於水分等侵入
到半導體晶片1之可靠性降低。
而且,第一實施型態係藉由於晶片銲墊10之晶片固定區域13以外之特定區域上,設置有從上面10a側貫通至下面10b側之開口部14,以便即使從晶片銲墊10與樹脂封裝層30之界面侵入之水分等到達固定有半導體晶片1之晶片銲墊10之上面10a側,仍可經由開口部14而於晶片銲墊10之下面10b側被去除,因此可抑制水分等滯留於半導體晶片1附近。因此,可更容易地抑制起因於到達半導體晶片1之水分等熱膨脹而產生半導體晶片1損傷該類不便。
而且,第一實施型態係藉由將開口部14以從俯視看來包圍半導體晶片1周圍之方式設置有複數個,以便可經由複數開口部14,將到達晶片銲墊10之上面10a側之水分等,於晶片銲墊10之下面10b側容易地去除,因此可容易地抑制水分等滯留於半導體晶片1附近。
圖7~圖14係用以說明根據圖1所示之本發明之第一實施型態之樹脂封裝型半導體裝置之製造方法之圖。接著,參考圖1、圖3、圖4及圖6~圖14,來說明有關根據本發明之第一實施型態之樹脂封裝型半導體裝置100之製造方法。
首先,如圖7所示,藉由將磷青銅或無氧銅等銅系(銅或銅合金)材料所構成之具有約0.15 mm厚度之薄板,進行打穿沖壓加工或蝕刻加工等,以一體地形成引線框架20。此時,引線框架20構成為包含:複數引線端子21、圍壩(dam)構件22及定位孔23等。此外,引線框架20構成為不含晶片銲墊10。接著,如圖8所示,與引線框架20為別體
而另外形成晶片銲墊10。
於此,於第一實施型態,晶片銲墊10係藉由將合金Alloy-42或科伐合金所構成之具有約0.125 mm厚度之薄板,進行打穿沖壓加工或蝕刻加工等而形成。此時,晶片銲墊10係俯視看來形成四角形狀,並且如圖6所示,於藉由晶片銲墊10之下面10b及晶片銲墊10之側面所構成之4個角部,分別形成缺口部12。而且,如圖8所示,於晶片銲墊10之4個角部,分別一體地形成俯視看來呈放射狀擴散之懸吊引線11。
而且,於第一實施型態,晶片銲墊10係形成具有比半導體晶片1之平面積大之平面積,並且以包圍固定有半導體晶片1之晶片固定區域13周圍之方式,形成從上面10a側貫通至下面10b之複數開口部14(參考圖4及圖6)。
接著,如圖9所示,於晶片銲墊10之晶片固定區域13(參考圖8),中介第一焊錫層2來固定半導體晶片1。具體而言,於晶片銲墊10之晶片固定區域13,塗布含高熔點焊錫等之焊錫膏(未圖示)後,於該焊錫膏上載置半導體晶片1。接著,將載置有半導體晶片1之晶片銲墊10放入回焊爐內,熔融焊錫膏。此外,回焊溫度約為例如350℃。然後,藉由冷卻已熔融之焊錫膏來形成第一焊錫層2。藉此,半導體晶片1會中介第一焊錫層2來固定於晶片銲墊10之上面10a上。
接著,如圖10及圖11所示,折曲4個懸吊引線11,並且將懸吊引線11之前端部分別連接於引線框架20之特定位
置。藉此,如圖11所示,晶片銲墊10係於比內引線部21b配置在下方側之狀態下,連接於引線框架20。此時,如圖12所示,引線框架20與懸吊引線11之接合(連接)係藉由超音波接合來進行。
接著,如圖13所示,經由接合金屬線5來電性連接半導體晶片1之電極墊與內引線部21b。然後,如圖14所示,利用轉換成形裝置等,並藉由樹脂封裝層30來將引線端子21之內引線部21b、半導體晶片1、接合金屬線5及晶片銲墊10予以樹脂封裝。此外,晶片銲墊10之下面10b係如圖3所示,構成為從樹脂封裝層30之下面露出。
接著,分別切斷懸吊引線11始於樹脂封裝層30之突出部、引線端子21(外引線部21a)及圍壩構件22。最後,將外引線部21a在樹脂封裝層30之外部折曲為鷗翼形狀。如此來製造圖1所示之根據本發明之第一實施型態之樹脂封裝型半導體裝置100。
於根據第一實施型態之樹脂封裝型半導體裝置100之製造方法,如上述藉由超音波接合,將晶片銲墊10之懸吊引線11分別接合於引線框架20之特定位置,以便即使與引線框架20為別體而另外形成晶片銲墊10之情況時,仍可容易地將晶片銲墊10接合於引線框架20之特定位置,因此可容易地製造可抑制半導體晶片1損傷之樹脂封裝型半導體裝置100。
而且,第一實施型態係藉由利用超音波接合來將晶片銲墊10接合於引線框架20,可抑制於藉由超音波接合以外之
鉚接接合或點焊接來將晶片銲墊10接合於引線框架20之情況下所產生之各種不便。具體而言,藉由鉚接接合來將晶片銲墊10接合於引線框架20之情況時,由於需要用以進行鉚接接合之銷或模具等,因此具有零件數及製造設備增加之不便。而且,於藉由點焊接來將晶片銲墊10接合於引線框架20之情況時,由於焊接時之熱而存在有固定於晶片銲墊10之半導體晶片1蒙受熱損傷之不便。因此,藉由利用超音波接合來將晶片銲墊10接合於引線框架20,可抑制零件數及製造設備增加,並且可抑制於半導體晶片1加以熱損傷之不便產生。
接著,說明有關用以確認上述第一實施型態之效果所進行之實驗。於該實驗中,為了確認晶片銲墊之材質對於半導體晶片之裂痕發生率所造成之影響,測定改變晶片銲墊之材質之情況下之半導體晶片之翹曲量及半導體晶片之裂痕發生率。具體而言,利用與上述製造方法同樣之方法,於晶片銲墊上中介焊錫層(第一焊錫層)來固定半導體晶片,藉此製作實施例1及比較例之試料。此外,實施例1係於含合金Alloy-42之晶片銲墊上固定有半導體晶片之試料,比較例係於含銅系(銅或銅合金)材料之晶片銲墊上固定有半導體晶片之試料。而且,固定於晶片銲墊上之半導體晶片之晶片尺寸,係實施例1及比較例兩者均為一邊長度7 mm之正方形形狀即7 mm□之半導體晶片、及一邊長度5 mm之正方形形狀即5 mm□之半導體晶片兩種。而且,實施例1之試料數及比較例之試料數係每一晶片尺寸各10
個。而且,晶片銲墊之厚度係實施例1及比較例兩者均約0.125 mm。
圖15係表示固定於晶片銲墊上之半導體晶片之翹曲量之測定方法之概略圖。參考圖15,半導體晶片之翹曲量a係藉由半導體晶片1中央之高度位置與半導體晶片1端部之高度位置之差來求出。而且,半導體晶片1之翹曲量a係利用基恩斯(KEYENCE)公司製之紅外線非接觸變位計(LT-8010)來測定。然後,取各10個測定結果之平均值來作為半導體晶片1之平均翹曲量。而且,半導體晶片1之裂痕發生率係藉由目視觀察來確認裂痕有無後,以全體個數(10個)除以存在裂痕之半導體晶片1之個數來算出。於表1表示此等結果。
如上述表1所示,比較實施例1與比較例之結果,判明半導體晶片之平均翹曲量係實施例1那方變得非常小於比較例。具體而言,就固定有7 mm□之半導體晶片之試料而言,於利用含銅及銅合金之晶片銲墊之比較例,半導體晶片之平均翹曲量為70 μm,相對地,於利用含合金Alloy-42之晶片銲墊之實施例1,半導體晶片之平均翹曲量為7.6 μm,其為比較例之約1/9之值。而且,就固定有5 mm□之半導體晶片之試料而言,於比較例,半導體晶片之平均翹
曲量為25 μm,相對地,於實施例1,半導體晶片之平均翹曲量為3.6 μm,其為比較例之約1/7之值。而且,半導體晶片之裂痕發生率在比較例均為100%,相對地,於實施例1均為0%。
如以上,確認藉由與半導體晶片(矽基板)之熱膨脹係數之差小之合金Alloy-42來構成晶片銲墊,即使晶片銲墊之厚度約0.125 mm,仍可減低固定於晶片銲墊上之半導體晶片之翹曲量。而且,確認由於裂痕發生率強烈受到半導體晶片翹曲量之影響,因此藉由減低半導體晶片翹曲量,亦可減低裂痕發生率。而且,確認藉由合金Alloy-42來構成晶片銲墊,即使固定有更大晶片尺寸之半導體晶片之情況時,仍可抑制裂痕發生。此外,實施例1係利用含合金Alloy-42之晶片銲墊,但即使利用含與合金Alloy-42之熱膨脹係數(4~8 ppm/K程度)之差小之科伐合金(熱膨脹係數:5~7 ppm/K程度)之晶片銲墊之情況時,據判仍可獲得與上述同樣之效果。
圖16係根據本發明之第二實施型態之樹脂封裝型半導體裝置之剖面圖,圖17係根據圖16所示之本發明之第二實施型態之樹脂封裝型半導體裝置之晶片銲墊之俯視圖。圖18係沿著圖17之500-500線之剖面圖。接著,參考圖16~圖18來說明有關根據第二實施型態之樹脂封裝型半導體裝置200之構造。此外,關於樹脂封裝型半導體裝置200之晶片銲墊110以外之構造,由於與上述第一實施型態相同,因
此省略其說明。
於此根據第二實施型態之樹脂封裝型半導體裝置200,與上述第一實施型態不同,晶片銲墊110係由銅或銅合金構成。而且,如圖16所示,晶片銲墊110係構成比引線端子21之厚度(約0.15 mm)大之厚度。具體而言,晶片銲墊110構成約0.25 mm之厚度,更宜構成約0.5 mm之厚度。此外,晶片銲墊110之其他結構係與上述第一實施型態之晶片銲墊10(參考圖4~圖6)之結構相同。亦即,晶片銲墊110係如圖17及圖18所示,包含一體地連結之4個懸吊引線111。而且,於藉由晶片銲墊110之下面(另一主面)110b及晶片銲墊110之側面所構成之角部,如圖18所示設有缺口部112。而且,於晶片銲墊110之上面(一主面)110a,設有固定半導體晶片1之晶片固定區域113,並以包圍該晶片固定區域113周圍之方式,設有從上面110a側貫通至下面110b之開口部114。
第二實施型態係如上述,藉由將晶片銲墊110構成比引線端子21之厚度大之約0.25 mm之厚度,更宜構成約0.5 mm之厚度,可使晶片銲墊110具有充分強度,因此即使由銅或銅合金來構成晶片銲墊110之情況下,中介第一焊錫層2來將半導體晶片1固定於晶片銲墊110上時,可抑制晶片銲墊110之翹曲變大。藉此,由於可減低加在半導體晶片1之應力(半導體晶片1之翹曲),因此可抑制於半導體晶片1發生裂痕等損傷。
而且,第二實施型態係藉由使晶片銲墊110之厚度與引
線端子21之厚度不同而構成,以便即使增大晶片銲墊110之情況下,仍可抑制引線端子21之厚度變大,因此可容易地進行引線端子21之形成及引線端子21之彎曲加工。藉此,可抑制半導體晶片1損傷,同時提高樹脂封裝型半導體裝置之製造效率。
此外,第二實施型態之其他效果係與上述第一實施型態相同。
接著,參考圖7及圖16~圖18,來說明有關根據本發明之第二實施型態之樹脂封裝型半導體裝置200之製造方法。
首先,如圖7所示,藉由與上述第一實施型態同樣之方法,來形成與上述第一實施型態同樣之引線框架20。接著,如圖17及圖18所示,藉由將銅或銅合金所構成之具有約0.25 mm厚度,更宜具有約0.5 mm厚度之薄板,進行打穿沖壓加工或蝕刻加工等,以形成晶片銲墊110。此時,關於材質及厚度以外之晶片銲墊110之結構,係與上述第一實施型態同樣地構成。其後,利用與上述第一實施型態同樣之製造方法,進行到外引線部21a之彎曲加工為止。藉此,製造圖16所示之根據本發明之第二實施型態之樹脂封裝型半導體裝置200。
接著,說明有關用以確認上述第二實施型態之效果所進行之實驗。於該實驗中,為了確認晶片銲墊之厚度對於半導體晶片之裂痕發生率所造成之影響,測定改變晶片銲墊之厚度之情況下之半導體晶片之翹曲量及半導體晶片之裂痕發生率。具體而言,利用與上述製造方法同樣之方法,
於晶片銲墊上中介焊錫層(第一焊錫層)來固定半導體晶片,藉此製作實施例2及實施例3之試料。而且,晶片銲墊均由銅系(銅或銅合金)材料構成,僅使其厚度變化。亦即,實施例2係於具有約0.25 mm厚度之含銅系材料之晶片銲墊上固定有半導體晶片之試料,實施例3係於具有約0.5 mm厚度之含銅系材料之晶片銲墊上固定有半導體晶片之試料。而且,固定於晶片銲墊上之半導體晶片之晶片尺寸係與上述第一實施型態(實施例1及比較例)相同,實施例2及實施例3兩者均為一邊長度7 mm之正方形形狀即7 mm□之半導體晶片、及一邊長度5 mm之正方形形狀即5 mm□之半導體晶片兩種。並且,實施例2之試料數及實施例3之試料數係每一晶片尺寸各10個。此外,半導體晶片之翹曲量及半導體晶片之裂痕發生率均藉由與上述第一實施型態同樣之方法測定。將此等結果與上述第一實施型態之比較例一同表示於表2。
如上述表2所示,比較實施例2與比較例之結果,判明半導體晶片之平均翹曲量係實施例2那方小於比較例。具體而言,就固定有7 mm□之半導體晶片之試料而言,於利用具有約0.125 mm厚度之晶片銲墊之比較例,半導體晶片之
平均翹曲量為70 μm,相對地,於利用具有約0.25 mm之厚度之晶片銲墊之實施例2,半導體晶片之平均翹曲量為65 μm。而且,就固定有5 mm□之半導體晶片之試料而言,於比較例,半導體晶片之平均翹曲量為25 μm,相對地,於實施例2,半導體晶片之平均翹曲量為22μm
而且,半導體晶片之裂痕發生率就固定有7 mm□之半導體晶片之試料而言,實施例2及比較例兩者均為100%,雖未能確認實施例2對於比較例之優越性,但就固定有5 mm□之半導體晶片之試料而言,於比較例,半導體晶片之裂痕發生率為100%,相對地,於實施例2,半導體晶片之裂痕發生率為60%,確認實施例2對於比較例之優越性。
而且,如上述表2所示,比較實施例3與比較例之結果,判明半導體晶片之平均翹曲量係實施例3那方小於比較例。具體而言,就固定有7 mm□之半導體晶片之試料而言,於利用具有約0.5 mm厚度之晶片銲墊之實施例3,半導體晶片之平均翹曲量為34.2 μm。而且,就固定有5 mm□之半導體晶片之試料而言,半導體晶片之平均翹曲量為13 μm。此等值均小,約為比較例之1/2。而且,半導體晶片之裂痕發生率於實施例3均為0%。
如以上,確認藉由增大晶片銲墊厚度,即使由銅系材料構成晶片銲墊之情況下,可縮小固定於晶片銲墊上之半導體晶片之翹曲量。而且,確認藉由縮小半導體晶片之翹曲量,可減低半導體晶片之裂痕發生率。以外,於實施例2確認於半導體晶片之晶片尺寸較小之範圍內,減低半導體
晶片之裂痕發生率之效果甚大。而且,於實施例3,確認即使為半導體晶片之晶片尺寸大之情況下,減低半導體晶片之裂痕發生率之效果仍甚大。
此外,本次所揭示之實施型態應於所有方面視為例示而非限制。本發明之範圍並非藉由上述實施型態之說明,而是藉由申請專利範圍來表示,並進一步包含與申請專利範圍均等之含意及範圍內之所有變更。
例如上述第一及第二實施型態係例示將本發明適用於QFP型樹脂封裝型半導體裝置,但本發明不限於此,若為具備晶片銲墊之樹脂封裝型半導體裝置均可,亦可將本發明適用於QFP型以外之樹脂封裝型半導體裝置。作為QFP型以外之樹脂封裝型半導體裝置可考慮例如QFP(Quad Flat Non-Leaded Package:四平包無引線)型、QFJ(Quad Flat J-lead Package:四平包J型引腳)型、SOP(Small Qutline Package:小外形封裝)型及SOJ(Small Qutline J-lead Package:小外形J型引線封裝)型等樹脂封裝型半導體裝置。
而且,上述第一及第二實施型態係表示以晶片銲墊之底面從樹脂封裝層之底面露出之方式,來構成樹脂封裝型半導體裝置之例,但本發明不限於此,以晶片銲墊之底面由樹脂封裝層覆蓋之方式來構成樹脂封裝型半導體裝置亦可。
而且,上述第一及第二實施型態係表示於藉由晶片銲墊之下面及晶片銲墊之側面所構成之4個角部,分別設置缺
口部之例,但本發明不限於此,於藉由晶片銲墊之下面及晶片銲墊之側面所構成之角部之一部分設置缺口部亦可。而且,亦可於晶片銲墊不設置缺口部。
而且,上述第一及第二實施型態係表示於晶片銲墊,設置從上面側貫通至下面側之開口部複數個之例,但本發明不限於此,於晶片銲墊僅設置1個從上面側貫通至下面側之開口部亦可。而且,於晶片銲墊不設置開口部而構成亦可。
而且,上述第一及第二實施型態係表示於樹脂封裝型半導體裝置之製造步驟中,藉由超音波接合來接合(連接)晶片銲墊之懸吊引線與引線框架之例,但本發明不限於此,藉由超音波接合以外之接合方法來連接晶片銲墊之懸吊引線與引線框架亦可。例如藉由鉚接接合或點焊接來連接晶片銲墊之懸吊引線與引線框架亦可。而且,將本發明適用於QFN型樹脂封裝型半導體裝置等之情況時,不連接晶片銲墊與引線框架並製造樹脂封裝型半導體裝置亦可。
而且,上述第一及第二實施型態係表示於晶片銲墊上固定半導體晶片後,再將固定有半導體晶片之晶片銲墊連接於引線框架之例,但本發明不限於此,將晶片銲墊連接於引線框架後,再於引線框架之晶片銲墊上固定半導體晶片亦可。
而且,上述第一實施型態係表示將晶片銲墊之厚度構成比引線端子之厚度小之厚度之例,但本發明不限於此,將晶片銲墊之厚度構成與引線端子之厚度相同之厚度亦可。
1‧‧‧半導體晶片
2‧‧‧第一焊錫層(焊錫層)
3‧‧‧第二焊錫層
4‧‧‧第三焊錫層
5‧‧‧接合金屬線
10,110‧‧‧晶片銲墊
10a,110a‧‧‧上面(一主面)
10b,110b‧‧‧下面(另一主面)
11,111‧‧‧懸吊引線
12,112‧‧‧缺口部
13,113‧‧‧晶片固定區域
14,114‧‧‧開口部
20‧‧‧引線框架
21‧‧‧引線端子
21a‧‧‧外引線部
21b‧‧‧內引線部(一端部)
22‧‧‧圍壩(dam)構件
30‧‧‧樹脂封裝層
40‧‧‧安裝基板
100,200‧‧‧樹脂封裝型半導體裝置
圖1係表示已去除根據本發明之第一實施型態之樹脂封裝型半導體裝置之樹脂封裝層之一部分之狀態之全體立體圖。
圖2係表示已去除根據圖1所示之本發明之第一實施型態之樹脂封裝型半導體裝置之樹脂封裝層之一部分之狀態之俯視圖。
圖3係沿著圖2之300-300線之剖面圖。
圖4係表示根據圖1所示之本發明之第一實施型態之樹脂封裝型半導體裝置之晶片銲墊之全體立體圖。
圖5係表示根據圖1所示之本發明之第一實施型態之樹脂封裝型半導體裝置之晶片銲墊之俯視圖。
圖6係沿著圖5之400-400線之剖面圖。
圖7係用以說明根據圖1所示之本發明之第一實施型態之樹脂封裝型半導體裝置之製造方法之俯視圖。
圖8係用以說明根據圖1所示之本發明之第一實施型態之樹脂封裝型半導體裝置之製造方法之俯視圖。
圖9係用以說明根據圖1所示之本發明之第一實施型態之樹脂封裝型半導體裝置之製造方法之立體圖。
圖10係用以說明根據圖1所示之本發明之第一實施型態之樹脂封裝型半導體裝置之製造方法之俯視圖。
圖11係用以說明根據圖1所示之本發明之第一實施型態之樹脂封裝型半導體裝置之製造方法之剖面圖。
圖12係用以說明根據圖1所示之本發明之第一實施型態
之樹脂封裝型半導體裝置之製造方法之剖面圖。
圖13係用以說明根據圖1所示之本發明之第一實施型態之樹脂封裝型半導體裝置之製造方法之俯視圖。
圖14係用以說明根據圖1所示之本發明之第一實施型態之樹脂封裝型半導體裝置之製造方法之俯視圖。
圖15係表示固定於晶片銲墊上之半導體晶片之翹曲量之測定方法之概略圖。
圖16係根據本發明之第二實施型態之樹脂封裝型半導體裝置之剖面圖。
圖17係根據圖16所示之本發明之第二實施型態之樹脂封裝型半導體裝置之晶片銲墊之俯視圖。
圖18係沿著圖17之500-500線之剖面圖。
1‧‧‧半導體晶片
2‧‧‧第一焊錫層(焊錫層)
5‧‧‧接合金屬線
10‧‧‧晶片銲墊
10a‧‧‧上面(一主面)
11‧‧‧懸吊引線
14‧‧‧開口部
21‧‧‧引線端子
21a‧‧‧外引線部
21b‧‧‧內引線部(一端部)
30‧‧‧樹脂封裝層
100‧‧‧樹脂封裝型半導體裝置
Claims (12)
- 一種樹脂封裝型半導體裝置,其特徵為包含:半導體晶片,其係包含矽基板;晶片銲墊,其係中介焊錫層而固定有前述半導體晶片;樹脂封裝層,其係封裝前述半導體晶片;複數引線端子,其係與前述半導體晶片電性地連接,一端部藉由前述樹脂封裝層覆蓋;及懸吊引線,其與前述晶片銲墊一體成型,同時相對於前述晶片銲墊折曲,其中前述引線端子係由銅或銅合金構成,前述晶片銲墊係由合金Alloy-42或科伐(Kovar)合金構成,且形成前述晶片銲墊之薄板之厚度係小於形成前述引線之薄板之厚度。
- 一種樹脂封裝型半導體裝置,其特徵為包含:半導體晶片,其係包含矽基板;晶片銲墊,其係中介焊錫層而固定有前述半導體晶片;樹脂封裝層,其係封裝前述半導體晶片;複數引線端子,其係與前述半導體晶片電性地連接,一端部藉由前述樹脂封裝層覆蓋;及懸吊引線,其與前述晶片銲墊一體成型,同時相對於前述晶片銲墊折曲,其中 前述晶片銲墊及前述引線端子係由銅或銅合金構成,前述晶片銲墊係構成比前述引線端子之厚度大,當正方形形狀之前述半導體晶片之一邊長為5 mm以下時,前述晶片銲墊之厚度為0.25 mm以上;當前述半導體晶片之一邊長超過5 mm時,前述晶片銲墊之厚度為0.5 mm以上。
- 如請求項1或2之樹脂封裝型半導體裝置,其中前述半導體晶片係固定於前述晶片銲墊之一主面上;前述晶片銲墊係配置為與一主面相反側之另一主面從前述樹脂封裝層露出。
- 如請求項1或2之樹脂封裝型半導體裝置,其中於前述晶片銲墊於藉由另一主面及側面所構成之角部上,設置有缺口部。
- 如請求項4之樹脂封裝型半導體裝置,其中前述晶片銲墊係以從俯視看來具有四角形狀;前述缺口部係分別設置於藉由前述晶片銲墊之另一主面及前述晶片銲墊之側面所構成之4個角部。
- 如請求項1或2之樹脂封裝型半導體裝置,其中前述晶片銲墊係具有比前述半導體晶片之平面積大之平面積;於前述晶片銲墊固定有前述半導體晶片之區域以外之特定區域上,設置有從一主面側貫通至另一主面側之開口部。
- 如請求項6之樹脂封裝型半導體裝置,其中前述開口部係以從俯視看來包圍前述半導體晶片周圍之方式設置有 複數個。
- 如請求項1或2之樹脂封裝型半導體裝置,其中前述懸吊引線之位置係於前述樹脂封裝層之端面位置中,以靠近前述引線端子下表面之方式設置。
- 一種樹脂封裝型半導體裝置之製造方法,其特徵為包含:形成包含引線端子之引線框架之步驟;形成與前述引線框架為不同物體、且一體連結有折曲形成之懸吊引線的晶片銲墊之步驟;於前述晶片銲墊之一主面上,中介焊錫層來固定包含矽基板之半導體晶片之步驟;及至少將前述半導體晶片藉由樹脂封裝層來予以樹脂封裝之步驟,其中形成前述引線框架之步驟包含:由銅或銅合金來構成前述引線框架之步驟;形成前述晶片銲墊之步驟包含:由合金Alloy-42或科伐(Kovar)合金來構成前述晶片銲墊,同時以小於形成前述引線之薄板厚度之厚度構成形成前述晶片銲墊之薄板之步驟。
- 一種樹脂封裝型半導體裝置之製造方法,其特徵為包含:形成包含引線端子之引線框架之步驟;形成與前述引線框架為不同物體,且一體連結有折曲形成之懸吊引線的晶片銲墊之步驟; 於前述晶片銲墊之一主面上,中介焊錫層來固定包含矽基板之半導體晶片之步驟;及至少將前述半導體晶片藉由樹脂封裝層來予以樹脂封裝之步驟,其中形成前述引線框架之步驟包含:由銅或銅合金來構成前述引線框架之步驟;形成前述晶片銲墊之步驟包含:由銅或銅合金來構成前述晶片銲墊之步驟;及將前述晶片銲墊構成為比前述引線框架之厚度大,且當正方形形狀之前述半導體晶片之一邊長為5 mm以下時,將前述晶片銲墊之厚度構成為0.25 mm以上;當前述半導體晶片之一邊長超過5 mm時,將前述晶片銲墊之厚度構成為0.5 mm以上。
- 如請求項9或10之樹脂封裝型半導體裝置之製造方法,其中於將前述半導體晶片固定於前述晶片銲墊上之步驟後,進一步包含:藉由超音波接合,將固定有前述半導體晶片之前述晶片銲墊接合於前述引線框架之特定位置之步驟。
- 如請求項9或10之樹脂封裝型半導體裝置之製造方法,其中在前述樹脂封裝之步驟前,進一步包含將前述懸吊引線之前端部連接至前述引線框架下表面之步驟。
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Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1696803B1 (en) | 2003-11-17 | 2016-09-28 | Boston Scientific Limited | Systems relating to associating a medical implant with a delivery device |
EP1765218B1 (en) | 2004-06-14 | 2014-06-11 | Boston Scientific Limited | An implantable sling for treating urinary incontinence |
EP3533416A1 (en) | 2005-07-25 | 2019-09-04 | Boston Scientific Limited | Pelvic floor repair system |
JP5089184B2 (ja) * | 2007-01-30 | 2012-12-05 | ローム株式会社 | 樹脂封止型半導体装置およびその製造方法 |
US9059187B2 (en) * | 2010-09-30 | 2015-06-16 | Ibiden Co., Ltd. | Electronic component having encapsulated wiring board and method for manufacturing the same |
US9425139B2 (en) | 2012-09-12 | 2016-08-23 | Marvell World Trade Ltd. | Dual row quad flat no-lead semiconductor package |
JP2014207430A (ja) | 2013-03-21 | 2014-10-30 | ローム株式会社 | 半導体装置 |
CN104838494B (zh) * | 2013-12-05 | 2017-06-23 | 新电元工业株式会社 | 引线框架、模具、附带贴装元件的引线框架的制造方法 |
JP2015176907A (ja) * | 2014-03-13 | 2015-10-05 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP6494465B2 (ja) * | 2015-08-03 | 2019-04-03 | エイブリック株式会社 | 半導体装置の製造方法 |
US10504736B2 (en) * | 2015-09-30 | 2019-12-10 | Texas Instruments Incorporated | Plating interconnect for silicon chip |
US10446137B2 (en) * | 2016-09-07 | 2019-10-15 | Microsoft Technology Licensing, Llc | Ambiguity resolving conversational understanding system |
JP6776840B2 (ja) * | 2016-11-21 | 2020-10-28 | オムロン株式会社 | 電子装置およびその製造方法 |
JP2020094933A (ja) * | 2018-12-13 | 2020-06-18 | 日立オートモティブシステムズ株式会社 | 熱式流量計 |
US10998256B2 (en) | 2018-12-31 | 2021-05-04 | Texas Instruments Incorporated | High voltage semiconductor device lead frame and method of fabrication |
US20210043466A1 (en) * | 2019-08-06 | 2021-02-11 | Texas Instruments Incorporated | Universal semiconductor package molds |
US11145578B2 (en) * | 2019-09-24 | 2021-10-12 | Infineon Technologies Ag | Semiconductor package with top or bottom side cooling and method for manufacturing the semiconductor package |
US11538768B2 (en) * | 2019-10-04 | 2022-12-27 | Texas Instruments Incorporated | Leadframe with ground pad cantilever |
IT201900025009A1 (it) | 2019-12-20 | 2021-06-20 | St Microelectronics Srl | Leadframe per dispositivi a semiconduttore, prodotto a semiconduttore e procedimento corrispondenti |
JP2022146271A (ja) * | 2021-03-22 | 2022-10-05 | ローム株式会社 | 半導体装置 |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62136059A (ja) * | 1985-12-09 | 1987-06-19 | Mitsubishi Electric Corp | 樹脂封止半導体装置用リ−ドフレ−ム |
JPH0758273A (ja) * | 1993-08-16 | 1995-03-03 | Sony Corp | リードフレーム及びそれを用いた半導体装置 |
JPH08162590A (ja) * | 1994-12-08 | 1996-06-21 | Hitachi Cable Ltd | リードフレーム |
JPH08316372A (ja) * | 1995-05-16 | 1996-11-29 | Toshiba Corp | 樹脂封止型半導体装置 |
JPH10335540A (ja) * | 1997-05-29 | 1998-12-18 | Sony Corp | 半導体装置及びその製造方法 |
JP3458057B2 (ja) * | 1998-03-12 | 2003-10-20 | 松下電器産業株式会社 | 樹脂封止型半導体装置 |
KR100297451B1 (ko) * | 1999-07-06 | 2001-11-01 | 윤종용 | 반도체 패키지 및 그의 제조 방법 |
JP3461332B2 (ja) * | 1999-09-10 | 2003-10-27 | 松下電器産業株式会社 | リードフレーム及びそれを用いた樹脂パッケージと光電子装置 |
JP4417541B2 (ja) * | 2000-10-23 | 2010-02-17 | ローム株式会社 | 半導体装置およびその製造方法 |
US6818973B1 (en) * | 2002-09-09 | 2004-11-16 | Amkor Technology, Inc. | Exposed lead QFP package fabricated through the use of a partial saw process |
JP3740116B2 (ja) * | 2002-11-11 | 2006-02-01 | 三菱電機株式会社 | モールド樹脂封止型パワー半導体装置及びその製造方法 |
CN100490140C (zh) * | 2003-07-15 | 2009-05-20 | 飞思卡尔半导体公司 | 双规引线框 |
US7327044B2 (en) * | 2005-01-21 | 2008-02-05 | Fox Electronics | Integrated circuit package encapsulating a hermetically sealed device |
JP5008832B2 (ja) | 2005-04-15 | 2012-08-22 | ローム株式会社 | 半導体装置及び半導体装置の製造方法 |
JP2006318996A (ja) | 2005-05-10 | 2006-11-24 | Matsushita Electric Ind Co Ltd | リードフレームおよび樹脂封止型半導体装置 |
US7262491B2 (en) * | 2005-09-06 | 2007-08-28 | Advanced Interconnect Technologies Limited | Die pad for semiconductor packages and methods of making and using same |
US20080079127A1 (en) * | 2006-10-03 | 2008-04-03 | Texas Instruments Incorporated | Pin Array No Lead Package and Assembly Method Thereof |
JP5089184B2 (ja) * | 2007-01-30 | 2012-12-05 | ローム株式会社 | 樹脂封止型半導体装置およびその製造方法 |
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