JP6776840B2 - 電子装置およびその製造方法 - Google Patents
電子装置およびその製造方法 Download PDFInfo
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- JP6776840B2 JP6776840B2 JP2016226044A JP2016226044A JP6776840B2 JP 6776840 B2 JP6776840 B2 JP 6776840B2 JP 2016226044 A JP2016226044 A JP 2016226044A JP 2016226044 A JP2016226044 A JP 2016226044A JP 6776840 B2 JP6776840 B2 JP 6776840B2
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- resin molded
- molded body
- wiring
- bent portion
- electronic device
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- 238000004519 manufacturing process Methods 0.000 title claims description 32
- 229920005989 resin Polymers 0.000 claims description 172
- 239000011347 resin Substances 0.000 claims description 172
- 238000000465 moulding Methods 0.000 claims description 41
- 238000000034 method Methods 0.000 claims description 39
- 239000000463 material Substances 0.000 claims description 26
- 230000008569 process Effects 0.000 claims description 13
- 239000000945 filler Substances 0.000 claims description 6
- 238000009751 slip forming Methods 0.000 claims description 3
- 239000000758 substrate Substances 0.000 description 38
- 239000000853 adhesive Substances 0.000 description 9
- 230000001070 adhesive effect Effects 0.000 description 9
- 238000001746 injection moulding Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 5
- 238000007641 inkjet printing Methods 0.000 description 5
- 229920000139 polyethylene terephthalate Polymers 0.000 description 5
- 239000005020 polyethylene terephthalate Substances 0.000 description 5
- 239000004743 Polypropylene Substances 0.000 description 4
- 239000012790 adhesive layer Substances 0.000 description 4
- 229920001971 elastomer Polymers 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 239000004417 polycarbonate Substances 0.000 description 4
- 229920000515 polycarbonate Polymers 0.000 description 4
- -1 polypropylene Polymers 0.000 description 4
- 229920001155 polypropylene Polymers 0.000 description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 3
- 239000004676 acrylonitrile butadiene styrene Substances 0.000 description 3
- 239000000806 elastomer Substances 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 239000004332 silver Substances 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000004952 Polyamide Substances 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 239000004734 Polyphenylene sulfide Substances 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 229920002647 polyamide Polymers 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 229920000069 polyphenylene sulfide Polymers 0.000 description 2
- 229920002799 BoPET Polymers 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 239000000443 aerosol Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000036772 blood pressure Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 230000007794 irritation Effects 0.000 description 1
- 239000011112 polyethylene naphthalate Substances 0.000 description 1
- 239000004814 polyurethane Substances 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 238000009864 tensile test Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
- H01L21/566—Release layers for moulds, e.g. release layers, layers against residue during moulding
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- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
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- H01L23/5387—Flexible insulating substrates
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- H05K1/02—Details
- H05K1/0277—Bendability or stretchability details
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- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/147—Structural association of two or more printed circuits at least one of the printed circuits being bent or folded, e.g. by using a flexible printed circuit
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
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- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
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- H—ELECTRICITY
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/148—Arrangements of two or more hingeably connected rigid printed circuit boards, i.e. connected by flexible means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/01—Tools for processing; Objects used during processing
- H05K2203/0191—Using tape or non-metallic foil in a process, e.g. during filling of a hole with conductive paste
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
- H05K2203/1305—Moulding and encapsulation
- H05K2203/1316—Moulded encapsulation of mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/14—Related to the order of processing steps
- H05K2203/1461—Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors
- H05K2203/1469—Circuit made after mounting or encapsulation of the components
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- Engineering & Computer Science (AREA)
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Structure Of Printed Boards (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
(電子装置の構成)
図1および図2を参照して、実施の形態1に係る電子装置100の概略的な構成について説明する。図1は、実施の形態1に係る電子装置100の概略的な構成を示す平面図である。図2は、図1のX−X線に沿った矢視断面図である。
次に、図3を参照して、実施の形態1に係る電子装置100の製造方法の一例について説明する。図3は、電子装置100の製造方法を説明する図である。図3(a)〜(d)には、それぞれ電子装置100を製造するための第1〜第4工程を説明するための図が示される。図3(a)において、左側が平面図、右側が側面図を示している。図3(b)には断面図が示される。図3(c)(d)において、左側が平面図、右側が平面図におけるX−X線に沿った矢視断面図を示している。
図3(a)に示されるように、まず、電子部品12a〜12eを、長方形状の仮固定シート200に接着剤(図示せず)により貼り付けて仮固定する。このとき、電子部品12a〜12eは、電極13a〜13eが形成された面が仮固定シート200に接するように貼り付けられる。
次に、図3(b)に示されるように、電子部品12a〜12eが仮固定された仮固定シート200を、第1型210と第2型220とを組み合わせることにより構成される成形型の内部に設置する。
図3(c)に示されるように、第2工程の射出成形により得られた構造体230を成形型から取り出す。構造体230は、成形型の空間221と同一形状(厚みt2)を有する樹脂成形体11と、成形型の空間222と同一形状(厚みt1)を有する屈曲部20とを備える。
図3(d)に示されるように、第3工程の後、樹脂成形体11の上面11aと屈曲部20の連続面20aとの上に所定パターンの配線30(30a〜30h)を形成する。
以上のように、電子装置100は、電子部品12と、電子部品12を埋設して固定する樹脂成形体11と、樹脂成形体11に連接する屈曲可能な屈曲部20とを備える。
(1)電子部品12を仮固定シート200に貼り付ける工程。
(2)仮固定シート200を成形型(第1型210および第2型220)内に配置し、成形型内に樹脂を充填させることにより、電子部品12が埋設された樹脂成形体11と、樹脂成形体11よりも薄い屈曲可能な屈曲部20とを一体成形する工程。
(3)仮固定シート200を樹脂成形体11から剥離することにより露出する、樹脂成形体11における仮固定シート200に接していた上面(シート接合面)11aと、屈曲部20における上面11aに連続する連続面20aとに、配線30を形成する工程。
本発明の実施の形態2に係る電子装置は、実施の形態1の電子装置100の変形例であり、電子部品と樹脂成形体とを含む本体部を複数備える。
本発明の実施の形態3に係る電子装置は、実施の形態1の電子装置100または実施の形態2の電子装置100Aの変形例であり、屈曲部20と本体部10の樹脂成形体11および本体部40の樹脂成形体41との材質が異なる。
上記の実施の形態1〜3では屈曲部20を樹脂材の射出成形により成形したが、実施の形態4に係る電子装置は、フレキシブル基板を屈曲部として用いる。
図6および図7を参照して、実施の形態4に係る電子装置100Bの構成を説明する。図6は、実施の形態4に係る電子装置100Bの概略的な構成を示す平面図である。図7は、図6のX−X線に沿った矢視断面図である。
次に、図8を参照して、実施の形態4に係る電子装置100Bの製造方法の一例について説明する。図8は、電子装置100Bの製造方法を説明する図である。図8(a)〜(d)には、それぞれ電子装置100Bを製造するための第1〜第4工程を説明するための図が示される。図8(a)において、左側が平面図、右側が側面図を示している。図8(b)には断面図が示される。図8(c)(d)において、左側が平面図、右側が平面図におけるX−X線に沿った矢視断面図を示している。
図8(a)に示されるように、まず、電子部品12a〜12eと屈曲部60とを、仮固定シート200に接着剤により貼り付けて仮固定する。このとき、電子部品12a〜12eは、電極13a〜13eが形成された面が仮固定シート200に接するように貼り付けられる。屈曲部60は、その一部のみが仮固定シート200に貼り付けられる。仮固定シート200への電子部品12a〜12eと屈曲部60との仮固定の方法は、実施の形態1の第1工程と同じであるため、詳細な説明を省略する。
次に、図8(b)に示されるように、電子部品12a〜12eおよび屈曲部60が仮固定された仮固定シート200を、第1型210と第2型220とを組み合わせることにより構成される成形型の内部に設置する。
図8(c)に示されるように、第2工程の射出成形により得られた構造体240を成形型から取り出す。構造体240は、電子部品12a〜12eを埋設するとともに、成形型の空間221と同一形状を有する樹脂成形体51と、樹脂成形体51に一部が埋設された屈曲部60とを備える。
図8(d)に示されるように、第3工程の後、樹脂成形体51の上面51aと屈曲部60の連続面60aとの上に所定パターンの配線30(30a〜30h)を形成する。配線30の形成方法は、実施の形態1の第4工程と同じである。
実施の形態3の電子装置100Bでは、樹脂成形体51は、屈曲部60の一部を埋設して支持する。これにより、接着剤等で接着する場合に比べて、屈曲部60と樹脂成形体51との接続の信頼性が高くなる。
(1)電子部品12と、屈曲可能な屈曲部60とを仮固定シート200に貼り付ける工程。
(2)仮固定シート200を成形型(第1型210と第2型220とを組み合わせた型)内に配置し、成形型内に樹脂を充填させることにより、電子部品12と屈曲部60の一部とが埋設された樹脂成形体51を成形する工程。
(3)仮固定シート200を樹脂成形体51から剥離することにより露出する、樹脂成形体51における仮固定シート200に接していた上面(シート接合面)51aに配線(第1配線)30を形成する工程。
本発明の実施の形態5に係る電子装置は、実施の形態4の電子装置100Bの変形例であり、フレキシブル基板である屈曲部60に予め配線が形成されている。
上面、12(12a〜12e),42(42a〜42c),71,76a,76b 電子部品、13a〜13e,43a〜43c 電極、20,60 屈曲部、20a,60a 連続面、30(30a〜30p),61(61a〜61c),72a,72b,77a,77c 配線、70,75,80 基板、81 導電層、90a,90b 導電性接着層、100,100A,100B,100C 電子装置、200 仮固定シート、210 第1型、211 凹部、220 第2型、221,222 空間、230,240 構造体。
Claims (11)
- 電子部品と、
前記電子部品を埋設して固定する樹脂成形体と、
前記樹脂成形体に連接する屈曲可能な屈曲部とを備える電子装置であって、
前記樹脂成形体は、前記屈曲部の一部を埋設して支持し、
前記樹脂成形体の表面は、前記電子部品を露出させる露出面を含み、
前記屈曲部の表面は、前記露出面と連続する連続面を含み、
前記電子装置は、さらに、
前記露出面と前記連続面との上に形成され、前記電子部品に接続する配線を備える、電子装置。 - 前記配線は、前記電子部品から前記連続面の上まで連続して形成される、請求項1に記載の電子装置。
- 前記配線は、
前記露出面の上に形成され、前記電子部品に接続する第1配線と、
前記連続面の上に予め形成され、前記第1配線に接続する第2配線とを含む、請求項1に記載の電子装置。 - 前記屈曲部の材料の破断時の伸び率は、前記樹脂成形体の材料の破断時の伸び率よりも大きい、請求項1から3のいずれか1項に記載の電子装置。
- 前記屈曲部は、破断時の伸び率が300%以上の樹脂により形成される、請求項4に記載の電子装置。
- 前記樹脂成形体は、破断時の伸び率が150%以下の樹脂により形成される、請求項5に記載の電子装置。
- 前記樹脂成形体はフィラーを含む、請求項1から6のいずれか1項に記載の電子装置。
- 電子部品をシートに貼り付ける工程と、
前記シートを2種類の成形型内に順に配置し、二色成形法により、前記電子部品が埋設された樹脂成形体と、前記樹脂成形体に連接する屈曲可能な屈曲部とを一体に成形する工程と、
前記シートを前記樹脂成形体から剥離することにより露出する、前記樹脂成形体における前記シートに接していたシート接合面と、前記屈曲部における前記シート接合面に連続する連続面とに、配線を形成する工程とを備える、電子装置の製造方法。 - 電子部品と、屈曲可能な屈曲部とをシートに貼り付ける工程と、
前記シートを成形型内に配置し、前記成形型内に樹脂を充填させることにより、前記電子部品と前記屈曲部の一部とが埋設された樹脂成形体を成形する工程と、
前記シートを前記樹脂成形体から剥離することにより露出する、前記樹脂成形体における前記シートに接していたシート接合面に第1配線を形成する工程とを備える、電子装置の製造方法。 - 前記屈曲部の表面は、前記シート接合面に連続する連続面を含み、
前記第1配線を形成する工程において、前記連続面の上にも前記第1配線を形成する、請求項9に記載の電子装置の製造方法。 - 前記屈曲部の表面に第2配線が予め形成されており、
前記貼り付ける工程において、前記第2配線が前記シートに対向するように前記屈曲部を前記シートに貼り付け、
前記第1配線を形成する工程において、前記第2配線に接続するように前記第1配線を形成する、請求項9に記載の電子装置の製造方法。
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JP2016226044A JP6776840B2 (ja) | 2016-11-21 | 2016-11-21 | 電子装置およびその製造方法 |
PCT/JP2017/033675 WO2018092407A1 (ja) | 2016-11-21 | 2017-09-19 | 電子装置およびその製造方法 |
CN201780060052.XA CN109792836B (zh) | 2016-11-21 | 2017-09-19 | 电子装置及其制造方法 |
US16/336,923 US11004699B2 (en) | 2016-11-21 | 2017-09-19 | Electronic device and method for manufacturing the same |
EP17871776.5A EP3544392B1 (en) | 2016-11-21 | 2017-09-19 | Electronic device and method for producing same |
TW106133028A TWI660650B (zh) | 2016-11-21 | 2017-09-27 | 電子裝置及其製造方法 |
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US20200035511A1 (en) | 2020-01-30 |
US11004699B2 (en) | 2021-05-11 |
EP3544392B1 (en) | 2021-08-11 |
EP3544392A4 (en) | 2020-01-29 |
CN109792836A (zh) | 2019-05-21 |
TWI660650B (zh) | 2019-05-21 |
EP3544392A1 (en) | 2019-09-25 |
CN109792836B (zh) | 2021-10-15 |
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TW201820943A (zh) | 2018-06-01 |
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