TWI660650B - 電子裝置及其製造方法 - Google Patents
電子裝置及其製造方法 Download PDFInfo
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- TWI660650B TWI660650B TW106133028A TW106133028A TWI660650B TW I660650 B TWI660650 B TW I660650B TW 106133028 A TW106133028 A TW 106133028A TW 106133028 A TW106133028 A TW 106133028A TW I660650 B TWI660650 B TW I660650B
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- Prior art keywords
- molded body
- resin molded
- wiring
- electronic device
- sheet
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Classifications
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Abstract
電子裝置(100)具備:電子零件(12);將電子零件(12)埋設並固定的樹脂成形體(11);及連接於樹脂成形體(11)的能夠彎曲的彎曲部(20)。例如,彎曲部(20)可與樹脂成形體(11)一體地成形。藉此,可使電子裝置(100)小型化及薄型化。
Description
本技術是有關於一種一部分能夠彎曲的電子裝置及其製造方法。
近年來,由於行動設備等中的超小型化的要求的提高,對搭載有電子零件的剛型的基板進行固定的場所受到限制。因此,已知有一種為了將未配置於同一平面上的多個剛型的基板連接而使用能夠彎曲的柔型的基板的技術。
圖11是表示將剛型的基板與柔型的基板組合而成的電子裝置的示例的圖。圖11所示的電子裝置具備剛型的基板70、剛型的基板75與柔型的基板80。
於剛型的基板70上形成有配線72a、配線72b,且搭載有連接於該配線72a、配線72b的電子零件71。於剛型的基板75上形成有配線77a~配線77c,且搭載有連接於該配線77a~配線77c的電子零件76a、電子零件76b。形成於柔型的基板80上的導電層81藉由導電性接著層90a而連接於基板70的配線72b,並且藉由導電性接著層90b而連接於基板75的配線77a。藉此,基板70、基板75藉由能夠彎曲的柔型的基板80而電性連接。
然而,圖11所示的電子裝置中,剛型的基板70、剛型的基板75需要用以與柔型的基板80連接的端子部,從而基板面
積大型化。另外,藉由組裝工時的增加而製造成本增加。
因而,日本專利特開平6-177490號公報(專利文獻1)中揭示有一種如下印刷配線板:藉由剛性配線板自柔性配線板的上下隔著接著層來夾持,藉此將柔性配線板與剛性配線板一體化。日本專利特開平6-177490號公報所記載的技術中,可藉由使用貫通孔等層間電路配線而將柔性配線板與剛性配線板連接。藉此,無需為了與柔型的基板的連接而設置端子部,從而可防止基板面積的大型化。
[現有技術文獻]
[專利文獻]
[專利文獻1]日本專利特開平6-177490號公報
然而,日本專利特開平6-177490號公報所記載的技術中,由於自柔性配線板的上下藉由剛性配線板來夾持,因此產生印刷配線基板變厚的問題。進而,由於藉由焊料等將電子零件搭載於印刷配線基板之上,因此進而增加了與電子零件相應的厚度。
另外,為了剛性配線板與柔性基板的多層化而需要積層衝壓等步驟或大型的裝置,因此存在製造成本變高的問題。
本發明是著眼於所述現有技術的問題點而成者,目的在於提供一種於具備能夠彎曲的彎曲部的同時能夠小型化及薄型化的電子裝置,並且提供一種抑制該電子裝置的製造成本的製造方
法。
根據某一方面,電子裝置具備:電子零件;將電子零件埋設並固定的樹脂成形體;及連接於樹脂成形體的能夠彎曲的彎曲部。
較佳為彎曲部藉由樹脂而與樹脂成形體一體地成形。或者,樹脂成形體亦可將彎曲部的一部分埋設並加以支撐。
較佳為樹脂成形體的表面包含使電子零件露出的露出面。彎曲部的表面包含與露出面連續的連續面。電子裝置進而具備:配線,形成於露出面與連續面之上,且連接於電子零件。
例如,配線自電子零件連續形成至連續面之上。或者,配線亦可包含:第一配線,形成於露出面之上,且連接於電子零件;及第二配線,預先形成於連續面之上,且連接於第一配線。
彎曲部的材料的斷裂時的伸長率大於樹脂成形體的材料的斷裂時的伸長率。例如,彎曲部亦可藉由斷裂時的伸長率為300%以上的樹脂形成。樹脂成形體亦可藉由斷裂時的伸長率為150%以下的樹脂形成。樹脂成形體亦可包含填料。
根據另一方面,電子裝置的製造方法具備:將電子零件貼附於片的步驟;將片配置於成形模具內,且使樹脂填充於成形模具內,藉此將埋設有電子零件的樹脂成形體與較樹脂成形體薄的能夠彎曲的彎曲部一體成形的步驟;及將配線形成於藉由將片自樹脂成形體剝離而露出的、樹脂成形體中的與片接觸的片接合
面和彎曲部中的與片接合面連續的連續面的步驟。
根據進而又一方面,電子裝置的製造方法具備:將電子零件貼附於片的步驟;將片依次配置於兩種成形模具內,藉由雙色成形法,將埋設有電子零件的樹脂成形體與連接於樹脂成形體的能夠彎曲的彎曲部一體地成形的步驟;及將配線形成於藉由將片自樹脂成形體剝離而露出的、樹脂成形體中的與片接觸的片接合面和彎曲部中的與片接合面連續的連續面的步驟。
根據進而又一方面,電子裝置的製造方法具備:將電子零件與能夠彎曲的彎曲部貼附於片的步驟;將片配置於成形模具內,且使樹脂填充於成形模具內,藉此將埋設有電子零件與彎曲部的一部分的樹脂成形體成形的步驟;及將第一配線形成於藉由將片自樹脂成形體剝離而露出的、樹脂成形體中的與片接觸的片接合面的步驟。
較佳為彎曲部的表面包含與片接合面連續的連續面。於形成第一配線的步驟中,將第一配線亦形成於連續面。
或者,亦可將第二配線預先形成於彎曲部的表面。然後,亦可於貼附的步驟中,以第二配線與片對向的方式將彎曲部貼附於片,且於形成第一配線的步驟中,以連接於第二配線的方式形成第一配線。
藉由本揭示,可實現於具備能夠彎曲的彎曲部的同時能夠小型化及薄型化的電子裝置。
10、40、50‧‧‧主體部
11、41、51‧‧‧樹脂成形體
11a、41a、51a‧‧‧上表面
12(12a~12e)、42(42a~42c)、71、76a、76b‧‧‧電子零件
13a~13e、43a~43c‧‧‧電極
20、60‧‧‧彎曲部
20a、60a‧‧‧連續面
30(30a~30p)、61(61a~61c)、72a、72b、77a~77c‧‧‧配線
70、75、80‧‧‧基板
81‧‧‧導電層
90a、90b‧‧‧導電性接著層
100、100A、100B、100C‧‧‧電子裝置
200‧‧‧暫時固定片
210‧‧‧第一模具
211‧‧‧凹部
220‧‧‧第二模具
221、222‧‧‧空間
230、240‧‧‧結構體
t1、t2‧‧‧厚度、深度
圖1是表示實施形態1的電子裝置的概略構成的平面圖。
圖2是沿圖1的X-X線的箭視剖面圖。
圖3(a)~圖3(d)是對實施形態1的電子裝置的製造方法進行說明的圖。
圖4是表示實施形態2的電子裝置的概略構成的平面圖。
圖5是沿圖4的X-X線的箭視剖面圖。
圖6是表示實施形態4的電子裝置的概略構成的平面圖。
圖7是沿圖6的X-X線的箭視剖面圖。
圖8(a)~圖8(d)是對實施形態4的電子裝置的製造方法進行說明的圖。
圖9是表示實施形態5的電子裝置的概略構成的平面圖。
圖10是沿圖9的XI-XI線的箭視剖面圖。
圖11是表示將剛型的基板與柔型的基板組合而成的電子裝置的示例的圖。
一面參照圖式一面對本發明的實施形態進行詳細說明。再者,對圖中的同一部分或相當部分標注同一符號且不重覆進行其說明。
<實施形態1>
(電子裝置的構成)
參照圖1及圖2對實施形態1的電子裝置100的概略構成進行說明。圖1是表示實施形態1的電子裝置100的概略構成的平面圖。圖2是沿圖1的X-X線的箭視剖面圖。
電子裝置100被組裝於可穿戴式行動設備等行動用電子設備或小型感測器等各種電子設備中,並承擔電子設備的主要的或輔助的功能。作為可穿戴式行動設備,例如有安裝於服裝上來測量身體的表面溫度的測量設備、或者繞於臂上來測量脈搏或血壓等的測量設備等。
如圖1及圖2所示,電子裝置100具備:形成有電子電路的主體部10;能夠彎曲的彎曲部20;及配線30(30a~30h)。主體部10包含:樹脂成形體11;及電子零件12(12a~12e)。
樹脂成形體11為大致板狀,且包括聚碳酸酯(polycarbonate,PC)或丙烯腈丁二烯苯乙烯(acrylonitrile-butadiene-styrene,ABS)等樹脂。再者,樹脂成形體11的形狀並無特別限定,只要配合電子裝置100的形狀適宜設計即可。樹脂成形體11的材質亦可為其他種類的樹脂(例如聚丙烯(polypropylene,PP)或彈性體等)。
樹脂成形體11藉由將電子零件12(12a~12e)埋設於其內部而將電子零件12固定。樹脂成形體11以電子零件12自上表面11a露出的方式埋設有電子零件12。
電子零件12(12a~12e)為晶片型電容器、晶片型電阻、積體電路(Integrated Circuit,IC)等電子零件。電子零件12的數
量及種類並無特別限定。
於電子零件12a~電子零件12e中的自樹脂成形體11露出的表面分別形成有電極13a~電極13e。
彎曲部20連接於樹脂成形體11,且能夠彎曲。具體而言,彎曲部20包括與樹脂成形體11相同的材質,且與樹脂成形體11一體成形。彎曲部20以彎曲性高於樹脂成形體11的方式具有較樹脂成形體11的厚度t2(例如3mm)薄的厚度t1(例如0.2mm)。
彎曲部20的表面包含與樹脂成形體11的上表面11a連續的連續面20a。此處,所謂兩個面「連續」,是指該兩個面之間的階差小至形成於所述兩個面之上的配線不切斷的程度。具體而言,彎曲部20的連續面20a與樹脂成形體11的上表面11a處於同一平面上。
配線30(30a~30h)形成於樹脂成形體11的上表面11a及彎曲部20的連續面20a的至少上表面11a之上,且連接於電子零件12a~電子零件12e的電極13a~電極13e中的任一者。
具體而言,配線30a~配線30c形成於樹脂成形體11的上表面11a及彎曲部20的連續面20a此兩者之上,且分別自電子零件12e的電極13e、電子零件12d的電極13d、電子零件12b的電極13b連續形成至連續面20a之上。
配線30d~配線30h形成於樹脂成形體11的上表面11a之上。配線30d連接於電子零件12a的電極13a及電子零件12b
的電極13b。配線30e連接於電子零件12a的電極13a及電子零件12c的電極13c。配線30f連接於電子零件12c的電極13c及電子零件12d的電極13d。配線30g連接於電子零件12a的電極13a及電子零件12d的電極13d。配線30h連接於電子零件12d的電極13d及電子零件12e的電極13e。
配線30例如可藉由使用噴墨印刷法噴射銀(Ag)墨而容易地形成。噴墨印刷法為自噴嘴噴射墨以使粒子狀的墨堆積於噴射對象面上的印刷方式。
如上所述,由於樹脂成形體11的上表面11a與彎曲部20的連續面20a連續,因此配線30可藉由使用噴墨印刷法噴射銀(Ag)墨而容易地形成。
(電子裝置的製造方法)
其次,參照圖3(a)~圖3(d)對實施形態1的電子裝置100的製造方法的一例進行說明。圖3(a)~圖3(d)是說明電子裝置100的製造方法的圖。圖3(a)~圖3(d)分別表示用於說明用以製造電子裝置100的第一步驟~第四步驟的圖。圖3(a)中,左側表示平面圖,右側表示側面圖。圖3(b)表示剖面圖。圖3(c)、圖3(d)中,左側表示平面圖,右側表示沿平面圖的X-X線的箭視剖面圖。
(第一步驟)
如圖3(a)所示,首先,藉由接著劑(未圖示)將電子零件12a~電子零件12e貼附並暫時固定於長方形狀的暫時固定片
200。此時,電子零件12a~電子零件12e是以形成有電極13a~電極13e的面接觸暫時固定片200的方式來貼附。
作為暫時固定片200的材料,例如可使用聚對苯二甲酸乙二酯(polyethylene terephthalate,PET)、聚萘二甲酸乙二酯(polyethylene naphthalate,PEN)、聚苯硫醚(polyphenylene sulfide,PPS)等。由於後述理由,暫時固定片200較佳為包含透過紫外線且具有柔軟性的材料。
暫時固定例如可使用塗佈於暫時固定片200的單個面的例如紫外線硬化型的接著劑(未圖示)來進行。例如將紫外線硬化型的接著劑以2μm~3μm的厚度塗佈於厚度50μm的PET製的暫時固定片200。該塗佈使用噴墨印刷法等方法進行即可。之後,將電子零件12a~電子零件12e分別設置於所設定的位置。然後,自暫時固定片200的未暫時固定有電子零件12a~電子零件12e的面照射例如3000mJ/cm2的強度的紫外線,藉此將接著劑硬化,從而將電子零件12a~電子零件12e暫時固定於暫時固定片200。
(第二步驟)
其次,如圖3(b)所示,將暫時固定有電子零件12a~電子零件12e的暫時固定片200設置於藉由將第一模具210與第二模具220組合而構成的成形模具的內部。
於第一模具210中的與第二模具220對向的面上形成有與暫時固定片200形狀相同的凹部211,且將暫時固定片200嵌入
該凹部211。藉此,暫時固定片200中的貼附有電子零件12a~電子零件12e的面與第二模具220對向。
另外,凹部211的深度與暫時固定片200的厚度相同。因此,暫時固定片200中的暫時固定有電子零件12的面和第一模具210的未形成有凹部211的部分中的與第二模具220對向的面存在於同一平面上。
第二模具220中的與第一模具210對向的面具有如下形狀:於與第一模具210的凹部211對向的部分形成深度t2的空間221,並且於不與第一模具210的凹部211對向的部分形成深度t1的空間222。空間221與空間222連通。
然後,將樹脂材射出至藉由將第一模具210與第二模具220組合而構成的成形模具的內部的空間221、空間222,從而進行樹脂的射出成形。
進行射出成形的條件根據樹脂而適宜選擇即可,例如於使用聚碳酸酯(PC)的情況下,以射出樹脂溫度270℃、射出壓力100MPa進行射出成形。
進行射出成形的樹脂可採用各種樹脂材料。但是,若使用彈性體等具有橡膠彈性的材料,則彎曲部20能夠更柔軟地變形。另外,進行射出成形的條件並無特別限定。
(第三步驟)
如圖3(c)所示,將藉由第二步驟的射出成形而獲得的結構體230自成形模具取出。結構體230具備:樹脂成形體11,具有
與成形模具的空間221相同的形狀(厚度t2);及彎曲部20,具有與成形模具的空間222相同的形狀(厚度t1)。
然後,將暫時固定片200自結構體230剝離。藉此,電子零件12a~電子零件12e的表面自樹脂成形體11中的與暫時固定片200接觸的片接合面(對應於上表面11a)露出。
於暫時固定片200為PET膜的情況下,藉由第二步驟時的熱變化而暫時固定片200大幅變形,因此可容易地將暫時固定片200自結構體230分離。
再者,第二步驟中,當將暫時固定片200嵌入第一模具210的凹部211時,暫時固定片200中的暫時固定有電子零件12的面和第一模具210中的與第二模具220對向的面存在於同一平面上。因此,彎曲部20中與第一模具210接觸的部分的表面與樹脂成形體11的上表面11a連續,並且成為與上表面11a處於同一平面上的連續面20a。
(第四步驟)
如圖3(d)所示,第三步驟之後,於樹脂成形體11的上表面11a和彎曲部20的連續面20a之上形成規定圖案的配線30(30a~30h)。
配線30的形成可使用藉由噴墨印刷法等來噴霧導電材料(例如銀墨等)的方法、利用氣溶膠的方法、或者利用分配器的方法等來進行。
配線30可使用適宜選擇的方法而容易地且電路設計的
自由度高地形成,各電子零件12a~電子零件12e無需焊接等即可簡便地進行電性連接。進一步而言,於工業上,可於各電子零件12a~電子零件12e的位置確定之後對各電子零件12a~電子零件12e進行接線,因此例如相較於使電子零件對準印刷基板的情況,可準確且容易地將各電子零件12a~電子零件12e電性連接。
藉此,具備包含電子零件12與樹脂成形體11的主體部10、彎曲部20及配線30的電子裝置100的製作結束。
(優點)
如以上般,電子裝置100具備:電子零件12;將電子零件12埋設並固定的樹脂成形體11;及連接於樹脂成形體11的能夠彎曲的彎曲部20。
樹脂成形體11藉由將電子零件12埋設並固定來作為搭載有電子零件的基板發揮功能。藉此,與藉由焊料等將電子零件搭載於先前的鋼型的基板的上表面的情況相比,可使電子裝置100小型化及薄型化。
進而,由於彎曲部20連接於樹脂成形體11,因此與藉由剛性配線板自上下來夾持柔性配線板的情況(參照日本專利特開平6-177490號公報)相比,可使電子裝置100小型化及薄型化。
彎曲部20與樹脂成形體11一體地成形。藉此,於彎曲部20與樹脂成形體11之間不存在施加機械性負荷的連接點,因此樹脂成形體11與彎曲部20的連接可靠性變高。另外,無需將比較昂貴的柔性基板用作其他構件,因此可減少零件成本。
樹脂成形體11的表面包含使電子零件12露出的上表面(露出面)11a。彎曲部20的表面包含與上表面11a連續的連續面20a。電子裝置100具備:配線30,形成於上表面11a與連續面20a之上,且連接於電子零件12。藉此,不需要用於將彎曲部與樹脂成形體11電性連接的端子部,從而可進一步小型化。
電子裝置100可藉由以下的(1)~(3)的步驟來製造。
(1)將電子零件12貼附於暫時固定片200的步驟。
(2)將暫時固定片200配置於成形模具(第一模具210及第二模具220)內,且使樹脂填充於成形模具內,藉此將埋設有電子零件12的樹脂成形體11與較樹脂成形體11薄的能夠彎曲的彎曲部20一體成形的步驟。
(3)將配線30形成於藉由將暫時固定片200自樹脂成形體11剝離而露出的、樹脂成形體11中的與暫時固定片200接觸的上表面(片接合面)11a和彎曲部20中的與上表面11a連續的連續面20a的步驟。
藉由所述製造方法,主體部10與彎曲部20的電性連接可藉由將配線30形成於樹脂成形體11的上表面11a與彎曲部20的連續面20a之上來達成。如此,不需要用以將先前般的柔型的基板連接於剛型的基板的複雜步驟,並且亦不需要接著劑等構件。因此,可減少電子裝置100的製造成本。
<實施形態2>
本發明的實施形態2的電子裝置為實施形態1的電子裝置
100的變形例,且具備多個包含電子零件與樹脂成形體的主體部。
圖4是表示實施形態2的電子裝置100A的概略構成的平面圖。圖5是沿圖4的X-X線的箭視剖面圖。
如圖4及圖5所示,電子裝置100A於具備主體部40與配線30i~配線30k的方面與實施形態1的電子裝置100不同。
主體部40連接於彎曲部20中的與連接於主體部10的端部為相反側的端部。主體部40包含:樹脂成形體41;及電子零件42(42a~42c)。
樹脂成形體41為大致板狀,且可藉由與樹脂成形體11及彎曲部20相同的樹脂而與樹脂成形體11及彎曲部20一體成形。
樹脂成形體41藉由將電子零件42(42a~42c)埋設於其內部而將電子零件42固定。樹脂成形體41以電子零件42自上表面41a露出的方式埋設有電子零件42。
樹脂成形體41的上表面41a與彎曲部20的連續面20a連續,且與樹脂成形體11的上表面11a及連續面20a處於同一平面上。
電子零件42(42a~42c)為晶片型電容器、晶片型電阻、IC(積體電路(Integrated Circuit))等電子零件。電子零件42的數量及種類並無特別限定。
於電子零件42a~電子零件42c中的自樹脂成形體41露出的表面分別形成有電極43a~電極43c。
配線30i~配線30k形成於樹脂成形體41的上表面
41a,且連接於電子零件42a~電子零件42c的電極43a~電極43c。
另外,本實施形態2中,形成於彎曲部20的連續面20a上的配線30a~配線30c延長至樹脂成形體41的上表面41a。配線30a連接於電子零件42b的電極43b。配線30b、配線30c連接於電子零件42c的電極43c。
電子裝置100A可藉由與實施形態1同樣的方法製造。具體而言,實施形態1所說明的第一步驟中,準備與暫時固定有電子零件12的暫時固定片200不同的暫時固定有電子零件42的暫時固定片。第二步驟中,將暫時固定有電子零件12的暫時固定片200與暫時固定有電子零件42的暫時固定片設置於成形模具的內部,且將樹脂材射出至成形模具的內部,從而進行樹脂的射出成形。藉此,將樹脂成形體11、樹脂成形體41及彎曲部20一體成形。之後,第四步驟中,將配線30(30a~30k)形成於樹脂成形體11的上表面11a及樹脂成形體41的上表面41a、以及與上表面11a、上表面41a連續的彎曲部20的連續面20a之上即可。
藉由所述構成,將能夠彎曲的彎曲部20配置於多個主體部10、主體部40之間。因此,即使為主體部10與主體部40的設置部位並非同一平面上的情況,亦可一面確保藉由彎曲部20來將主體部10的電子電路與主體部40的電子電路電性連接的狀態,一面將電子裝置100A組裝於電子設備中。
<實施形態3>
本發明的實施形態3的電子裝置為實施形態1的電子裝置
100或實施形態2的電子裝置100A的變形例,且彎曲部20與主體部10的樹脂成形體11及主體部40的樹脂成形體41的材質不同。
例如,主體部10的樹脂成形體11及主體部40的樹脂成形體41中較佳為使用聚碳酸酯(PC)或丙烯腈丁二烯苯乙烯(ABS)等斷裂時的伸長率為150%以下的樹脂材。再者,所謂斷裂時的伸長率,表示當依據日本工業標準(Japanese Industrial Standards,JIS)K 7162進行拉伸試驗時,斷裂時的試驗片相對於試驗前的試驗片的伸長率。
藉此,主體部10、主體部40變得不易變形,因此容易將主體部10、主體部40固定於固定位置。
相對於此,彎曲部20中較佳為使用斷裂時的伸長率為580%的聚胺甲酸酯(polyurethane,PU)或者斷裂時的伸長率為300%的聚醯胺(polyamide,PA)等斷裂時的伸長率為300%以上的樹脂材。
藉此,依據欲組裝電子裝置100、電子裝置100A的電子設備的其他構成或者主體部10、主體部40的設置位置,視需要可於將彎曲部20拉伸的狀態下將電子裝置100、電子裝置100A組裝於電子設備中。其結果,即使存在電子設備的內部構成的個體偏差或者內部構成的多少的設計變更,亦容易將電子裝置100、電子裝置100A組裝於電子設備中。
當為被組裝至搭載於服裝(例如內衣)上來測量身體的
表面溫度的測量設備中的電子裝置100A的情況下,彎曲部20設置於靠近人體的關節的位置。藉此,使用斷裂時的伸長率為300%以上的樹脂材而形成的彎曲部20可配合穿著服裝的人的動作來伸縮。
包含溫度感測器作為電子零件12的主體部10設置於遠離人體的關節的比較穩定的位置。主體部10的樹脂成形體11較佳為當接觸人體的表面時,為了減少對該人體的刺激而具有某種程度的彈力性。形成樹脂成形體11的樹脂材根據主體部10的設置部位而自斷裂時的伸長率為150%以下的樹脂材中適宜選擇。
另外,即使為使彎曲部20與主體部10的樹脂成形體11及主體部40的樹脂成形體41的樹脂材相同的情況,亦較佳為使填料(例如玻璃填料、碳填料)複合於構成樹脂成形體11及樹脂成形體41的樹脂材中。藉此,可提高主體部10、主體部40的強度。尤其,為了有效率地提高強度,較佳為使玻璃填料複合。
作為使彎曲部20與主體部10的樹脂成形體11及主體部40的樹脂成形體41的材質不同的方法,使用先前公知的雙色成形法等即可。
雙色成形法為將不同的樹脂彼此或者不同的原材料彼此組合而一體地進行成形的方法。具體而言,於使用第一成形模具將樹脂成形體11成形後,使用第二成形模具將彎曲部20成形,藉此將樹脂成形體11與彎曲部20一體地成形。或者,亦可於使用第一成形模具將彎曲部20成形後,使用第二成形模具將樹脂成
形體11成形,藉此將樹脂成形體11與彎曲部20一體地成形。
於使用斷裂時的伸長率高的材質作為彎曲部20的情況下,彎曲部20亦可具有與樹脂成形體11相同的厚度。
<實施形態4>
所述實施形態1~實施形態3中藉由樹脂材的射出成形將彎曲部20成形,而實施形態4的電子裝置將柔性基板用作彎曲部。
(電子裝置的構成)
參照圖6及圖7對實施形態4的電子裝置100B的構成進行說明。圖6是表示實施形態4的電子裝置100B的概略構成的平面圖。圖7是沿圖6的X-X線的箭視剖面圖。
如圖6及圖7所示,電子裝置100B於具備主體部50來代替主體部10且具備彎曲部60來代替彎曲部20的方面與實施形態1的電子裝置100不同。
彎曲部60為包含聚醯亞胺(polyimide,PI)或聚對苯二甲酸乙二酯(PET)等的膜上的柔性基板。彎曲部60的形狀並無特別限定,例如為矩形狀。彎曲部60的厚度並無特別限定,例如為50μm。
主體部50於具備樹脂成形體51來代替樹脂成形體11的方面與實施形態1的主體部10不同。
樹脂成形體51為大致板狀,且包括聚碳酸酯(PC)或丙烯腈丁二烯苯乙烯(ABS)等樹脂。再者,樹脂成形體51的形狀並無特別限定,只要配合電子裝置100B的形狀適宜設計即可。
樹脂成形體51的材質亦可為其他種類的樹脂(例如聚丙烯(PP)或彈性體等)。
與樹脂成形體11同樣地,樹脂成形體51藉由將電子零件12(12a~12e)埋設於其內部而將電子零件12固定。樹脂成形體51以電子零件12自上表面51a露出的方式埋設電子零件12。
進而,樹脂成形體51藉由埋設彎曲部60的一部分來支撐彎曲部60。藉此,彎曲部60連接於樹脂成形體51。圖6及圖7所示的例子中,樹脂成形體51將矩形狀的彎曲部60的包含其中一條短邊的端部埋設並加以支撐。樹脂成形體51以使其上表面51a與彎曲部60的表面的一部分(連續面60a)連續的方式來支撐彎曲部60。具體而言,樹脂成形體51以上表面51a與彎曲部60的連續面60a處於同一平面上的方式來支撐彎曲部60。
與實施形態1同樣地,配線30(30a~30h)形成於樹脂成形體51的上表面51a及彎曲部60的連續面60a的至少一者之上,且連接於電子零件12a~電子零件12e中的任一者。
(電子裝置的製造方法)
其次,參照圖8(a)~圖8(d)對實施形態4的電子裝置100B的製造方法一例進行說明。圖8(a)~圖8(d)是對電子裝置100B的製造方法進行說明的圖。圖8(a)~圖8(d)分別表示用於說明用以製造電子裝置100B的第一步驟~第四步驟的圖。圖8(a)中,左側表示平面圖,右側表示側面圖。圖8(b)表示剖面圖。圖8(c)、圖8(d)中,左側表示平面圖,右側表
示沿平面圖的X-X線的箭視剖面圖。
(第一步驟)
如圖8(a)所示,首先,藉由接著劑將電子零件12a~電子零件12e與彎曲部60貼附並暫時固定於暫時固定片200。此時,電子零件12a~電子零件12e是以形成有電極13a~電極13e的面接觸暫時固定片200的方式來貼附。彎曲部60僅將其一部分貼附於暫時固定片200。電子零件12a~電子零件12e與彎曲部60暫時固定於暫時固定片200的方法與實施形態1的第一步驟相同,因此省略詳細說明。
(第二步驟)
其次,如圖8(b)所示,將暫時固定有電子零件12a~電子零件12e及彎曲部60的暫時固定片200設置於藉由將第一模具210與第二模具220組合而構成的成形模具的內部。
與實施形態1同樣地,將暫時固定片200嵌入形成於第一模具210中的凹部211。此時,彎曲部60被收容於空間222的大致整個區域,並且其一部分突出至空間221中。
然後,將樹脂材射出至藉由將第一模具210與第二模具220組合而構成的成形模具的內部的空間221,從而進行樹脂的射出成形。進行射出成形的條件與實施形態1的第二步驟相同。
(第三步驟)
如圖8(c)所示,將藉由第二步驟的射出成形而獲得的結構體240自成形模具取出。結構體240具備:樹脂成形體51,埋設
有電子零件12a~電子零件12e,並且具有與成形模具的空間221相同的形狀;及彎曲部60,其一部分埋設於樹脂成形體51中。
然後,將暫時固定片200自結構體240剝離。藉此,電子零件12a~電子零件12e的表面自樹脂成形體51的上表面51a露出。另外,彎曲部60中貼附於暫時固定片200的連續面60a與樹脂成形體51的上表面51a成為同一平面上,且與上表面51a連續。
(第四步驟)
如圖8(d)所示,第三步驟之後,於樹脂成形體51的上表面51a和彎曲部60的連續面60a之上形成規定圖案的配線30(30a~30h)。配線30的形成方法與實施形態1的第四步驟相同。
藉此,具備包含電子零件12與樹脂成形體51的主體部50、藉由樹脂成形體51來支撐的彎曲部60、及配線30的電子裝置100B的製作結束。
(優點)
實施形態3的電子裝置100B中,樹脂成形體51將彎曲部60的一部分埋設並加以支撐。藉此,與藉由接著劑等進行接著的情況相比,彎曲部60與樹脂成形體51的連接的可靠性變高。
電子裝置100B可藉由以下的(1)~(3)的步驟來製造。
(1)將電子零件12與能夠彎曲的彎曲部60貼附於暫時固定片200的步驟。
(2)將暫時固定片200配置於成形模具(將第一模具210與第二模具220組合而成的模具)內,且使樹脂填充於成形模具內,藉此將埋設有電子零件12與彎曲部60的一部分的樹脂成形體51成形的步驟。
(3)將配線(第一配線)30形成於藉由將暫時固定片200自樹脂成形體51剝離而露出的、樹脂成形體51中的與暫時固定片200接觸的上表面(片接合面)51a的步驟。
藉此,可容易地製造具備彎曲部60的電子裝置100B。因此,可減少電子裝置100B的製造成本。
配線30亦形成於彎曲部60中的與樹脂成形體51的上表面51a連續的連續面60a。藉此,主體部50與彎曲部60的電性連接可藉由將配線30形成於樹脂成形體51的上表面51a與彎曲部60的連續面60a之上來達成。如此,不需要用以將先前般的柔型的基板連接於剛型的基板的複雜步驟,並且亦不需要接著劑等構件。因此,可減少電子裝置100B的製造成本。
<實施形態5>
本發明的實施形態5的電子裝置為實施形態4的電子裝置100B的變形例,且於作為柔性基板的彎曲部60預先形成有配線。
圖9是表示實施形態5的電子裝置100C的概略構成的平面圖。圖10是沿圖9的XI-XI線的箭視剖面圖。
如圖9及圖10所示,電子裝置100C具備:主體部50;彎曲部60;及配線(第一配線)30(30d~30h,30m,30n,30p)。
彎曲部60中,於與樹脂成形體51的上表面51a連續的連續面60a上預先形成有配線(第二配線)61(61a~61c)。
配線61例如可藉由具有12μm左右的厚度的銅而形成。或者,配線61亦可藉由鋁等來代替銅而形成。
配線30m是以將形成於彎曲部60的配線61a與電子零件12b連接的方式形成。配線30n是以將形成於彎曲部60的配線61b與電子零件12d連接的方式形成。配線30p是以將形成於彎曲部60的配線61c與電子零件12e連接的方式形成。
藉此,可將已形成有配線的柔性基板用作彎曲部60。
電子裝置100C可藉由與所述實施形態4的電子裝置100B同樣的製造方法(參照圖8)來製造。但是,圖8(a)~圖8(d)所示的第一步驟中,彎曲部60是以配線61與暫時固定片200對向的方式(接觸的方式)貼附於暫時固定片200。藉此,於樹脂的射出成形後,配線61與樹脂成形體51中的與暫時固定片200接觸的上表面(片接合面)51a成為同一平面上。其結果,當形成配線30時,可容易地使配線30的一部分連接於配線61。如此,可容易地使作為柔性基板的彎曲部60的配線61與形成於樹脂成形體51上的配線30連接。即,不需要用以將先前般的柔型的基板連接於剛型的基板的複雜步驟,並且亦不需要接著劑等構件。因此,可減少電子裝置100C的製造成本。
應考慮到此次所揭示的實施形態於所有方面為例示,而並非限制者。本發明的範圍並非由所述說明而是由申請專利範圍
表示,意在包含與申請專利範圍均等的含義及範圍內的所有變更。
Claims (13)
- 一種電子裝置,其具備:電子零件;將所述電子零件埋設並固定的樹脂成形體;及連接於所述樹脂成形體的能夠彎曲的彎曲部,其中,所述樹脂成形體的表面包含使所述電子零件露出的露出面,所述彎曲部的表面包含與所述露出面連續的連續面,所述電子裝置進而具備:配線,形成於所述露出面與所述連續面之上,且連接於所述電子零件。
- 如申請專利範圍第1項所述的電子裝置,其中,所述彎曲部藉由樹脂而與所述樹脂成形體一體地成形。
- 如申請專利範圍第1項所述的電子裝置,其中,所述樹脂成形體將所述彎曲部的一部分埋設並加以支撐。
- 如申請專利範圍第1項所述的電子裝置,其中,所述配線自所述電子零件連續形成至所述連續面之上。
- 如申請專利範圍第1項所述的電子裝置,其中,所述配線包含:第一配線,形成於所述露出面之上,且連接於所述電子零件;及第二配線,預先形成於所述連續面之上,且連接於所述第一配線。
- 如申請專利範圍第1項所述的電子裝置,其中,所述彎曲部的材料的斷裂時的伸長率大於所述樹脂成形體的材料的斷裂時的伸長率。
- 如申請專利範圍第6項所述的電子裝置,其中,所述彎曲部藉由斷裂時的伸長率為300%以上的樹脂形成。
- 如申請專利範圍第7項所述的電子裝置,其中,所述樹脂成形體藉由斷裂時的伸長率為150%以下的樹脂形成。
- 如申請專利範圍第1項所述的電子裝置,其中,所述樹脂成形體包含填料。
- 一種電子裝置的製造方法,其具備:將電子零件貼附於片的步驟;將所述片配置於成形模具內,且使樹脂填充於所述成形模具內,藉此將埋設有所述電子零件的樹脂成形體與較所述樹脂成形體薄的能夠彎曲的彎曲部一體地成形的步驟;及將連接於所述電子零件的配線形成於藉由將所述片自所述樹脂成形體剝離而露出的、所述樹脂成形體中的與所述片接觸的片接合面和所述彎曲部中的與所述片接合面連續的連續面的步驟。
- 一種電子裝置的製造方法,其具備:將電子零件貼附於片的步驟;將所述片依次配置於兩種成形模具內,藉由雙色成形法,將埋設有所述電子零件的樹脂成形體與連接於所述樹脂成形體的能夠彎曲的彎曲部一體地成形的步驟;及將連接於所述電子零件的配線形成於藉由將所述片自所述樹脂成形體剝離而露出的、所述樹脂成形體中的與所述片接觸的片接合面和所述彎曲部中的與所述片接合面連續的連續面的步驟。
- 一種電子裝置的製造方法,其具備:將電子零件與能夠彎曲的彎曲部貼附於片的步驟;將所述片配置於成形模具內,且使樹脂填充於所述成形模具內,藉此將埋設有所述電子零件與所述彎曲部的一部分的樹脂成形體成形的步驟;及將連接於所述電子零件的第一配線形成於藉由將所述片自所述樹脂成形體剝離而露出的、所述樹脂成形體中的與所述片接觸的片接合面的步驟,其中,所述彎曲部的表面包含與所述片接合面連續的連續面,且於形成所述第一配線的步驟中,將所述第一配線亦形成於所述連續面之上。
- 如申請專利範圍第12項所述的電子裝置的製造方法,其中,將第二配線預先形成於所述彎曲部的表面,於所述貼附的步驟中,以所述第二配線與所述片對向的方式將所述彎曲部貼附於所述片,且於形成所述第一配線的步驟中,以連接於所述第二配線的方式形成所述第一配線。
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1802883A (zh) * | 2003-07-03 | 2006-07-12 | 株式会社日立制作所 | 组件装置及其制造方法 |
TW200806131A (en) * | 2005-12-23 | 2008-01-16 | Teikoku Tsushin Kogyo Kk | Structure and method of fixing electronic parts to circuit board |
TW201004516A (en) * | 2008-07-14 | 2010-01-16 | Unimicron Technology Corp | Circuit board structure |
TW201606954A (zh) * | 2014-04-22 | 2016-02-16 | 歐姆龍股份有限公司 | 埋設電子零件的樹脂構造體及其製造方法 |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04346490A (ja) * | 1991-05-24 | 1992-12-02 | Matsushita Electric Ind Co Ltd | プリント配線板の製造方法 |
JPH06177490A (ja) | 1992-12-03 | 1994-06-24 | Matsushita Electric Works Ltd | プリント配線板 |
JP4103653B2 (ja) * | 2003-03-27 | 2008-06-18 | 株式会社デンソー | Icカード |
JP4602208B2 (ja) * | 2004-12-15 | 2010-12-22 | 新光電気工業株式会社 | 電子部品実装構造体及びその製造方法 |
US7759167B2 (en) * | 2005-11-23 | 2010-07-20 | Imec | Method for embedding dies |
DE102006055576A1 (de) * | 2006-11-21 | 2008-05-29 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Verfahren zum Herstellen eines dehnbaren Schaltungsträgers und dehnbarer Schaltungsträger |
JP5089184B2 (ja) * | 2007-01-30 | 2012-12-05 | ローム株式会社 | 樹脂封止型半導体装置およびその製造方法 |
JP2009071234A (ja) * | 2007-09-18 | 2009-04-02 | Denso Corp | 半導体装置 |
JP2009147010A (ja) * | 2007-12-12 | 2009-07-02 | Ricoh Co Ltd | 配線構造体 |
JP5374975B2 (ja) * | 2008-09-03 | 2013-12-25 | 住友電気工業株式会社 | シール構造および電子機器 |
US8482137B2 (en) * | 2009-01-27 | 2013-07-09 | Panasonic Corporation | Method of mounting semiconductor chips, semiconductor device obtained using the method, method of connecting semiconductor chips, three-dimensional structure in which wiring is provided on its surface, and method of producing the same |
JP5251845B2 (ja) * | 2009-11-26 | 2013-07-31 | 株式会社安川電機 | 半導体装置の製造方法 |
US8929085B2 (en) * | 2011-09-30 | 2015-01-06 | Apple Inc. | Flexible electronic devices |
JP5386567B2 (ja) * | 2011-11-15 | 2014-01-15 | 株式会社フジクラ | 撮像素子チップの実装方法、内視鏡の組立方法、撮像モジュール及び内視鏡 |
JP6237624B2 (ja) * | 2012-06-29 | 2017-11-29 | ソニー株式会社 | カメラモジュールおよび電子機器 |
WO2014185194A1 (ja) * | 2013-05-13 | 2014-11-20 | 株式会社村田製作所 | フレキシブル回路基板、および、フレキシブル回路基板の製造方法 |
US20150359099A1 (en) * | 2014-06-04 | 2015-12-10 | Apple Inc. | Low area over-head connectivity solutions to sip module |
JP6385234B2 (ja) * | 2014-10-16 | 2018-09-05 | 三菱電機株式会社 | 半導体装置 |
WO2016074176A1 (en) * | 2014-11-12 | 2016-05-19 | Intel Corporation | Flexible system-in-package solutions for wearable devices |
JP2016111037A (ja) * | 2014-12-02 | 2016-06-20 | 東レ株式会社 | 太陽電池裏面保護用シート、およびそれを用いた太陽電池 |
-
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- 2016-11-21 JP JP2016226044A patent/JP6776840B2/ja not_active Expired - Fee Related
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2017
- 2017-09-19 WO PCT/JP2017/033675 patent/WO2018092407A1/ja active Application Filing
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Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1802883A (zh) * | 2003-07-03 | 2006-07-12 | 株式会社日立制作所 | 组件装置及其制造方法 |
TW200806131A (en) * | 2005-12-23 | 2008-01-16 | Teikoku Tsushin Kogyo Kk | Structure and method of fixing electronic parts to circuit board |
TW201004516A (en) * | 2008-07-14 | 2010-01-16 | Unimicron Technology Corp | Circuit board structure |
TW201606954A (zh) * | 2014-04-22 | 2016-02-16 | 歐姆龍股份有限公司 | 埋設電子零件的樹脂構造體及其製造方法 |
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