TWI382456B - 鬆弛矽化鍺層的磊晶成長 - Google Patents

鬆弛矽化鍺層的磊晶成長 Download PDF

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Publication number
TWI382456B
TWI382456B TW093122682A TW93122682A TWI382456B TW I382456 B TWI382456 B TW I382456B TW 093122682 A TW093122682 A TW 093122682A TW 93122682 A TW93122682 A TW 93122682A TW I382456 B TWI382456 B TW I382456B
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TW
Taiwan
Prior art keywords
layer
germanium
containing layer
fabricating
semiconductor structure
Prior art date
Application number
TW093122682A
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English (en)
Chinese (zh)
Other versions
TW200509226A (en
Inventor
謙托Ｊ 爾瑞那
皮爾瑞 托馬西尼
奈爾 寇帝
麥特喜愛斯 波爾
Original Assignee
Asm美國股份有限公司
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Publication of TW200509226A publication Critical patent/TW200509226A/zh
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Publication of TWI382456B publication Critical patent/TWI382456B/zh

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    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02—Elements
    • C30B29/06—Silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/52—Alloys
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/24—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using chemical vapour deposition [CVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3202—Materials thereof
    • H10P14/3204—Materials thereof being Group IVA semiconducting materials
    • H10P14/3211—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3242—Structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3242—Structure
    • H10P14/3244—Layer structure
    • H10P14/3248—Layer structure consisting of two layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411—Silicon, silicon germanium or germanium

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Recrystallisation Techniques (AREA)
  • Chemical Vapour Deposition (AREA)
TW093122682A 2003-07-30 2004-07-29 鬆弛矽化鍺層的磊晶成長 TWI382456B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US49102903P 2003-07-30 2003-07-30

Publications (2)

Publication Number Publication Date
TW200509226A TW200509226A (en) 2005-03-01
TWI382456B true TWI382456B (zh) 2013-01-11

Family

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Family Applications (1)

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TW093122682A TWI382456B (zh) 2003-07-30 2004-07-29 鬆弛矽化鍺層的磊晶成長

Country Status (6)

Country Link
US (2) US7514372B2 (https=)
EP (1) EP1649495A2 (https=)
JP (1) JP2007511892A (https=)
KR (1) KR20060039915A (https=)
TW (1) TWI382456B (https=)
WO (1) WO2005013326A2 (https=)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070020833A1 (en) * 2003-06-26 2007-01-25 Rj Mears, Llc Method for Making a Semiconductor Device Including a Channel with a Non-Semiconductor Layer Monolayer
US7598515B2 (en) * 2003-06-26 2009-10-06 Mears Technologies, Inc. Semiconductor device including a strained superlattice and overlying stress layer and related methods
US7531828B2 (en) * 2003-06-26 2009-05-12 Mears Technologies, Inc. Semiconductor device including a strained superlattice between at least one pair of spaced apart stress regions
US7612366B2 (en) * 2003-06-26 2009-11-03 Mears Technologies, Inc. Semiconductor device including a strained superlattice layer above a stress layer
US20070010040A1 (en) * 2003-06-26 2007-01-11 Rj Mears, Llc Method for Making a Semiconductor Device Including a Strained Superlattice Layer Above a Stress Layer
US20070015344A1 (en) * 2003-06-26 2007-01-18 Rj Mears, Llc Method for Making a Semiconductor Device Including a Strained Superlattice Between at Least One Pair of Spaced Apart Stress Regions
US20070020860A1 (en) * 2003-06-26 2007-01-25 Rj Mears, Llc Method for Making Semiconductor Device Including a Strained Superlattice and Overlying Stress Layer and Related Methods
US7901968B2 (en) * 2006-03-23 2011-03-08 Asm America, Inc. Heteroepitaxial deposition over an oxidized surface
US7785995B2 (en) * 2006-05-09 2010-08-31 Asm America, Inc. Semiconductor buffer structures
CA2661047A1 (en) * 2006-05-15 2007-11-22 Arise Technologies Corporation Low-temperature doping processes for silicon wafer devices
US7608526B2 (en) * 2006-07-24 2009-10-27 Asm America, Inc. Strained layers within semiconductor buffer structures
WO2010024987A1 (en) * 2008-08-27 2010-03-04 S.O.I.Tec Silicon On Insulator Technologies Methods of fabricating semiconductor structures or devices using layers of semiconductor material having selected or controlled lattice parameters
US8039371B2 (en) * 2009-07-01 2011-10-18 International Business Machines Corporation Reduced defect semiconductor-on-insulator hetero-structures
KR101478977B1 (ko) 2009-11-18 2015-01-06 소이텍 글라스 접합층을 이용한 반도체 구조들 및 디바이스들의 제조 방법들 및 이와 같은 방법들에 의해 형성되는 반도체 구조들 및 디바이스들
FR2968830B1 (fr) 2010-12-08 2014-03-21 Soitec Silicon On Insulator Couches matricielles ameliorees pour le depot heteroepitaxial de materiaux semiconducteurs de nitrure iii en utilisant des procedes hvpe
US9023721B2 (en) 2010-11-23 2015-05-05 Soitec Methods of forming bulk III-nitride materials on metal-nitride growth template layers, and structures formed by such methods
FR2968678B1 (fr) 2010-12-08 2015-11-20 Soitec Silicon On Insulator Procédés pour former des matériaux a base de nitrure du groupe iii et structures formées par ces procédés
US9127345B2 (en) 2012-03-06 2015-09-08 Asm America, Inc. Methods for depositing an epitaxial silicon germanium layer having a germanium to silicon ratio greater than 1:1 using silylgermane and a diluent
US9171715B2 (en) 2012-09-05 2015-10-27 Asm Ip Holding B.V. Atomic layer deposition of GeO2
US9218963B2 (en) 2013-12-19 2015-12-22 Asm Ip Holding B.V. Cyclical deposition of germanium
US9536746B2 (en) * 2014-03-13 2017-01-03 Taiwan Semiconductor Manufacturing Co., Ltd. Recess and epitaxial layer to improve transistor performance
US9343303B2 (en) 2014-03-20 2016-05-17 Samsung Electronics Co., Ltd. Methods of forming low-defect strain-relaxed layers on lattice-mismatched substrates and related semiconductor structures and devices
EP3221885B1 (en) * 2014-11-18 2019-10-23 GlobalWafers Co., Ltd. High resistivity semiconductor-on-insulator wafer and a method of manufacturing
US10431695B2 (en) 2017-12-20 2019-10-01 Micron Technology, Inc. Transistors comprising at lease one of GaP, GaN, and GaAs
US10825816B2 (en) 2017-12-28 2020-11-03 Micron Technology, Inc. Recessed access devices and DRAM constructions
US10734527B2 (en) 2018-02-06 2020-08-04 Micron Technology, Inc. Transistors comprising a pair of source/drain regions having a channel there-between
CN116544101A (zh) * 2022-02-02 2023-08-04 Asm Ip私人控股有限公司 形成硅锗结构的方法
WO2024005276A1 (ko) * 2022-07-01 2024-01-04 주식회사 비아트론 에피택시 공정을 이용한 반도체 소자 제조 방법 및 이를 위한 제조 장치

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020079507A1 (en) * 2000-12-27 2002-06-27 Shim Kyu Hwan SiGe MODFET with a metal-oxide film and method for fabricating the same
US20020185686A1 (en) * 2001-06-12 2002-12-12 International Business Machines Corporation Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5256550A (en) * 1988-11-29 1993-10-26 Hewlett-Packard Company Fabricating a semiconductor device with strained Si1-x Gex layer
US5442205A (en) * 1991-04-24 1995-08-15 At&T Corp. Semiconductor heterostructure devices with strained semiconductor layers
US5221413A (en) * 1991-04-24 1993-06-22 At&T Bell Laboratories Method for making low defect density semiconductor heterostructure and devices made thereby
JP2877108B2 (ja) * 1996-12-04 1999-03-31 日本電気株式会社 半導体装置およびその製造方法
JP2953567B2 (ja) 1997-02-06 1999-09-27 日本電気株式会社 半導体装置の製造方法
US5891769A (en) * 1997-04-07 1999-04-06 Motorola, Inc. Method for forming a semiconductor device having a heteroepitaxial layer
EP1016129B2 (en) * 1997-06-24 2009-06-10 Massachusetts Institute Of Technology Controlling threading dislocation densities using graded layers and planarization
WO2000004357A1 (en) * 1998-07-15 2000-01-27 Smithsonian Astrophysical Observatory Epitaxial germanium temperature sensor
FR2783254B1 (fr) 1998-09-10 2000-11-10 France Telecom Procede d'obtention d'une couche de germanium monocristallin sur un substrat de silicium monocristallin,et produits obtenus
US6350993B1 (en) * 1999-03-12 2002-02-26 International Business Machines Corporation High speed composite p-channel Si/SiGe heterostructure for field effect devices
WO2002015244A2 (en) * 2000-08-16 2002-02-21 Massachusetts Institute Of Technology Process for producing semiconductor article using graded expitaxial growth
WO2003003431A1 (en) * 2000-09-05 2003-01-09 The Regents Of The University Of California Relaxed sige films by surfactant mediation
AU2002306436A1 (en) * 2001-02-12 2002-10-15 Asm America, Inc. Improved process for deposition of semiconductor films
US6855649B2 (en) * 2001-06-12 2005-02-15 International Business Machines Corporation Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing
US6844213B2 (en) * 2001-06-14 2005-01-18 Integrated Sensing Systems Process of forming a microneedle and microneedle formed thereby
JP2003007621A (ja) * 2001-06-21 2003-01-10 Nikko Materials Co Ltd ＧａＮ系化合物半導体結晶の製造方法
US7052622B2 (en) * 2001-10-17 2006-05-30 Applied Materials, Inc. Method for measuring etch rates during a release process
US6875279B2 (en) * 2001-11-16 2005-04-05 International Business Machines Corporation Single reactor, multi-pressure chemical vapor deposition for semiconductor devices
JP3970011B2 (ja) * 2001-12-11 2007-09-05 シャープ株式会社 半導体装置及びその製造方法
US20030124818A1 (en) * 2001-12-28 2003-07-03 Applied Materials, Inc. Method and apparatus for forming silicon containing films
US6723622B2 (en) * 2002-02-21 2004-04-20 Intel Corporation Method of forming a germanium film on a semiconductor substrate that includes the formation of a graded silicon-germanium buffer layer prior to the formation of a germanium layer
US7452757B2 (en) * 2002-05-07 2008-11-18 Asm America, Inc. Silicon-on-insulator structures and methods
US6812495B2 (en) * 2002-06-19 2004-11-02 Massachusetts Institute Of Technology Ge photodetectors
US7238595B2 (en) * 2003-03-13 2007-07-03 Asm America, Inc. Epitaxial semiconductor deposition methods and structures
US7132338B2 (en) * 2003-10-10 2006-11-07 Applied Materials, Inc. Methods to fabricate MOSFET devices using selective deposition process

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020079507A1 (en) * 2000-12-27 2002-06-27 Shim Kyu Hwan SiGe MODFET with a metal-oxide film and method for fabricating the same
US20020185686A1 (en) * 2001-06-12 2002-12-12 International Business Machines Corporation Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing

Also Published As

Publication number Publication date
US20090189185A1 (en) 2009-07-30
EP1649495A2 (en) 2006-04-26
JP2007511892A (ja) 2007-05-10
WO2005013326A3 (en) 2008-07-10
KR20060039915A (ko) 2006-05-09
US7514372B2 (en) 2009-04-07
TW200509226A (en) 2005-03-01
WO2005013326A2 (en) 2005-02-10
US20050051795A1 (en) 2005-03-10
US7666799B2 (en) 2010-02-23

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