TWI362689B - Method for forming fine pattern of semiconductor device - Google Patents

Method for forming fine pattern of semiconductor device Download PDF

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Publication number
TWI362689B
TWI362689B TW096147906A TW96147906A TWI362689B TW I362689 B TWI362689 B TW I362689B TW 096147906 A TW096147906 A TW 096147906A TW 96147906 A TW96147906 A TW 96147906A TW I362689 B TWI362689 B TW I362689B
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Taiwan
Prior art keywords
mask
pattern
film
layer
reticle
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TW096147906A
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English (en)
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TW200849328A (en
Inventor
Ki Lyoung Lee
Keun Do Ban
Cheol Kyu Bok
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Hynix Semiconductor Inc
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Publication of TW200849328A publication Critical patent/TW200849328A/zh
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Publication of TWI362689B publication Critical patent/TWI362689B/zh

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274Photolithographic processes
    • HELECTRICITY
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0332Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
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    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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    • H01L21/0338Process specially adapted to improve the resolution of the mask
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    • H01L21/321After treatment
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Description

1362689 九、發明說明: ' 相關申請案之交互參照 * 特此主張申請於2007年6月5日韓國專利申請號10- 2007-0054974之優先權利益且其之揭示以其全文引用方式 納入本文中。 【發明所屬之技術領域】 本發明通常係有關一種於半導體元件形成細緻圖案的 方法。 # 【先前技術】 由於資訊媒體例如電腦之普及,半導體元件技術已經 、 快速地升級。半導體70件需要以高速度操作且需要具有高 , 儲存容量。結果’帛導體元件之製造技術需要製造具有改 良之整合、可靠度和存取資料的特性之高容量的記憶元 件。 為了改良元件之整合’已經發展光刻技術以形成細緻
圖案。光刻技術包括使用化學放大型深紫外光(Duv)光 源例如ArF(193 nm)和Vuv(l57 —之曝光技術,和 用於將適合於曝光光源之光阻材料顯影的技術。 在光刻技術中控制圖案線 半導體元件之處理速度視 ’隨著圊案之線寬被減少, 當半導體元件變得更小時, 見之關鍵尺寸是重要的。通常, 圖案線寬的關鍵尺寸而定。例如 處理速度被增加以改良元件性能 然而,在使用具有小於 光器之光刻方法中,藉由單— 1·2之一般數值孔徑的ArF 曝光方法難以形成小於4 0
1362689 之線/間距圖案。 為了改良光刻技術之解析和擴充製程範圍(pr〇cess margin)’已經發展雙重製作圖案技術。雙重製作圖案技術 包括藉其光阻-塗布之晶圓以二個光罩分別地曝光且然後顯 影而藉此獲得複雜圖案、密集圖案或隔離圖案之方法。 因為雙重製作圖案技術於製作圖案使用二個光罩,製 造成本和週轉週期(turn_ar〇und_time)低於使用單一光罩 之單一製作圖案技術之製造成本和週轉週期,藉此降低通 產量(throughput)。當具有小於曝光器之解析限度的間 距(P滅)之圖案在胞區(cell regi〇n)形成時,假像被重疊。 結果,雙重製作圖案技術無法獲得所要的圖案。在對準中, 。亥荨覆蓋為對準失敗(mis_alignment )。 【發明内容】 本發明之各種具體實例係有關提供一 的方法。 乘 根據本發明之一具體實例,一種於半導體元件形成細 緻圖案的方法包含在具有底層之半導體基材上面形成—種 I括第個、第二個 '和第三個光罩薄膜之層疊薄層(s⑽ 。在第二個光罩薄膜上面形成光阻圖案。用光阻圖 /、:”、蝕刻阻障光罩蝕刻第三個光罩薄膜以形成第三個光 罩圖案。用第三個光罩圖案作為钱刻阻障光罩姓刻第二個 一第_光罩薄膜以形成第一個和第二個光罩圖案。用 二個光罩圖案作為鞋刻阻障光罩側面儀刻第二個光罩圖 6 1362689 案。移除第三個光罩圖案。在第一個和第二個光罩圖案上 面塗布旋塗碳層,經由旋塗碳層第二個光罩圖案之上部被 曝光。藉由旋塗碳材料作為蝕刻阻障光罩, 7 %弟一個圖 案:第二個光罩圖案的部分以曝光底層。移除旋塗碳層以 獲得具有均勻線寬之細緻第一個光罩圖案。 底層可包含一具有絕緣薄膜和聚合物層作為頂層之疊 層圖案的導電層。第一個和第三個光罩薄膜具有與第二個 光罩薄膜之蝕刻選擇性比不同的蝕刻選擇性比。例如,第 個光罩薄膜為鎢層^第二個光罩薄膜較佳係選自一或多 個之氮化矽薄膜(SiN)、氧化矽薄膜(Si〇)、氮氧化矽 薄膜(SiON )、和包括至少一或多個其薄膜之堆疊層。第 二個光罩薄膜較佳係選自一或多個之非晶形碳層、包括非 晶形碳層和氮氧化矽薄膜之堆疊層、和多光罩(mulu mask) 薄膜。多光罩薄膜較佳地藉由i)旋塗碳材料(其中碳元 素以85重量%至90重量%範圍之量存在,以總化合物分 子量為基準)形成,或π)包含Si化合物(其中Si元素 以30重量%至80重量%範圍之量存在,以總化合物分子 量為基準)之光罩的組成物形成。n ) Si化合物較佳地選 自由含Si聚合物、含Si聚合物之寡聚物和旋塗玻璃(s〇g) 材料例如氫倍半矽氧烷(HSQ)或甲基倍半矽氧烷(MSQ) 組成之群組。 側面蝕刻第二個光罩圖案步驟係藉由修整蝕刻方法進 行。修整蝕刻方法在第二個光罩薄膜中具有高於第一個或 第二個光罩薄膜之磨光速度的磨光速度。修整蝕刻方法係 7 136258^ (例如CHxFy,在此X和y為在1至1〇 範圍之整數):Λ 6 =2_10 : 1的流量比之蝕刻氣體進行。 在此,該氟煙氣體為CHF3氣體。 -^固 *1* 罢 側面姓刻方法之心=上進行側面姓刻方法之後’與進行 . ^的第二個光罩圖f之線寬比較,第二個 30 35%、具有減少 '約2〇_5〇%,特別地3〇_4〇%,更特別地, 30_35%之線寬。 牙、第一個光罩圖案和旋塗碳層步驟較佳地各自藉由 氧灰化方法推奸哲 分目精田 宰 。一個光罩圖案之線寬對第一個光罩圖 条之間的間隔之比為1 : 。 *法種於半導體元件形成細緻圖案的 個至第層之+導體基材上面形成-種包括第- 和第-個丄$ 、的層疊(stack咖)。蝕刻第二個 ::先罩薄膜以形成第二個和第三個光罩圖案 圖案作為'刻阻障光罩部分"刻第-個 光罩薄膜^ m罩圖案作為㈣阻障光罩對第二個 :先=側面㈣方法。移除第三個光罩圖案。在第 -個和第;、之上部的上面之旋塗碳層被曝光且塗布在第 罩圖案及底層上。第-個圖案和第二個光 光底声°p刀猎由旋塗碳層作為蝕刻阻障光罩移除以曝 膜被曝光。 ^層和一部分之第一個光罩薄 下部!::光:薄膜之部分钱刻的步驟較佳地包括形成其 邛互連而不曝光底圖案之第一個光罩圖案。 8 1362689 本發明的方法可包含一種光阻蝕刻阻障光罩方法步 驟’其進行一次以形成光罩圖案,藉此簡化製造成本和方 法步驟以改良效率。 根據本發明之一具體實例,該方法可改良由於光阻圖 案之重f的覆蓋對準失敗(mis_alignment ),藉此獲得一 種具有用現在的光刻設備不能形成之間距的圖案。 【實施方式】
特殊具體實例之詳細說明 將參考所附圖式詳細地說明本發明。 為了防止重疊和對準失敗(Mis_alignment),發展η -種雙重曝絲刻技術(DEET)和u)間隔製作圖案技術 (SPT),其已被使用於半導體元件製備方法中。 i) DEET包含形成具有大於所需要的圖案兩倍之線 寬的第-罐,和形成具有第一個圖案之間的相同線寬 之第二個圖案。更狀言之,DDET包括〇正型方法和b) 負型方法。 如圆尸/r不,在a)正型方法中, τ 底層3、第一個光 罩薄膜5、第二個光罩薄膜7和第一 弟個正光阻圖案8係在 半導體基材1上面形成。第二個光薑 九罩圖案7-1係用第一個 光阻圖案8作為蝕刻阻障光罩形成。 , m 乐一個正光阻圖牵9 在第二個光罩圖案7-1之間形成。笛 〃 第一個光罩圖案5_ι俏 用第二個光罩圖案7-1和第二個光阻 :’、 光罩形成。 _案9作為钱刻阻障 23 '第一個 如圖2中所示。在b)負型方法 , 丫,底層 9 1362689 光罩薄膜25、第二個光罩薄膜27和第一個負光阻圖案28 係在半導體基材21上面形成。第二個光罩圖案271係用 第一個負光阻圖案28作為蝕刻阻障光罩形成。第二個負 光阻圖案29係在第二個光罩圖案27_丨和第一個光罩薄膜 25上面形成,用第二個負光阻圖案29作為蝕刻阻障光罩 蝕刻第二個光罩圖案274以形成第二個光罩圖案27_2〇 用第二個光罩圖案27-2作為蝕刻阻障光罩蝕刻第一個光罩 薄膜25以形成第一個光罩圖案25-1。 因為DEET使用二種光罩,所以可能形成一具有所要 間距大小之圖案。然而,方法步驟是複雜的,且製造成本 增加。而且,當第二個光阻圖案形成時,由於圖案之覆蓋 的不準確而發生對準失敗(mis-alignment)。 ii) spt為一種以防止對準失敗(mis_aHgnmen〇的 自動對準(Self-alignment )技術,其係藉由在胞區進行用 於形成圖案之光罩方法。SPT包括a)正型方法和b)負 型方法。 如圖3中所示,在a)正型方法中,底層33、第一個 光罩4膜3 5、第二個光罩薄膜3 7和第一個光阻圖案3 8係 在半導體基材31上面形成。第二個光罩圖案37_丨係用第 一個光阻圖案38作為蝕刻阻障光罩形成。間隔39係在第 二個光罩圖案37-1之側壁形成。第一個光罩圖案35_丨係 用間隔3 9作為蝕刻阻障光罩形成。 如圖4中所示’ b)負型方法包括在半導體基材41上 面形成底層43、第一個光罩薄膜45、第二個光罩薄膜47 1362689 和第-個光阻圖案48’和用第—個光阻圖案48作為㈣ 阻障光罩形成第二個光罩圖案卜間隔49係在第二個 光罩圖案47-!之側壁形成。旋塗玻璃薄膜5〇或抗反射薄 膜係塗布在所產生之結構上面。進行CMp或回钱(心_ back)方法以曝光第二個光罩圖案(不顯示)。移除 間隔’和用第二個光罩圖案47]作為㈣阻障光罩形成第 —個光罩圖案454。 SPT需要額外的光罩方法以便在核心和邊緣部分中形 f圖案或隔離迷你胞段區之㈣ 部分。結I’方法步驟是複雜的。且,當間隔形成時難以 調整圖案之線寬,因此降低圖案線寬之均句性。 圖5a至5i為說明根據本發明之一具體實例的於半導 體疋件形成細緻圖案的方法。 圖5 a顯不第一個$笛—/ΐϊΐ、丨,切 主第二個光罩溥膜113、115、和117 和有機抗反射薄膜119,其分別地依序沈積在底層m上 面。 曰在此具體實例中’底層為一包括閘極氧化物薄膜、多 夕層嫣層和絕緣薄膜之導電層。絕緣薄膜具有一種包 括多層(poly layer)和絕緣薄膜之堆疊結構。 在此八體實例中,第一個光罩薄膜⑴包括鶴(w)。 在此具體實例中,第_ 弟一個先罩薄膜115包括氮化物薄膜 )氧化物薄膜(Sl0)、氮氧化矽薄膜(SiON), t包括至少一個或更多該薄膜之堆疊層。在此具體實例 第一個光罩薄膜i i 7包括非晶形碳層或包括非晶形碳 11 1362689 層和氮氧化矽薄膜之堆疊層。 較佳地第-個和第三個光罩薄膜具有與第二個光 臈之钱刻選擇性比不同的钱刻選擇性比。較佳地第—個 和第三個光罩薄膜具有低於第:個光罩薄膜之_選擇性 比和钱刻速度之一或兩者, 久权佳地對各種的蝕刻氣 體。更特定言4,第一個光罩薄膜較佳地包括鎢薄臈,第
二個光罩薄臈較佳地包括氮化物薄膜,和第三個光罩薄膜 較佳地包括-包括非晶形碳層和氮氧切薄膜之堆疊層。 使用作為第-個光罩薄膜之鶴薄膜可在後來用於形成 閘極圖的蝕刻方法期間被用作蝕刻阻障光罩時被移除。結 果’不需進行移除鎢薄膜之額外方法。 、° 第三個光罩薄膜較佳地包括多光罩薄膜,其可藉由旋 轉塗布方法形成且具有取代包括非晶形碳層和㈣化石夕薄 膜,堆疊層的優良平坦化性f。多光罩薄膜不使用像非晶 /反層樣的化學氣相沈積,且效率是極佳的。 可使用任何種類的多光罩薄膜。多光罩薄膜在製造半 導體元件之一般法中可作為用於改良姓刻選擇性比之光罩 薄膜和作為用於增加均勻性之抗反射薄膜。一較佳多 光罩薄膜在第一個具體實例中係藉由丨)旋塗碳材料(其 2呶兀素以85重量%至90重量%範圍之量存在,以總化 。物刀子里為基準)形成,或在第二個具體實例丨丨)中, 藉由包含Si化合物(其中Si元素以3〇重量%至8〇重量 %範圍之量存在,以總化合物分子量為基準)之光罩組成 物开/成。第二個具體實例H ) Si化合物可為含以聚合物、 12 一〜來口物之养聚物和s〇G材料例如HSQ和MSQ。更特 旦、之光罩組成物較佳地包含一種在30重量份至7〇重 ::範圍之篁(以100重量份之組成物為基準)的含Si聚 :物和殘餘的有機溶劑作為主要的成份。光罩組成物較佳 進一步地包含弋 1 ^ 人A 式2、熱酸產生劑或光酸產生劑之化 ά物3
[式2]
”中Ra Rd各個為氫或經取代或未經取代之直鏈或支
鏈C丨-C5烷基基團盔 e為5至500之整數,f為〇至5之整 數’和g為1至5之整數。 式1化合物之分;县&仏, 刀卞3:較佳地在5〇〇至50,000之範圍。 含Si聚合物之分早 刀于量較佳地在300至30,000之範圍。 含S i聚合物較佳地句妊_ 或多種選自式3至5之化合物的 基礎樹脂。 13 1362689 [式3]
其中心和R2各個為氫或經取代或未經取代之直鏈或 支鍵(^-(^烧基基團,和m、η和〇各自獨立地為在1至10 範圍之整數。 [式4]
其中R3為氫、經取代或未經取代之直鏈或支鏈Ci-C5 烷基基團、經取代或未經取代之c3-c8環烷基基團、或經 取代或未經取代之C5-C12芳族基團,及X和y各自獨立為 在0至5範圍之整數。
14 1362689 其中尺⑺為^^^呂丨⑴尺’^尺’為氫或直鏈或支鏈匸·。 - 1 1 ( 烷基,和k為1至10之整數。 用於多光罩薄膜之旋塗碳材料較佳地包括日產化學公 司(Nissan Chemical Co.)的SHN18,或用於多光罩薄膜 之si化合物較佳地包括日產化學公司的mHN〇4。 圖5b顯示在有機抗反射薄膜119 (其為頂層)上所形 成之光阻圖案1 21。 光阻薄膜(不顯示)係塗布在有機抗反射薄膜上,和 鲁在光阻薄膜上進行光刻方法以獲得光阻圖案121。光阻圖 案121之間距較佳地為設計規則的二倍大。較佳地,光阻 - 圖案之線寬對圖案間之間的間隔之比為3 : 1。 卜圖5(:顯示用光阻圖案121作為蝕刻阻障光罩所形成之 第二個光罩圖案117_丨和有機抗反射圖案丨丨、^。 圖5d顯示用第三個光罩圖案117_丨和有機抗反射圖案 119-1作為蝕刻阻障光罩所形成之第二個光罩圖案lb」 鲁和第-個光罩圖案113_!,其包括開口部份以曝光底層⑴ (參見® 6a,其顯示本發明之一具體實例,纟中第一個光 罩圖案U3-1為鶴層、第二個光罩圓案ιΐ5ι包括一包括 氮化物薄膜(SiN)和氮氧化梦薄膜(Si〇N)堆疊層之沈 積光罩氮化物薄膜(HMNit),和第三個光罩圖案i… 為非晶形碳(A-C )層)。 :行敍刻方法以用第三個光罩圓案作為钮刻阻 SSL:和第二個光罩薄膜(113和115,分別地) 到底層111被曝光。部分鞋刻方法係在第一個 15 1362689 广頂部上進行而不曝光底層,藉此形成其底 之第-個光罩„ (不顯示)。當形成其底部連接 個光罩圖㈣’第—個光罩薄膜較佳地包括鶴或多 層(poly layer)。 作為蝕刻阻障 圖5e顯示藉由用第三個光罩圖案117 光罩進行修整方法所獲之所產生的結構。 進行修整蝕刻方法以用一種邏鳋 印徑避輯方法均勻地調整圖案
•^寬修正㈣方法用上層材料作為㈣阻障光罩過姓刻 (—h)下層材料以調整下層材料之線寬。在此,下 層材料之蝕刻選擇性比與上層封斜 , ,、工層柯村不冋。在習知DRAM方 法中不進行修整姓刻方法。 第-個和第三個光罩薄膜兩者用與第二個光罩薄膜差 異大之㈣選擇性比進行修整㈣方法致使第二個光罩薄 臈之側壁可被均勾钱刻而沒有損失第一個和第三個光罩薄 臈。即,在修整钱刻方法中,對於一被選擇姓刻氣第二 個光罩薄帛115具有高於第一個光罩薄冑ιΐ3之蝕刻速度 的触刻速度以及高於第三個光罩薄膜m之㈣速度㈣ 刻速度。、结果,在修整钱刻方法中第二個光罩圖案ιΐ5ι 之側壁首先被姓刻和移除。 進打修整姓刻方法,較佳地用氟烴氣體(例如CHxFy, ,此X和y為在i至1G範圍之整數)對鶴作為鈍化姓刻 氣且較佳地用SFe氣體以蝕刻氮化物薄膜。更佳地,修整 触刻方法係用具有CHF3氣體:% = 2 _丨〇 :丨較佳地,4 ;5 : 1的流量比之蝕刻氣進行。 1362689
進行修整钱刻方法直到第二個光罩圖案ιΐ5 2 〇之線 寬具有與光阻圖案之間的間隔相同的大小,或η)減少在 修整钱刻方法進行之前的第二個光罩圖案115-1之線寬大 广約20-50% (參見圖6b,其顯示在修整蝕刻方法進行之 後減少線寬大小約20_50%之第二個光罩圖案卜第三個 :罩圖案不被蝕刻氣損害。而且,因為其底部被連 之第-個光罩圖帛113](不顯示)係藉由部分蝕刻方 ’形成,雖然底層⑴由絕緣薄膜形成,留在底層之上的 第—個光罩圖案⑴·!作為阻障薄膜以防止底&⑴ 刻氣損害。 參考圖5f,在所產生結構上進行^灰化方法以移除 殘餘的第三個光罩圖案117-1。 旋塗碳層123係在所產生之結構上面形成。旋塗碳層 ^地具有以在85重量%至9G重量%範圍之量存在的碳 :素含量,以總分子量為基準。像第三個光罩薄膜,可使 用曰產化學公司之SHN18。 圖5g顯示所產生之結構,其中藉由在旋塗碳層 進行回蝕方法將第二個光罩圖案115·2之頂部曝光 回敍方法較佳地係用選自氧、f、 礼氣虱和其組合之蝕刻氣進 仃0 姓刻方法,較佳地蝕刻旋 罩圓案115-2之底部外面 作為蝕刻阻障光罩移除經 為了以安定條件進行後來的 塗碳層而不曝光安排在第二個光 的第—個光罩薄膜圖案113_】。 參考圖5h,用旋塗碳層123 17 !?62689 曝光的第二個光罩圖案115·2和位於經曝光的第二個光罩 圖案之下的第—個光罩圖案1131之部分以曝光底層⑴。 結果,形成包括開口部份125之第一個光罩圖案^3 2。 對於氮化物或鎢較佳地用蝕刻氣體例如SF6、、 Ar及其組合進行蝕刻方法。 2 2
第一個光罩圖案113_2之線寬較佳地被減少至小於第 個光罩圖案113_1之線寬約1/3的大小。當顯影檢視關 鍵尺寸(DICD )以其本身轉錄時,第一個光罩圖案具有與 光阻圖案之間的間隙相同的大小。例%,當蝕刻偏差 (etching bias )為80 nm和設計規則為4〇 nm元件時第 —個光罩圖案之線寬對第一個光罩圖案之間的間隙之比為 參考圖5i,在所產生結構進行上%灰化方法以移除旋塗 碳層123。 當第一個光罩圖案113-1之底部互連時,在第—個光 罩圖案113-1之連結部份上進行過(〇ver)灰化方法以暴 露底層,藉此獲得均勻細緻圖案。 用第一個光罩圖案11 3-2作為姓刻阻障光罩餘刻下導 電層(不顯示)以形成導電圖案。導電圖案可包括閉線、 位元線和金屬線。較佳地進行一額外光罩方法以在除了胞 區域外之核心和邊緣部分中形成圖案。 用具有與設計規則之二倍大的間距之暴露光罩圖案, 可形成具有減少間距之圖案。與使用二個光罩之習知雙重 製作圖案技術比較’可獲得自我對準(self_align)圖案而沒 1362689 有覆蓋對準失敗(mis-alignment)。 如上所述,根據本發明之一具體實例,進行修整方法 以減少在底層上面所形成之光罩圖案的線寬。將旋塗碳材 料塗布在所產生之結構上面。用旋塗碳層作為蝕刻阻障光 罩來蝕刻光罩圖案以簡化方法步驟和獲得具有均勻線寬之 細敏圖案而不論曝光器的覆蓋準確性。 上述本發明之具體實例為說明的且不為限制的。各種替代 方案和同等物是可能的。本發明不被本文所描述的光刻步 驟限制。本發明也不被限制於任何特定類型之半導體元 牛例如本發明可在動態隨機存取記憶體(dynainic random access mem〇ry ) ( DRAM )元件或非揮發性記憶體元件中 實施。鑑於本揭示,其他增加、減少、或修正將為一般技 藝人士顯而易知的,且意欲落在所附申請專利範圍之範圍 内。 L圚式簡單說明】
圖1為說明習知正型雙重製作圖案方法之圖式。 圖2為說明習知負型雙重製作圖案方法之圖式。 圖3為說明習知正型間隔製作圖案方法之圖式。 圖4為說明習知負型間隔製作圖案方法之圖式。 圖 5 a 至 ς · ^ 1為說明根據本發明之一具體實例的於半導 體兀件形成細緻圖案的方法。 圖仏為說明圖5d的方法之SEM相片。 圖6t>為說明圓5e的方法之SEM相片。 【主要元件符號說明】 19 1362689 1、21、31、41 :半導體基材 3、23、33、43、111 :底層 5、25、35、45 :第一個光罩薄膜 5-1、25-1、35-1、45-1 :第一個光罩圖案 7、 27、37、47 :第二個光罩薄膜 7-1、27-1、27-2、3 7-1、47-1 :第二個光罩圖案 8、 38、48:第一個正光阻圖案 9:第二個正光阻圖案 , # 28 :第一個負光阻圖案 29 :第二個負光阻圖案 39 、 49 :間隔 50 :旋塗玻璃薄膜 ' 1 1 3 :第一個光罩薄膜 1 13-1、113-2 :第一個光罩圖案 1 1 5 :第二個光罩薄膜 115-1、115-2 :第二個光罩圖案 _ 117:第三個光罩薄膜 117-1 :第三個光罩圖案 1 1 9 :有機抗反射薄膜 119-1 :有機抗反射圖案 1 2 1 :光阻圖案 123 :旋塗碳層 125 :開口部份 20

Claims (1)

1362689 申請專利範圍 101年1月12曰修正替換頁 _ 丨。丨年丨月丨崎修正本 含 • 一種於半導體元件形成細緻圖案的方 在:有底層之半導體基材上面形成—包括第一個光罩 =膜1二個光罩薄膜和第三個光罩薄膜之疊薄 turn); 在第二個光罩薄臈上面形成光阻圖案; 使用光阻圖案作為飯刻阻障光罩將第三個光罩薄膜製 作圖案以形成第三個光罩圖案; 、 使用第三個光罩圖案作為钱刻阻障光罩將第一個和第 一個光罩薄膜製作圖荦彡 戸圆茶以形成第一個和第二個光罩圖案; 使用第三個光罩圊牵# A 作為蝕刻阻障光罩將第二個光罩 圖案側面蝕刻; 4 移除第三個光罩圖案; 在第'一個光罩圖宰上面形士、. 罩圖案之上部曝光;㈣成-旋塗碳層以使第二個光 進行=Ϊ=層(SP1一·earbGn layer)作為餘刻阻障光罩 進仃蝕刻方法以曝光底層 早 罩圖案形成】 “包括開口部份之第一個光 移除旋塗碳層。 2·根據"專利範圍第 、浥緣薄膜和作為頂層之聚 ,、有 ,α ^ ^ ^ 初層之疊層圖案的導電層。 3.根據申請專利範圍第 嘴具有與第二個光罩薄膜之二的方法,其中第-個光罩薄 、 χΙ丨選擇性比不同的蝕刻選擇 21 1362689
刻選 性比,和第三個光罩薄膜具有與第 擇性比不同的钱刻選擇性比。 /·根據巾請專利範圍第1項的方法,其中第-個光㈣ 膜為鶴層。 / 5·根據申請專利範圍第1項的方法,其"二個光罩薄 膜係選自由氫化石夕薄膜、盡各 # ㈣_㈣膜、氮氧切薄膜,及 其組合組成之群組。 6·根據申請專利範圍第Μ的方法,其中第三個光罩薄 膜為非晶形碳層、包括非晶形碳層和氣化氧化石夕㈣咖 oxide nitride)薄膜之堆疊層、或多光罩薄膜。 : 二據申請專利範圍第6項的方法,其中多光罩薄膜係 藉由敎塗蝴.(其中碳元素以85重量%至90重量%範 圍之量存在,以總化合物分子量為基準),或包含以化合 物(其令Si元素以3〇重量%至80重量之量存[ 以總化合物分子量為基準)的光罩組成物形成。 8一·根據中請專利範圍第7項的方法,其中多光罩薄膜係 曰種包含選自由含Si聚合物、含Si聚合物之寡聚物和 紅塗玻璃材料組成之群組的Si化合物之光罩組成物形成。 9·根據申請專利範圍第8項的方法,其中旋塗玻璃材料 ·,,、虱倍半_氧院(HSQ)或f基倍半碎氧院 (MSQ) 〇 10·、根據申請專利範圍第i項的方法,其包含藉由修整 蝕刻方法側面蝕刻第二個光罩圖案。 土产哲根據申°月專利圍第10項的方法,其中修整餘刻方 >在第二個光罩薄膜中具有高於第一個或第三個光罩薄膜 22 101年1月12曰修正替換頁 之磨光速度的磨光速度 12.根射請專利範圍第⑺項的方法,進—步包含用且 之氟煙氣體對SF6的流量比之㈣氣體進行修整 ^艮據申請專利範圍第12項的方法,其中說烴氣體為CHF3 一猶根射請專利範圍第1項的方法,進-步包含進行 種側面钱刻方法,以減少望—彳田土 s π 0/ t 我夕弟一個先罩圖案之線寬20-50 %,與減少之前的第二個光罩圖案之線寬比較。 1M艮據申請專利範圍第14項的方法進一步 —種側面蝕刻方法,以诘,丨、 0/ , 以減少第二個光罩圖案之線寬30-40 % ’與減少之前的第-低 π弟—個先罩圖案之線寬比較。 1 6 ·根據申請專利範圍 葡允儿一 項的方法,進-步包含藉由 氧火化方法進行移除第三個 尤卓圖案和旋塗碳層之步驟。 17 ·根據申請專利筋圍楚1 tS 刊靶圍第1項的方法,進-步包含在第 —個和第二個并:I岡安L ^ _ # ™ ^ 、行使用旋塗碳層作為银刻阻障 先罩之蝕刻方法。 平 1 8 ·根據申請專利圖笛 碳層之後,n/ 法,其中在移除旋塗 為丨,i 固光罩圖案之線寬對圖案之間的間隔之比 19.根據申請專利範 罩舊m 粑固第1項的方法,其中該第-個光 皁溥臈之製作圖案包含 ^ A ^ 丁使用第一個和第三個光罩圖案 乍為姓刻阻P早光罩在第— 蝕刻士、+ 個九罩溥膜上部分蝕刻;和進行 蝕刻方法以移除旋塗碳 叮 # 4分之第一個光罩薄膜直到 23 101年1月12曰修正替換頁 底層被曝光。 --- --- 2〇·根據申請專利範圍第19項的方法,其中進行在第一 光罩薄膜上之部分蝕刻以不使底層曝光,藉此形成其下 部互連之第一個光罩圖案。 十一、圖式: 如次頁 24
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US7576009B2 (en) 2009-08-18

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