TWI355069B - Dram device - Google Patents

Dram device Download PDF

Info

Publication number
TWI355069B
TWI355069B TW096141857A TW96141857A TWI355069B TW I355069 B TWI355069 B TW I355069B TW 096141857 A TW096141857 A TW 096141857A TW 96141857 A TW96141857 A TW 96141857A TW I355069 B TWI355069 B TW I355069B
Authority
TW
Taiwan
Prior art keywords
gate
recessed
oxide layer
semiconductor substrate
region
Prior art date
Application number
TW096141857A
Other languages
English (en)
Other versions
TW200921902A (en
Inventor
Shing Hwa Renn
Original Assignee
Nanya Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nanya Technology Corp filed Critical Nanya Technology Corp
Priority to TW096141857A priority Critical patent/TWI355069B/zh
Priority to US12/049,385 priority patent/US7948028B2/en
Priority to JP2008115410A priority patent/JP4857307B2/ja
Priority to DE102008023622.5A priority patent/DE102008023622B4/de
Publication of TW200921902A publication Critical patent/TW200921902A/zh
Application granted granted Critical
Publication of TWI355069B publication Critical patent/TWI355069B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/2822—Making the insulator with substrate doping, e.g. N, Ge, C implantation, before formation of the insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/82385—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823885—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Semiconductor Memories (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Description

1355069 九、發明說明： 【發明所屬之技術領域】 本發明係有關於深溝渠電容(deep trench capacitor)動態隨機存 取記憶體(dynamic random access memory，簡稱為 DRAM)技術領 域’特別是有關於DRAM週邊電路(support circuit)的電晶體元件。 【先前技術】 如熟習該項技藝者所知，DRAM的記憶胞通常是在較高的電 壓fe圍下操作，因此，其週邊電路中的高壓M〇s電晶體元件的閘 極氧化層可靠度顯得特別重要。 目前，為了解決P+閘極MOS電晶體元件的硼穿透(b〇r〇n Penetrati°n)問題，通常是去輕電縣化法(deonipledpia麵 —datlon ’間稱為DpN)等技術，將氣引進舰μ週邊電路的間極 =二I^面’在閘極氧化層中引進高濃度I的作 _閘細⑽電晶體元件賴極氧化層的可靠度下 靠度。 週二是無法兼顧到 ⑽電晶體元件的間極氧化層柯"乍效能以及咖+間極 1355069 【發明内容】 本毛月主要目的在提供一種改良之dram週邊電路中的 NMOS 可以_兼細週邊電路的低壓 件的閘極氧件的知作效能以及高麼n+閘極m〇s電晶體元 發明之較佳實施例，本發明提供一種動態隨機存取記 包含有—半導體基底，其上形成有 區; 一凹入式間極’嵌入於該閉極溝渠中，·一源極推雜 %:…凹人朗極—側的該半導體基底中；—祕摻雜區， 凹人式開極另-側的該半導體基底中；及—閘極氧化層， ==入式問極與該料體基底之間，該間極氧化層具有^少 的=的厚度，魏出—種觸的不對獅構，財厚度較厚 較凹入式間極與職極推雜區之間，而厚度 她乳化層則是位於該凹入式間極與該源極摻雜區之間。 特舉上ΓΓ特徵、和優點能更明顯易懂，下文 作詳細說明如下。然而如 加以Γ 賴料核說彻，財料對本發明 1355069 【實施方式】 凊參閱第丨圖，其為依據本發明較佳實施例所繪示的DRAM 元件部分區域的剖面示意圖。如第丨圖所示，DRAM元件1包含 有至少一記憶體陣列區域100以及一週邊電路區域，其中，在 記憶體陣列區域100中設有複數個記憶胞10，每一個記憶胞10 係由一延伸U型通道元件(extendedu-shapedevice，簡稱為 ^ EUD)12以及一深溝渠電容Η所組成。 為簡化說明’在第1圖中僅顯示出其中—個記憶胞⑴。前述 的延伸u型通道元件12又可稱為凹人式通道陣狀件(recess channd array device，簡稱為RCAT)，或者凹入式閘極M〇s電晶 體元件。 延伸U型通道元件12包含有一凹入式問極⑵、一源極推雜 • 區123、一汲極摻雜區丨24以及一閘極氧化層125。其中，凹入式 -_ 121係嵌入於敍刻至半導體基底⑴2 -預定深度的閘極溝渠 featetrench)l22内，且凹入式閘極121可以包含有多晶矽、金屬或 者其組合。 閘極溝渠122可大賴分為垂直_部分ma以及口型底部 122b ’而延伸U型通道元件12的u型通道126即位於口型底： • 122b。 _ 1355069 根據本發明之較佳實_，深溝渠電容結構M包含有一捧雜 多晶石夕(doped P〇lysilicon)層141以及一側壁電容介電㈣副 capacitor dielectri_ 142 ’例如，氧化石夕遗化石夕氧化矽 (oxide-nitride-oxide ’簡稱為〇NO)介電層。換雜多晶石夕層⑷係用 來作為深溝渠電容結構14之上電極。 為簡化說明，溝渠電容結構14的埋入式電容下電極(buried plate)並未特別顯示在圖中’而僅簡要顯示溝渠電容結構14的上部 構造。 此外，在溝渠電谷結構14的上部，利用所謂的「單邊埋入導 電f (Single-Sided Buried Strap ’簡稱為SSBS)」製程形成有單邊埋 入導電帶143 ’以及溝渠上蓋層(TrenchT0p〇xjde，簡稱為 ΤΤΟ)144。其中’溝渠上蓋層！私可以是氧化石夕所構成，例如，以 尚密度電漿化學氣相沈積(high-density plasma chemical vapor deposition，簡稱為HDPCVD)法所沈積者。 前述的「單邊埋入導電帶」製程通常包括有以下的步驟··將 側壁電谷介電層丨42以及多晶石夕層（p〇iy_2)i41回钱刻至一第一預 定深度，再填入另一多晶矽層(P〇ly_3)，回蝕刻P〇丨y_3至第二預定 深度後，在P〇ly-3上形成不對稱的側壁子，然後蝕刻未被該側壁 子覆蓋的Poly-3以及P〇ly-2 ,最後，填入ττο石夕氧絕緣層，再以 化學機械研磨製程將TT0矽氧絕緣層平坦化。 1355069 L伸U型通迢元件12係透過沒極摻雜區ι24與經由溝渠電容 結構14的單邊埋人導電帶143物出來的擴散區域145相連接。 電子或者電騎經由位讀(@絲)财接職塞⑽、延伸u型 通道元件12的源極摻雜區123、開啟的u型通道126、沒極摻雜 區124、擴散區域145所構成的路徑到達深溝渠電容14的上電極， 並進行資料的存取動作。 根據本發明之較佳實施例’延伸U型通道元件丨2中用來容納 凹入式閘極121的閘極溝渠122的深度山約介於1500埃至2500 埃之間，而寬度％約介於2〇〇埃至6〇〇埃之間。 根據本發明之較佳實施例，在週邊電路區域2〇〇内的半導體 基底102上至少設有一高壓MOS電晶體元件20以及一低壓MOS 電晶體元件30。在高壓MOS電晶體元件20以及低壓MOS電晶 體元件30之間可以設有一淺溝絕緣(shan〇w trench isolation，簡稱 為STI)結構1〇4，用來電性隔離高壓MOS電晶體元件20以及低 壓MOS電晶體元件30。 其中’高壓MOS電晶體元件20包括一凹入式閘極221、一 源極摻雜區223、一汲極摻雜區224以及一閘極氧化層225。凹入 式閘極221係嵌入於蝕刻至半導體基底102—預定深度的閘極溝 渠222内’且凹入式閘極221可以包含有多晶石夕、金屬或者其組 合。 1355069
. 根據本發明之較佳實施例，高壓MOS電晶體元件20為NM0S 電晶體’其凹入式閘極221為N+摻雜多晶矽閘極。源極摻雜區223 内可以另外形成有一摻雜濃度較高的N+摻雜區223a，汲極摻雜區 224内可以另外形成有一摻雜濃度較高的N+摻雜區224a。 閘極溝渠222區分為垂直側壁部分222a以及ϋ型底部222b， 而尚壓MOS電晶體元件2〇的u型通道226即位於ϋ型底部 φ 222b。根據本發明之較佳實施例，用來容納凹入式閘極221的閘 極溝渠奶的深度山與閉極溝渠122的深度d丨相同，同樣介於15〇〇 埃至2500埃之間，但是閘極溝渠您的寬度％則大於閉極溝渠 ]22的見度w,。根據本發明之較佳實施例，閘極溝渠222的寬度 W2約介於1300埃至丨6〇〇埃之間。 本發明的技術特徵之一是週邊電路區域2 〇 〇内的高壓㈣s電 晶體元件20的間極結構與記憶體陣列區域100内的延伸u型通道 元件12的問極結構同樣是嵌入在半導體基底K)2 t，因此，梦程 上是完全相容的。 則 化展—技術_是高壓M〇S電晶體元件2G的閉極氧 構具有峰不同的厚度，呈現出—賴制不對稱結 ^ 20 2253 M0S ^ 間極氧化層與__ 224之間，而厚度較薄的 ;凹入式閘極221與源極摻雜區223之間。 1355069 開極氧化層22%從閘極溝渠222靠近源極摻雜區223 —側的 3側壁部分222a向下延伸到u型底部皿。根據本發明之較 佳貫施例，閘極氧化層225a的厚度約介於15〇埃至3㈨埃之間， 而閘極氧化層225b的厚度約介於20埃至6〇埃之間。、 根據本發明之較佳實施例，低壓M〇s電晶體元件兕為一平 面通道PMOS電晶體，包括一問極32卜一 p+源極推雜區切、 一 P+沒極摻雜區324以及-閘極氧化層325。根據本發明之較佳 實施例’罐MOS電晶體元件30為PM〇s電晶體，其間極321 為p摻雜多晶石夕閘極。在閘極321的側壁上則可以形成有側壁子 330。源極摻雜區323可以包括一輕摻雜汲極區(iighdyd〇ped dram ’簡稱為LDD)323a，汲極摻雜區324可以包括一輕摻雜汲極 區324a。輕摻雜汲極區323a與輕摻雜汲極區324a之間即為一平 面P通道326。 凊參閱第2圖及第3圖，其繪示的是本發明較佳實施例形成 . 鬲壓M0S電晶體元件20的不對稱閘極氧化層225的方法的示意 圖，其中，仍沿用相同的符號來表示相同的區域或結構。首先， 如第2圖所示，在半導體基底1〇2上形成有一氧化矽墊層4〇2以 及-II化石夕塾層404。接著，利用微影及触刻製程，分別在記憶體 陣列區域1〇〇以及週邊電路區域200内的半導體基底1〇2中形成 一閘極溝渠122以及一閘極溝渠222。同樣的，閘極溝渠122可區 分為垂直側壁部分122a以及U型底部122b，閘極溝渠222可區 12 1355069 * 分為垂直側壁部分222a以及U型底部222b。 曰其中，開極溝渠m與間極溝渠222的深度實質上相同，但 疋閘極溝渠222喊度W2則大閘極溝渠122的寬度你 據本發明之較佳實施例，閘極溝渠222的寬度^約介 •至1600埃之間，閘極溝渠122的寬度Wl約介於埃至㈣埃 之間。 、 - 接著’進行一斜角度離子佈植製程，將預定的摻質，例如氟， -以預定的入射角度卜植入閘極溝渠222的單邊的垂直側辟部分 222a中。根擄本發明之較佳實施例，一小部分的u型底部土2221) 可以被植入前述的預定的摻質。 根據本發明之雛，前述的斜角度離子佈植製程的入 射角度Θ可介於〇度至30度之間，較佳為1〇度至15度^間。此 參 外’前述預定的摻質需能夠造成後續_氧化層成長速率的差異。 • 由於5己憶體陣列區域】00内的閘極溝渠122的寬度比週邊電 .路區域200内的閘極溝渠222的寬度小很多，因此，^的斜角 度離子佈植製程實質上並不會將該預定的換質植入到閉極溝渠 122的垂直側壁部分122a以及u型底部122b，特別是間極溝渠 122的U型底部〗22b。 13 1355069 ，第3圖所示’在完成斜角度離子佈植製程之後，隨即進行 一熱氧化製程，例如，爐管製程，在閘極溝渠122與閘極溝渠切 内分別形成·氧化層125以及·氧化層奶。由於在間極溝準 瓜的單邊的垂直側壁部分孤中已植人氟，氧化速率會較未植 入鼠的閘極麟222的其它部位快，因此會形成較厚的間極氧化 層 225a。 • 最、、;的閘極氧化層225具有兩種不同的厚度，呈現出不對稱 結構。根據本發明之較佳實_，閘極氧化層225a的厚度約介於 150埃至300埃之間，而開極氧化層225b的厚度約介於烈埃至 60埃之間。 如刚所述’由於前述的斜角度離子佈植製程實質上並不會將 該預定的換質植入到閘極溝渠122的垂直側壁部分既以及㈣ 底部122b，特別是閘極溝渠122㈣型底部⑽，因此，此斜角 度離子佈㈣錄本上對於記鐘陣顺域丨⑽内的電晶體製程 並無影響。 以上戶斤述僅為本發明之較佳實施例，凡依本發明申請專利範 圍所做之均¥變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖為依擄本發明較佳實施例所繪示&DRAM元件部分區域的 1355069 别面示意圖。 第2圖及g3 m的是本發明她實關賴綠體s電晶體 元件的不對稱閘極氧化層的方法示意圖。 【主要元件符號說明】
1 DRAM元件 10 記憶胞 12 延伸U型通道元件 14 深溝渠電容 20 高壓MOS電晶體元件 30 低壓MOS電晶體元件 100 記憶體陣列區域 102 半導體基底 104 淺溝絕緣結構 121 凹入式閘極 122 閘極溝渠 122a 垂直側壁部分 122b U型底部 123 源極換雜區 124 汲極摻雜區 125 閘極氧化層 126 U型通道 130 接觸插塞 141 摻雜多晶矽層 142 側壁電容介電層 143 單邊埋入導電帶 144 溝渠上蓋層 145 擴散區域 221 凹入式閘極 222 閘極溝渠 222a 垂直側壁部分 222b u型底部 223 源極#雜區 223a N+#雜區 224 汲極摻雜區 224a N+摻雜區 1355069 225 閘極氧化層 225a 閘極氧化層 225b 閘極氧化層 226 U型通道 321 閘極 323 P+源極摻雜區 323a 輕摻雜没極區 324 P+汲極摻雜區 324a 輕摻雜没極區 325 閘極氧化層 326 平面P通道 330 側壁子 402 氧化矽墊層 404 氮化矽墊層 16

Claims (1)

  1. 申請專利範圍：
    21
    100年修正替換頁 Α·—種動態隨機存取記憶體元件，包含有： 半導體基底，該半導體基底包財—記憶辦舰域和 邊電路區域，該記.隨陣艇域設有―第—凹人式閘極而該。 電路區域設有-第二凹人式閘極，其中該第—凹人式閘極和該第 二凹入式閘極皆嵌入於該半導體基底中； -第-閘極氧化層’介於該第—狀式閘極和該半導體基底 間，該第一閘極氧化層具有一均勻厚度；以及 ~ 間 同的厚度。 -第厂閘極氧化層，介於該第二凹人式酿和該铸體基底 ’該第二_氧化層位於該第二凹人式閘極兩侧的部位具有 2·如申,#專概圍第丨顧述之動態隨機存取記憶體元件 該第-凹人式閘極之寬度小於該第二凹人式閘極之寬度。、 其中 \如申凊專利翻第1項所述之動騎機存取記憶體元件 該第和第—I^人胡極為—N+摻雜多晶梦閉極。 4.如申請專利範圍第】項所述之動態隨機存 該第一和第1人式雜包含有多_、金錢者其組合中 »·如申#專利範圍第2、3或4項所述之動 ，，其中該第1入式閘極和該第二凹入式二】=: 1355069 100年9月22日修正替換頁 底的深度介於1500埃至2500埃之間。 Η 、圖式：
    18
TW096141857A 2007-11-06 2007-11-06 Dram device TWI355069B (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
TW096141857A TWI355069B (en) 2007-11-06 2007-11-06 Dram device
US12/049,385 US7948028B2 (en) 2007-11-06 2008-03-17 DRAM device having a gate dielectric layer with multiple thicknesses
JP2008115410A JP4857307B2 (ja) 2007-11-06 2008-04-25 Ｄｒａｍ素子
DE102008023622.5A DE102008023622B4 (de) 2007-11-06 2008-05-15 Verfahren zum Herstellen einer DRAM-Vorrichtung mit einer dielektrischen Gate-Schicht mit mehreren Dicken

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW096141857A TWI355069B (en) 2007-11-06 2007-11-06 Dram device

Publications (2)

Publication Number Publication Date
TW200921902A TW200921902A (en) 2009-05-16
TWI355069B true TWI355069B (en) 2011-12-21

Family

ID=40530736

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096141857A TWI355069B (en) 2007-11-06 2007-11-06 Dram device

Country Status (4)

Country Link
US (1) US7948028B2 (zh)
JP (1) JP4857307B2 (zh)
DE (1) DE102008023622B4 (zh)
TW (1) TWI355069B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI680570B (zh) * 2018-12-04 2019-12-21 南亞科技股份有限公司 記憶體裝置及其形成方法

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2555241A1 (en) * 2011-08-02 2013-02-06 Nxp B.V. IC die, semiconductor package, printed circuit board and IC die manufacturing method
KR101862345B1 (ko) 2012-02-27 2018-07-05 삼성전자주식회사 모오스 전계효과 트랜지스터를 포함하는 반도체 장치 및 그 제조 방법
FR3018139B1 (fr) 2014-02-28 2018-04-27 Stmicroelectronics (Rousset) Sas Circuit integre a composants, par exemple transistors nmos, a regions actives a contraintes en compression relachees
FR3021457B1 (fr) * 2014-05-21 2017-10-13 St Microelectronics Rousset Composant, par exemple transistor nmos, a region active a contraintes en compression relachees, et condensateur de decouplage associe
FR3025335B1 (fr) 2014-08-29 2016-09-23 Stmicroelectronics Rousset Procede de fabrication d'un circuit integre rendant plus difficile une retro-conception du circuit integre et circuit integre correspondant
US9412667B2 (en) 2014-11-25 2016-08-09 International Business Machines Corporation Asymmetric high-k dielectric for reducing gate induced drain leakage
US9722092B2 (en) 2015-02-25 2017-08-01 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having a stacked metal oxide
US9379197B1 (en) * 2015-10-07 2016-06-28 Inotera Memories, Inc. Recess array device
US10224407B2 (en) 2017-02-28 2019-03-05 Sandisk Technologies Llc High voltage field effect transistor with laterally extended gate dielectric and method of making thereof
US11569371B2 (en) 2017-05-25 2023-01-31 Dynex Semiconductor Limited Semiconductor device
US11257916B2 (en) * 2019-03-14 2022-02-22 Semiconductor Components Industries, Llc Electronic device having multi-thickness gate insulator
US11690216B2 (en) * 2019-12-13 2023-06-27 Micron Technology, Inc. Structure to reduce bending in semiconductor devices
KR20220075859A (ko) 2020-11-30 2022-06-08 삼성전자주식회사 반도체 메모리 장치
CN113678253A (zh) * 2021-06-30 2021-11-19 长江存储科技有限责任公司 具有凹陷栅极晶体管的外围电路及其形成方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5640034A (en) * 1992-05-18 1997-06-17 Texas Instruments Incorporated Top-drain trench based resurf DMOS transistor structure
GB9917099D0 (en) * 1999-07-22 1999-09-22 Koninkl Philips Electronics Nv Cellular trench-gate field-effect transistors
JP4860022B2 (ja) * 2000-01-25 2012-01-25 エルピーダメモリ株式会社 半導体集積回路装置の製造方法
TW591756B (en) * 2003-06-05 2004-06-11 Nanya Technology Corp Method of fabricating a memory cell with a single sided buried strap
KR100511045B1 (ko) * 2003-07-14 2005-08-30 삼성전자주식회사 리세스된 게이트 전극을 갖는 반도체 소자의 집적방법
US7294879B2 (en) * 2003-07-18 2007-11-13 International Business Machines Corporation Vertical MOSFET with dual work function materials
JP4552603B2 (ja) * 2004-11-08 2010-09-29 エルピーダメモリ株式会社 半導体装置の製造方法
US8188551B2 (en) * 2005-09-30 2012-05-29 Infineon Technologies Ag Semiconductor devices and methods of manufacture thereof
KR100675281B1 (ko) * 2005-09-05 2007-01-29 삼성전자주식회사 디커플링 캐패시터를 갖는 반도체 소자 및 그 제조방법
US20070132016A1 (en) * 2005-12-12 2007-06-14 Elwin Matthew P Trench ld structure
TWI309066B (en) 2005-12-19 2009-04-21 Nanya Technology Corp Semiconductor device having a trench gate the fabricating method of the same
KR100704475B1 (ko) * 2005-12-28 2007-04-09 주식회사 하이닉스반도체 듀얼 폴리 리세스 게이트를 갖는 반도체 소자의 제조방법
US8159035B2 (en) * 2007-07-09 2012-04-17 Taiwan Semiconductor Manufacturing Co., Ltd. Metal gates of PMOS devices having high work functions

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI680570B (zh) * 2018-12-04 2019-12-21 南亞科技股份有限公司 記憶體裝置及其形成方法

Also Published As

Publication number Publication date
US20090114966A1 (en) 2009-05-07
US7948028B2 (en) 2011-05-24
JP4857307B2 (ja) 2012-01-18
JP2009117793A (ja) 2009-05-28
DE102008023622A1 (de) 2009-05-14
DE102008023622B4 (de) 2014-08-28
TW200921902A (en) 2009-05-16

Similar Documents

Publication Publication Date Title
TWI355069B (en) Dram device
US8343829B2 (en) Recessed-gate transistor device having a dielectric layer with multi thicknesses and method of making the same
TWI323498B (en) Recessed gate mos transistor device and method of making the same
JP5989985B2 (ja) 埋没ジャンクションを有する垂直型トランジスタ及びその形成方法
TW480712B (en) Integrated memory cell and method of fabrication
TWI278068B (en) Growth controlled vertical transistor
TW200411910A (en) A stacked gate flash memory and the method of fabricating the same
TW571384B (en) Semiconductor apparatus, transistor-capacitor memory cell and method of making a semiconductor structure
TW200917497A (en) Nonvolatile semiconductor device and method of manufacturing the same
TW474013B (en) A nonvolatile memory device with a high work function floating-gate and method of fabrication
JP2008135458A (ja) 半導体装置及びその製造方法
TW200805506A (en) Method for making a raised vertical channel transistor device
TW201203468A (en) Semiconductor device
TWI320207B (en) Method of fabricating metal oxide semiconductor
CN108565263B (zh) 半导体器件及其制作方法
TWI249185B (en) Semiconductor device and method of manufacturing the same
TW200945561A (en) Semiconductor device and method for fabricating the same
TWI362114B (en) Structure and method for low vss resistance and reduced dibl in a floating gate memory cell
TW200921854A (en) Non-volatile memory and method of manufacturing thereof
TW516233B (en) MOS-transistor in a one-transistor memory-cells with a local thicker gate-oxide and its production method
TWI297183B (en) Method for fabricating recessed gate mos transistor device
TWI374543B (en) Recessed channel transistor and method for preparing the same
TWI294664B (en) Method of fabricating self-aligned gate trench utilizing asymmetric poly spacer
TW452970B (en) Structure and fabrication process of semiconductor trench-type capacitor
CN104617140B (zh) 凹入式沟道存取晶体管器件及其制作方法